Preliminary
GS8180D18D-333/300/250/200
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ 2x2B4
SigmaQuad SRAM
200 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
•Simultaneous Read and Write SigmaQuad™ Interface
•JEDEC-standard pinout and package
•Dual Double Data Rate interface
•Echo Clock outputs track data output drivers
•Byte Write controls sampled at data-in time
•Burst of 4 Read and Write
•1.8 V +150/–100 mV core power supply
•1.5 V or 1.8 V HSTL Interface
•Pipelined read operation
•Fully coherent read and write pipelines
•ZQ mode pin for programmable output drive strength
•IEEE 1149.1 JTAG-compliant Boundary Scan
•165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
•Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
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- 333 |
-300 |
-250 |
-200 |
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tKHKH |
3.0 ns |
3.3 ns |
4 ns |
5 ns |
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tKHQV |
1.6 ns |
1.8 ns |
2.1 ns |
2.3 ns |
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SigmaRAM™ Family Overview
GS8180D18 are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
SigmaQuad SRAMs are offered in a number of configurations. Some emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst of 2 version is also offered. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand.
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1
Clocking and Addressing Schemes
A Σ 2x2B4 SigmaQuad SRAM is a synchronous device. It employs two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Σ 2x2B4 SigmaQuad SRAM also supplies Echo Clock outputs, CQ and CQ, that are synchronized with read data output. When used in a source synchronous clocking scheme, these Echo Clock outputs can be used to fire input registers at the data’s destination.
Because Separate I/O Σ 2x2B4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a
Σ 2x2B4 RAM is always two address pins less than the advertised index depth (e.g., the 1M x 18 has a 256K addressable index).
Rev: 2.00f 6/2002 |
1/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180D18D-333/300/250/200
1M x 18 SigmaQuad SRAM — Top View
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9 |
10 |
11 |
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MCL/SA |
NC/SA |
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MCL/SA |
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A |
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CQ |
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W |
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BW1 |
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K |
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NC |
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R |
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SA |
CQ |
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(144Mb) |
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B |
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NC |
Q9 |
D9 |
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SA |
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NC |
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K |
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SA |
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NC |
NC |
Q8 |
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BW0 |
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C |
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NC |
NC |
D10 |
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VSS |
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SA |
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NC |
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SA |
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VSS |
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NC |
Q7 |
D8 |
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D |
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NC |
D11 |
Q10 |
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VSS |
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VSS |
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VSS |
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VSS |
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VSS |
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NC |
NC |
D7 |
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E |
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NC |
NC |
Q11 |
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VDDQ |
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VSS |
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VSS |
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VSS |
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VDDQ |
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NC |
D6 |
Q6 |
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F |
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NC |
Q12 |
D12 |
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VDDQ |
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VDD |
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VSS |
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VDD |
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VDDQ |
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NC |
NC |
Q5 |
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G |
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NC |
D13 |
Q13 |
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VDDQ |
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VDD |
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VSS |
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VDD |
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VDDQ |
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NC |
NC |
D5 |
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H |
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NC |
VREF |
VDDQ |
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VDDQ |
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VDD |
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VSS |
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VDD |
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VDDQ |
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VDDQ |
VREF |
ZQ |
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J |
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NC |
NC |
D14 |
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VDDQ |
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VDD |
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VSS |
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VDD |
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VDDQ |
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NC |
Q4 |
D4 |
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K |
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NC |
NC |
Q14 |
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VDDQ |
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VDD |
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VSS |
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VDD |
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VDDQ |
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NC |
D3 |
Q3 |
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L |
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NC |
Q15 |
D15 |
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VDDQ |
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VSS |
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VSS |
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VSS |
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VDDQ |
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NC |
NC |
Q2 |
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M |
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NC |
NC |
D16 |
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VSS |
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VSS |
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VSS |
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VSS |
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VSS |
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NC |
Q1 |
D2 |
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N |
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NC |
D17 |
Q16 |
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VSS |
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SA |
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SA |
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SA |
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VSS |
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NC |
NC |
D1 |
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P |
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NC |
NC |
Q17 |
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SA |
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SA |
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C |
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SA |
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SA |
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NC |
D0 |
Q0 |
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R |
TDO |
TCK |
SA |
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SA |
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SA |
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SA |
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SA |
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SA |
TMS |
TDI |
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C |
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11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch |
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Notes:
1.Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3.MCL = Must Connect Low
4.It is recommended that H1 be tied low for compatibility with future devices.
Rev: 2.00f 6/2002 |
2/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180D18D-333/300/250/200
Pin Description Table
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Symbol |
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Description |
Type |
Comments |
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SA |
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Synchronous Address Inputs |
Input |
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— |
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NC |
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No Connect |
— |
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— |
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Synchronous Read |
Input |
Active Low |
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R |
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Synchronous Write |
Input |
Active Low |
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W |
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Active Low |
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BW0–BW1 |
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Synchronous Byte Writes |
Input |
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K |
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Input Clock |
Input |
Active High |
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Input Clock |
Input |
Active Low |
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K |
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C |
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Output Clock |
Input |
Active High |
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Output Clock |
Input |
Active Low |
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C |
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TMS |
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Test Mode Select |
Input |
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— |
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TDI |
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Test Data Input |
Input |
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— |
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TCK |
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Test Clock Input |
Input |
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— |
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TDO |
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Test Data Output |
Output |
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— |
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VREF |
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HSTL Input Reference Voltage |
Input |
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— |
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ZQ |
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Output Impedance Matching Input |
Input |
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— |
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MCL |
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Must Connect Low |
— |
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— |
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CQ |
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Synchronous Echo Clock Output |
Output |
Echoes C or K Clock |
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Synchronous Echo Clock-bar Output |
Output |
Echoes |
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or |
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Clock |
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CQ |
C |
K |
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D0–D17 |
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Synchronous Data Inputs |
Input |
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— |
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Q0–Q17 |
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Synchronous Data Outputs |
Output |
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— |
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VDD |
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Power Supply |
Supply |
2.5 V Nominal |
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VDDQ |
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Isolated Output Buffer Supply |
Supply |
1.5 V Nominal |
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VSS |
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Power Supply: Ground |
Supply |
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— |
Note: NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half.
A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the
Rev: 2.00f 6/2002 |
3/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180D18D-333/300/250/200
same internal circuits. Differences between the truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand.
Alternating Read-Write Operations
SigmaQuad SRAMs follow a few simple rules of operation.
-Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
-Read or Write data transfers in progress may not be interrupted and re-started.
-R and W high always deselects the RAM but does not disable the CQ or CQ output pins.
-All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.
Rev: 2.00f 6/2002 |
4/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180D18D-333/300/250/200
Σ 2x2B4 SigmaQuad SRAM DDR Read
The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. The four resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C, the rising edge of C after that, the next rising edge of C, and finally by the next rising edge of C.
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Σ |
2x2B4 Double Data Rate SigmaQuad SRAM Read First |
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D w g R e v . G |
N o O p |
R ead |
W rite |
R e a d |
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W rite |
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R e a d |
K |
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/K |
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A d d re s s |
X X |
B |
C |
D |
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E |
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F |
/R |
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/W |
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D C 0 |
D C 1 |
D C 2 |
D C 3 |
D E 0 |
D |
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C |
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/C |
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Q B 0 |
Q B 1 |
Q B 2 |
Q B 3 |
Q D 0 |
Q |
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C Q |
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/C Q |
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Rev: 2.00f 6/2002 |
5/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180D18D-333/300/250/200
Σ 2x2B4 SigmaQuad SRAM DDR Write
The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K.
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Σ |
2x2B4 Double Data Rate SigmaQuad SRAM Write First |
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D w g R e v . G |
N o O p |
W rite |
R e a d |
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W r i te |
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R e a d |
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W r i te |
K |
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/ K |
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A d d r e s s |
X X |
B |
C |
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D |
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F |
/ R |
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/ W |
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/ B W x |
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D B 0 |
D B 1 |
D B 2 |
D B 3 |
D D 0 |
D D 1 |
D D 2 |
D |
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C |
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/ C |
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Q C 0 |
Q C 1 |
Q C 2 |
Q |
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C Q |
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/ C Q |
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Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.
Rev: 2.00f 6/2002 |
6/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180D18D-333/300/250/200
Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample |
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BW0 |
BW1 |
D0–D8 |
D9–D17 |
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Time |
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Beat 1 |
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0 |
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1 |
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Data In |
Don’t Care |
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Beat 2 |
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1 |
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0 |
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Don’t Care |
Data In |
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Beat 3 |
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0 |
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0 |
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Data In |
Data In |
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Beat 4 |
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1 |
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0 |
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Don’t Care |
Data In |
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Resulting Write Operation
Byte 1 |
Byte 2 |
Byte 3 |
Byte 4 |
Byte 5 |
Byte 6 |
Byte 7 |
Byte 8 |
D0–D8 |
D9–D17 |
D0–D8 |
D9–D17 |
D0–D8 |
D9–D17 |
D0–D8 |
D9–D17 |
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Written |
Unchanged |
Unchanged |
Written |
Written |
Written |
Unchanged |
Written |
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Output Register Control
SigmaQuad SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.
Echo Clock
SigmaQuad SRAMs feature Echo Clock outputs, CQ and CQ, that track the performance of the output drivers. The Echo Clocks are delayed copies of the Output Register clocks, C and C or K and K (if the C and C clock inputs are tied high). Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaQuad SRAMs provide both in-phase, or true, Echo Clock output, CQ and inverted Echo Clock output CQ.
Echo Clocks are always active. Neither inhibiting reads via holding R high, nor deselection of the RAM via holding R and W high will deactivate the Echo Clocks.
Rev: 2.00f 6/2002 |
7/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8180D18D-333/300/250/200
Example Four Bank Depth Expansion Schematic
R3
W3
R2
W2
R1
W1
R0
W0
A0–An |
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K |
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D1–Dn |
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Bank 0 |
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Bank 2 |
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A |
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A |
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A |
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W |
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W |
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W |
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R |
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R |
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K |
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K |
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K |
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D |
Q |
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D |
Q |
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D |
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C |
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C |
CQ |
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C |
CQ |
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C |
CQ |
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CQ0 |
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CQ1 |
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CQ2
CQ3
Q1–Qn
Bank 3
A
W
R
K
D Q C CQ
Note: For simplicity BWn, K, C and CQ are not shown.
Rev: 2.00f 6/2002 |
8/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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Preliminary |
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GS8180D18D-333/300/250/200 |
|||||
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Σ |
2x2B4 SigmaQuad SRAM Depth Expansion |
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|||||
Dwg Rev. G |
No Op |
Read |
Write |
Read |
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Write |
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Read |
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Write |
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- |
Bank 2 |
Bank 2 |
Bank 1 |
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Bank 2 |
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Bank 1 |
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Bank 1 |
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K |
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/K |
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Address |
XX |
B |
C |
D |
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E |
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F |
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G |
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/R1 |
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/W1 |
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/R2 |
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/W2 |
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D |
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Bank 1 |
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D |
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DC0 |
DC1 |
DC2 |
DC3 |
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DE0 |
DE1 |
DE2 |
DE3 |
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Bank 2 |
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C |
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/C |
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Q |
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QD0 |
QD1 |
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QD2 |
QD3 |
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Bank 1 |
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Q |
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QB0 |
QB1 |
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QB2 |
QB3 |
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Bank 2 |
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Q Bank 1 + |
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QB0 |
QB1 |
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QB2 |
QB3 |
QD0 |
QD1 |
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QD2 |
QD3 |
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Q Bank 2 |
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CQ |
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Bank 1 |
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CQ |
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Bank 2 |
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|
Rev: 2.00f 6/2002 |
9/27 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.