GSI GS8170LW72C-250I, GS8170LW72C-250, GS8170LW36C-333I, GS8170LW36C-333, GS8170LW36C-300I Datasheet

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Preliminary

GS8170LW18/36/72C-333/300/250

209-Bump BGA

Commercial Temp

Industrial Temp

18Mb Σ 1x1 Late Write

SigmaRAM™ SRAM

250 MHz–333 MHz

1.8 V VDD

1.8 V and 1.5 V I/O

Features

Late Write mode

Pipeline read operation

JEDEC-standard SigmaRAMpinout and package

1.8 V +150/–100 mV core power supply

1.5 V or 1.8 V I/O supply

Dual Cycle Deselect

Synchronous Burst operation

Fully coherent read and write pipelines

Echo Clock outputs track data output drivers

ZQ mode pin for user-selectable output drive strength

Byte write operation (9-bit bytes)

2 user-programmable chip enable inputs for easy depth expansion.

IEEE 1149.1 JTAG-compatible Boundary Scan

209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

-333

Pipeline mode

tKHKH

3.0 ns

tKHQV

1.6 ns

 

SigmaRAM Family Overview

GS8170LW18/36/72 SigmaRAMs (Σ RAM™) are built in compliance with the Σ RAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage CMOS I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

GSI's Σ RAMs are offered in a number of configurations that emulate other synchronous SRAMs, such as Burst RAMs, NBT, Late Write, or Double Data Rate (DDR) SRAMs. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering and write cueing. The Σ RAM family standard allows a user to implement the interface protocol best suited to the task at hand.

Bottom View

209-Bump, 14 mm x 22 mm BGA

1 mm Bump Pitch, 11 x 19 Bump Array

Functional Description

Because Σ RAMs are synchronous devices, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

This Σ RAM reads in Pipeline mode. In Pipeline mode, single data rate Σ RAMs incorporate a rising-edge-triggered output register. For read cycles, a pipelined SRAM’s output data is staged at the input of an edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

GS8170LW18/36/72C Σ RAMs are implemented with GSI's high performance CMOS technology and are packaged in a 209-bump BGA.

Rev: 1.01 7/2002

1/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

8170LW72C 256K x 72 Pinout

256K x 72 Common I/O—Top View

 

 

1

2

 

3

 

 

4

 

5

6

 

 

7

8

 

 

 

9

 

 

10

 

11

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQg

DQg

 

A

 

 

E2

A

ADV

A

 

 

E3

 

 

 

A

DQb

DQb

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

DQg

DQg

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

DQb

DQb

 

Bc

Bg

W

Bb

Bf

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

DQg

DQg

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

DQb

DQb

Bh

 

 

Bd

E1

 

Be

Ba

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(144M)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

DQg

DQg

VSS

 

NC

NC

MCL

NC

NC

 

VSS

DQb

DQb

E

DQg

 

DQc

VDDQ

 

VDDI

VDD

VDD

VDD

VDDI

 

VDDQ

 

DQf

DQb

F

DQc

 

DQc

VSS

 

VSS

VSS

ZQ

VSS

VSS

 

VSS

 

DQf

DQf

G

DQc

 

DQc

VDDQ

 

VDDQ

VDD

EP2

VDD

VDDQ

 

VDDQ

 

DQf

DQf

H

DQc

 

DQc

VSS

 

VSS

VSS

EP3

VSS

VSS

 

VSS

 

DQf

DQf

J

DQc

DQc

VDDQ

 

VDDQ

VDD

MCH

VDD

VDDQ

 

VDDQ

 

DQf

DQf

K

CQ2

 

 

 

CK

 

NC

VSS

MCL

VSS

NC

 

NC

 

 

 

CQ1

 

CQ2

CQ1

L

DQh

DQh

VDDQ

 

VDDQ

VDD

MCL

VDD

VDDQ

 

VDDQ

 

DQa

DQa

M

DQh

DQh

VSS

 

VSS

VSS

MCL

VSS

VSS

 

VSS

 

DQa

DQa

N

DQh

DQh

VDDQ

 

VDDQ

VDD

MCH

VDD

VDDQ

 

VDDQ

 

DQa

DQa

P

DQh

DQh

VSS

 

VSS

VSS

MCL

VSS

VSS

 

VSS

 

DQa

DQa

R

DQd

DQh

VDDQ

 

VDDI

VDD

VDD

VDD

VDDI

 

VDDQ

 

DQa

DQe

T

DQd

DQd

VSS

 

NC

NC

MCL

NC

NC

 

VSS

 

DQe

DQe

U

DQd

DQd

NC

 

 

A

NC

 

 

A

NC

 

 

A

 

NC

DQe

DQe

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(72M)

 

 

 

 

 

(36M)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

DQd

DQd

 

A

 

 

A

A

A1

A

 

 

A

 

 

 

A

 

DQe

DQe

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

DQd

DQd

TMS

 

TDI

A

A0

A

TDO

 

TCK

 

DQe

DQe

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• 2001.03

 

 

 

 

 

 

 

 

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

 

 

 

 

 

 

 

 

 

Rev: 1.01 7/2002

2/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

8170LW36C 512K x 36 Pinout

512K x 36 Common I/O—Top View

 

 

1

2

 

3

 

4

 

5

6

 

 

7

8

 

 

9

 

10

 

11

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

NC

 

A

 

 

E2

A

ADV

A

 

E3

 

 

A

DQb

DQb

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

NC

 

NC

 

 

 

 

NC

A

 

 

 

 

 

A

 

 

 

 

NC

DQb

DQb

 

Bc

W

Bb

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

NC

 

NC

NC

 

 

 

 

NC

 

 

 

 

 

NC

NC

 

 

 

 

DQb

DQb

 

 

Bd

E1

Ba

 

 

 

 

 

 

 

 

 

 

 

 

 

(144M)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

NC

 

NC

VSS

 

NC

NC

MCL

NC

NC

 

VSS

DQb

DQb

E

NC

 

DQc

VDDQ

 

VDDI

VDD

VDD

VDD

VDDI

 

VDDQ

 

NC

DQb

F

DQc

 

DQc

VSS

 

VSS

VSS

ZQ

VSS

VSS

 

VSS

 

NC

NC

G

DQc

 

DQc

VDDQ

 

VDDQ

VDD

EP2

VDD

VDDQ

 

VDDQ

 

NC

NC

H

DQc

 

DQc

VSS

 

VSS

VSS

EP3

VSS

VSS

 

VSS

 

NC

NC

J

DQc

 

DQc

VDDQ

 

VDDQ

VDD

MCH

VDD

VDDQ

 

VDDQ

 

NC

NC

K

CQ2

 

 

 

CK

 

NC

VSS

MCL

VSS

NC

 

NC

 

 

 

CQ1

 

CQ2

CQ1

L

NC

 

NC

VDDQ

 

VDDQ

VDD

MCL

VDD

VDDQ

 

VDDQ

 

DQa

DQa

M

NC

 

NC

VSS

 

VSS

VSS

MCL

VSS

VSS

 

VSS

 

DQa

DQa

N

NC

 

NC

VDDQ

 

VDDQ

VDD

MCH

VDD

VDDQ

 

VDDQ

 

DQa

DQa

P

NC

 

NC

VSS

 

VSS

VSS

MCL

VSS

VSS

 

VSS

 

DQa

DQa

R

DQd

 

NC

VDDQ

 

VDDI

VDD

VDD

VDD

VDDI

 

VDDQ

 

DQa

NC

T

DQd

DQd

VSS

 

NC

NC

MCL

NC

NC

 

VSS

 

NC

NC

U

DQd

DQd

NC

 

 

A

NC (72M)

 

 

A

NC (36M)

 

A

 

NC

 

NC

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

DQd

DQd

 

A

 

 

A

A

A1

A

 

A

 

 

A

 

NC

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

DQd

DQd

TMS

 

TDI

A

A0

A

TDO

 

TCK

 

NC

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• 2001.03

 

 

 

 

 

 

 

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

 

 

 

 

 

 

 

Rev: 1.01 7/2002

3/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

8170LW18 1M x 18 Pinout

1M x 18 Common I/O—Top View

 

 

1

2

 

3

 

4

5

6

 

 

7

8

 

9

 

10

11

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

NC

 

A

 

E2

A

ADV

A

E3

 

 

A

 

NC

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

NC

 

NC

 

 

 

 

NC

A

 

 

 

 

 

A

NC

 

NC

 

NC

 

NC

Bb

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

NC

 

NC

NC

 

NC

NC

 

 

 

 

 

A

NC

 

 

 

 

 

NC

 

NC

E1

Ba

 

 

 

 

 

 

 

 

 

 

 

(144M)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

NC

 

NC

VSS

 

NC

NC

MCL

NC

NC

 

VSS

 

NC

 

NC

E

NC

DQb

VDDQ

 

VDDI

VDD

VDD

VDD

VDDI

 

VDDQ

 

NC

 

NC

F

DQb

DQb

VSS

 

VSS

VSS

ZQ

VSS

VSS

 

VSS

 

NC

 

NC

G

DQb

DQb

VDDQ

 

VDDQ

VDD

EP2

VDD

VDDQ

 

VDDQ

 

NC

 

NC

H

DQb

DQb

VSS

 

VSS

VSS

EP3

VSS

VSS

 

VSS

 

NC

 

NC

J

DQb

DQb

VDDQ

 

VDDQ

VDD

MCH

VDD

VDDQ

 

VDDQ

 

NC

 

NC

K

CQ2

 

 

 

CK

 

NC

VSS

MCL

VSS

NC

 

NC

 

 

 

CQ1

 

CQ2

CQ1

L

NC

 

NC

VDDQ

 

VDDQ

VDD

MCL

VDD

VDDQ

 

VDDQ

 

DQa

 

DQa

M

NC

 

NC

VSS

 

VSS

VSS

MCL

VSS

VSS

 

VSS

 

DQa

 

DQa

N

NC

 

NC

VDDQ

 

VDDQ

VDD

MCH

VDD

VDDQ

 

VDDQ

 

DQa

 

DQa

P

NC

 

NC

VSS

 

VSS

VSS

MCL

VSS

VSS

 

VSS

 

DQa

 

DQa

R

NC

 

NC

VDDQ

 

VDDI

VDD

VDD

VDD

VDDI

 

VDDQ

 

DQa

 

NC

T

NC

 

NC

VSS

 

NC

NC

MCL

NC

NC

 

VSS

 

NC

 

NC

U

NC

 

NC

NC

 

A

NC

 

 

A

NC

A

 

NC

 

NC

 

NC

 

 

 

 

 

 

 

 

 

 

 

(72M)

 

 

 

 

 

(36M)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V

NC

 

NC

 

A

 

A

A

A1

A

A

 

 

A

 

NC

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

NC

 

NC

TMS

 

TDI

A

A0

A

TDO

 

TCK

 

NC

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• 2001.03

 

 

 

 

 

 

 

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

 

 

 

 

 

 

 

Rev: 1.01 7/2002

4/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

 

 

 

 

 

 

 

 

 

 

 

Preliminary

 

 

 

 

 

 

 

 

 

 

 

GS8170LW18/36/72C-333/300/250

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Description Table

 

 

 

 

 

 

 

 

Symbol

Description

Type

Comments

 

 

 

 

 

 

 

 

 

 

 

 

A

Address

Input

 

 

 

 

 

 

ADV

Advance

Input

Active High

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte Write Enable

Input

Active Low

 

 

 

Bx

 

 

CK

Clock

Input

Active High

 

 

 

 

 

 

 

 

CQ

Echo Clock

Output

Active High

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Echo Clock

Output

Active Low

 

 

CQ

 

 

DQ

Data I/O

Input/Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Enable

Input

Active Low

 

 

 

E1

 

E2 & E3

Chip Enable

Input

Programmable Active High or Low

 

 

 

 

 

 

EP2 & EP3

Chip Enable Program Pin

Input

 

 

 

 

 

 

TCK

Test Clock

Input

Active High

 

 

 

 

 

 

TDI

Test Data In

Input

 

 

 

 

 

 

TDO

Test Data Out

Output

 

 

 

 

 

 

TMS

Test Mode Select

Input

 

 

 

 

 

 

MCH

Must Connect High

Input

Active High

 

 

 

 

 

 

MCL

Must Connect Low

Input

Active Low

 

 

 

 

 

 

 

 

NC

No Connect

Not connected to die

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write

Input

Active Low

 

 

 

 

W

 

VDD

Core Power Supply

Input

1.8 V Nominal

 

VDDQ

Output Driver Power Supply

Input

1.8 V or 1.5 V Nominal

 

VDDI

Input Buffer Power Supply

Input

1.8 V or 1.5 V Nominal

 

VSS

Ground

Input

 

 

ZQ

Output Impedance Control

Input

Low = Low Impedance [High Drive]

 

 

High = High Impedance [Low Drive]

 

 

 

 

 

 

 

 

 

 

 

Rev: 1.01 7/2002

5/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Background

The central characteristics of Σ RAMs are that they are extremely fast and consume very little power. Because both operating and interface power is low, Σ RAMs can be implemented in a wide (x72) configuration, providing very high single package bandwidth (in excess of 20Gb/s in ordinary pipelined configuration) and very low random access latency (5 ns). The use of very low voltage circuits in the core and 1.8 V or 1.5 V interface voltages allow the speed, power and density performance of Σ RAMs.

The Σ RAM family of pinouts has been designed to support a number of different common read and write protocols. The following timing diagrams provide a quick comparison between single data rate read and write protocols options available in the context of the Σ RAM standard. This particular datasheet covers the single data rate (non-DDR), Late Write (LW) Σ RAM.

Common I/O SigmaRAM Family Mode Comparison—EW vs. LW vs. DLW

Σ 1x1Ep (Early Write - Pipelined Read)

CK

 

 

 

 

 

 

Address

A

B

C

D

E

F

Control

R

X

X

W

R

R

DQ

 

QA

 

DD

 

QE

CQ

 

 

 

 

 

 

Σ 1x1Lp (Late Write - Pipelined Read)

CK

 

 

 

 

 

 

Address

A

B

C

D

E

F

Control

R

Z

W

R

X

W

QA

DC

QD

DF

CQ

 

 

 

Σ 1x1Dp (Double Late Write - Pipelined Read)

CK

 

 

 

 

 

 

 

Address

A

B

C

D

E

F

 

Control

R

W

R

W

R

W

 

 

 

 

QA

 

QC

DD

QE

CQ

Note: R = Read, W = Write, Z = Deselect

The character of the applications for fast synchronous SRAMs in networking systems are extremely diverse. Σ RAMs have been developed to address the broad variety of applications in the networking market in a manner that can be supported with a unified development and manufacturing infrastructure. Σ RAMs address each of the bus protocol options commonly found in networking systems. This allows the Σ RAM to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use with older SRAMs, like the NBT, Late Write, or Double Data Rate SRAMs, as well as with new chip sets and ASICs that employ the Echo Clocks and realize the full potential of the Σ RAMs.

Rev: 1.01 7/2002

6/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Mode Selection Truth Table Standard

L6

M6

J6

Name

Function

Analogous to...

In This Data Sheet?

 

 

 

 

 

 

 

0

0

0

Σ 1x1Ef

Early Write, Flow through Read

Flow through Burst RAM

No

 

 

 

 

 

 

 

0

0

1

Σ 1x1Lf

Late Write, Flow through Read

Flow through NBT SRAM

No

 

 

 

 

 

 

 

0

1

0

 

RFU

 

n/a

 

 

 

 

 

 

 

0

1

1

Σ 1x2Lp

DDR

Double Data Rate SRAM

No

 

 

 

 

 

 

 

1

0

0

Σ 1x1Ep

Early Write, Pipeline Read

Pipelined Burst RAM

No

 

 

 

 

 

 

 

1

0

1

Σ 1x1Dp

Double Late Write, Pipeline Read

Pipelined NBT SRAM

No

 

 

 

 

 

 

 

1

1

0

Σ 1x1Lp

Late Write, Pipeline Read

Pipelined Late Write SRAM

Yes

 

 

 

 

 

 

 

1

1

1

 

RFU

n/a

 

 

 

 

 

 

 

All address, data and control inputs (with the exception of PE2, PE3, ZQ, and the mode pins, L6, M6, J6) are synchronized to rising clock edges. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or

E3 deactivates the Echo Clocks, CQ1–CQ2.

Rev: 1.01 7/2002

7/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Read Operations

Pipelined Read

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.

Single Data Rate Pipelined Read

 

Read

Deselect

Read

Read

Read

 

CK

 

 

 

 

 

 

Address

A

XX

C

D

E

F

ADV

 

 

 

 

 

 

/E1

 

 

 

 

 

 

/W

 

 

 

 

 

 

DQ

 

 

QA

QC

 

QD

CQ

 

 

 

 

 

 

 

 

 

 

Key

 

 

 

 

 

Hi-Z

Access

 

 

Rev: 1.01 7/2002

8/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

Preliminary

GS8170LW18/36/72C-333/300/250

Write Operations

Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.

Late Write

In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications.

SigmaRAM Late Write with Pipelined Read

 

Read

Deselect

Write

Read

Read

 

CK

 

 

 

 

 

 

Address

A

XX

C

D

E

F

ADV

 

 

 

 

 

 

/E1

 

 

 

 

 

 

/W

 

 

 

 

 

 

DQ

 

 

QA

DC

 

QD

CQ

 

 

 

 

 

 

 

 

 

 

Key

 

 

 

 

 

Hi-Z

Access

 

 

Rev: 1.01 7/2002

9/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

GSI GS8170LW72C-250I, GS8170LW72C-250, GS8170LW36C-333I, GS8170LW36C-333, GS8170LW36C-300I Datasheet

Preliminary

GS8170LW18/36/72C-333/300/250

Byte Write Control

The Byte Write Enable inputs (BX) determine which bytes will be written. All or none may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.

Example of x36 Byte Write Truth Table

 

Function

 

W

BA

BB

BC

BD

 

Read

 

H

X

X

X

X

 

Write Byte A

 

L

L

H

H

H

 

Write Byte B

 

L

H

L

H

H

 

Write Byte C

 

L

H

H

L

H

 

Write Byte D

 

L

H

H

H

L

 

Write all Bytes

 

L

L

L

L

L

 

Write Abort

 

L

H

H

H

H

 

Byte Write Control Example with x18 SigmaRAM Late Write RAM

 

 

Write

Write

Write

Non-Write

 

Write

 

CK

 

 

 

 

 

 

 

Address

A

B

C

D

 

E

F

ADV

 

 

 

 

 

 

 

/E1

 

 

 

 

 

 

 

ADV

 

 

 

 

 

 

 

/BA

 

 

 

 

 

 

 

/BB

 

 

 

 

 

 

 

 

 

DA

DB

 

 

 

DE

DQA0-DQA8

 

 

 

 

 

 

 

 

 

DA

 

DC

 

 

 

DQB0-DQB8

 

 

 

 

 

 

 

CQ

Rev: 1.01 7/2002

10/33

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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