Preliminary
GS8170DD18/36C-333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ 1x2Lp Double Data Rate
SigmaRAM™ SRAM
250 MHz–333 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
•Double Data Rate Read and Write mode
•JEDEC-standard SigmaRAM™ pinout and package
•1.8 V +150/–100 mV core power supply
•1.5 V or 1.8 V I/O supply
•Pipelined read operation
•Fully coherent read and write pipelines
•Echo Clock outputs track data output drivers
•ZQ mode pin for user-selectable output drive strength
•2 user-programmable chip enable inputs for easy depth expansion
•IEEE 1149.1 JTAG-compatible Boundary Scan
•209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
•Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
-333
Pipeline mode |
tKHKH |
3.0 ns |
|
tKHQV |
1.6 ns |
||
|
SigmaRAM Family Overview
GS8170DD18/36 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage CMOS I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
GSI's Σ RAMs are offered in a number of configurations that emulate other synchronous SRAMs, such as Burst RAMs, NBT, Late Write, or Double Data Rate (DDR) SRAMs. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering and write cueing. The
Σ RAM™ family standard allows a user to implement the interface protocol best suited to the task at hand.
Functional Description
Because SigmaRAMs are synchronous devices, address and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. In
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
DDR mode the device captures Data In on both rising and falling edges of clock and drives data on both clock edges as well.
Because the DDR Σ RAM always transfers data in two halves, A0 is internally set to 0 for the first half of each read or write transfer, and automatically incremented to 1 for the falling edge transfer. The address field of a DDR Σ RAM is always one address pin less than the advertised index depth (e.g., the 1M x 18 has a 512k addressable index).
In Pipeline mode, Single Data Rate (SDR) Σ RAMs incorporate a rising-edge-triggered output register. In DDR mode, risingand falling-edge-triggered output registers are employed. For read cycles, a DDR SRAM’s output data is staged at the input of an edge-triggered output register during the access cycle and then released to the output drivers at the next rising and subsequent falling edge of clock.
GS817x18/36/72B Σ RAMs are implemented with GSI's high performance CMOS technology and are packaged in a 209bump BGA.
Rev: 1.00e 6/2002 |
1/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DD18/36C-333/300/250
8170DD36 512K x 36 Pinout
512K x 36 Common I/O—Top View
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1 |
2 |
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3 |
4 |
5 |
6 |
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7 |
8 |
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9 |
10 |
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11 |
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A |
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NC |
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NC |
A |
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E2 |
A |
ADV |
A |
E3 |
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A |
DQb |
DQb |
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B |
NC |
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NC |
MCL |
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NC |
A |
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A |
MCL |
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NC |
DQb |
DQb |
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W |
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C |
NC |
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NC |
NC |
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MCL |
NC |
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NC |
NC |
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MCL |
DQb |
DQb |
||||
E1 |
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(144M) |
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D |
NC |
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NC |
VSS |
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NC |
NC |
MCL |
NC |
NC |
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VSS |
DQb |
DQb |
||||||||
E |
NC |
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DQc |
VDDQ |
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VDDI |
VDD |
VDD |
VDD |
VDDI |
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VDDQ |
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NC |
DQb |
|||||||
F |
DQc |
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DQc |
VSS |
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VSS |
VSS |
ZQ |
VSS |
VSS |
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VSS |
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NC |
NC |
|||||||
G |
DQc |
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DQc |
VDDQ |
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VDDQ |
VDD |
EP2 |
VDD |
VDDQ |
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VDDQ |
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NC |
NC |
|||||||
H |
DQc |
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DQc |
VSS |
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VSS |
VSS |
EP3 |
VSS |
VSS |
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VSS |
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NC |
NC |
|||||||
J |
DQc |
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DQc |
VDDQ |
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VDDQ |
VDD |
MCH |
VDD |
VDDQ |
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VDDQ |
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NC |
NC |
|||||||
K |
CQ2 |
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CK |
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NC |
VSS |
MCL |
VSS |
NC |
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NC |
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CQ1 |
|||||
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CQ2 |
CQ1 |
||||||||||||||||||||
L |
NC |
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NC |
VDDQ |
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VDDQ |
VDD |
MCL |
VDD |
VDDQ |
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VDDQ |
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DQa |
DQa |
|||||||
M |
NC |
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NC |
VSS |
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VSS |
VSS |
MCH |
VSS |
VSS |
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VSS |
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DQa |
DQa |
|||||||
N |
NC |
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NC |
VDDQ |
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VDDQ |
VDD |
MCH |
VDD |
VDDQ |
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VDDQ |
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DQa |
DQa |
|||||||
P |
NC |
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NC |
VSS |
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VSS |
VSS |
MCL |
VSS |
VSS |
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VSS |
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DQa |
DQa |
|||||||
R |
DQd |
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NC |
VDDQ |
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VDDI |
VDD |
VDD |
VDD |
VDDI |
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VDDQ |
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DQa |
NC |
|||||||
T |
DQd |
DQd |
VSS |
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NC |
NC |
MCL |
NC |
NC |
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VSS |
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NC |
NC |
||||||||
U |
DQd |
DQd |
NC |
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A |
NC (72M) |
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A |
NC (36M) |
A |
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NC |
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NC |
NC |
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V |
DQd |
DQd |
A |
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A |
A |
A1 |
A |
A |
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A |
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NC |
NC |
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W |
DQd |
DQd |
TMS |
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TDI |
A |
MCL |
A |
TDO |
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TCK |
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NC |
NC |
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• 2001.03 |
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch |
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|
Rev: 1.00e 6/2002 |
2/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DD18/36C-333/300/250
8170DD18 1M x 18 Pinout
1M x 18 Common I/O—Top View
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1 |
2 |
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3 |
4 |
5 |
6 |
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7 |
8 |
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9 |
10 |
11 |
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A |
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NC |
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NC |
A |
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E2 |
A |
ADV |
A |
E3 |
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A |
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NC |
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NC |
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B |
NC |
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NC |
MCL |
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NC |
A |
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A |
NC |
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NC |
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NC |
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NC |
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W |
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C |
NC |
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NC |
NC |
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NC |
NC |
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A |
NC |
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MCL |
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NC |
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NC |
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E1 |
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(144M) |
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D |
NC |
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NC |
VSS |
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NC |
NC |
MCL |
NC |
NC |
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VSS |
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NC |
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NC |
||||||
E |
NC |
DQb |
VDDQ |
|
VDDI |
VDD |
VDD |
VDD |
VDDI |
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VDDQ |
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NC |
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NC |
|||||||
F |
DQb |
DQb |
VSS |
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VSS |
VSS |
ZQ |
VSS |
VSS |
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VSS |
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NC |
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NC |
|||||||
G |
DQb |
DQb |
VDDQ |
|
VDDQ |
VDD |
EP2 |
VDD |
VDDQ |
|
VDDQ |
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NC |
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NC |
|||||||
H |
DQb |
DQb |
VSS |
|
VSS |
VSS |
EP3 |
VSS |
VSS |
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VSS |
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NC |
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NC |
|||||||
J |
DQb |
DQb |
VDDQ |
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VDDQ |
VDD |
MCH |
VDD |
VDDQ |
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VDDQ |
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NC |
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NC |
|||||||
K |
CQ2 |
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CK |
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NC |
VSS |
MCL |
VSS |
NC |
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NC |
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CQ1 |
|||||
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CQ2 |
CQ1 |
||||||||||||||||||||
L |
NC |
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NC |
VDDQ |
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VDDQ |
VDD |
MCL |
VDD |
VDDQ |
|
VDDQ |
|
DQa |
|
DQa |
||||||
M |
NC |
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NC |
VSS |
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VSS |
VSS |
MCH |
VSS |
VSS |
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VSS |
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DQa |
|
DQa |
||||||
N |
NC |
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NC |
VDDQ |
|
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
|
VDDQ |
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DQa |
|
DQa |
||||||
P |
NC |
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NC |
VSS |
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VSS |
VSS |
MCL |
VSS |
VSS |
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VSS |
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DQa |
|
DQa |
||||||
R |
NC |
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NC |
VDDQ |
|
VDDI |
VDD |
VDD |
VDD |
VDDI |
|
VDDQ |
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DQa |
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NC |
||||||
T |
NC |
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NC |
VSS |
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NC |
NC |
MCL |
NC |
NC |
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VSS |
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NC |
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NC |
||||||
U |
NC |
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NC |
NC |
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A |
NC |
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A |
NC |
A |
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NC |
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NC |
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NC |
||||
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(72M) |
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(36M) |
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|||||
V |
NC |
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NC |
A |
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A |
A |
A1 |
A |
A |
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A |
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NC |
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NC |
||||||
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W |
NC |
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NC |
TMS |
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TDI |
A |
MCL |
A |
TDO |
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TCK |
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NC |
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NC |
||||||
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||||
• 2001.03 |
|
|
|
|
|
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch |
|
|
|
|
|
Rev: 1.00e 6/2002 |
3/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
|
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Preliminary |
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GS8170DD18/36C-333/300/250 |
||
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Pin Description Table |
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|||||
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||||
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Pin Location |
Symbol |
Description |
Type |
|
Comments |
|
||||
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A3, A5, A7, A9, B7, U4, |
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U6, U8, V3, V4, V5, V6, |
|
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A |
Address |
Input |
|
— |
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||
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V7, V8, V9, W5, W7 |
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C7 |
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A |
Address |
Input |
|
x18 version only |
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||
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||
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B5 |
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A |
Address |
Input |
|
x18 and x36 versions |
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||
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||||
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A6 |
ADV |
Advance |
Input |
|
Active High |
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||||
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|||
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K3 |
|
CK |
Clock |
Input |
|
Active High |
|
|||
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|||
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K1, K11 |
|
CQ |
Echo Clock |
Output |
|
Active High |
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|||
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K2, K10 |
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Echo Clock |
Output |
|
Active Low |
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CQ |
||||||||||
|
E2, F1, F2, G1, G2, H1, |
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H2, J1, J2, L10, L11, |
|
DQ |
Data I/O |
Input/Output |
|
x18 and x36 versions |
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|||
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M10, M11, N10, N11, |
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|||||||
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P10, P11, R10 |
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A10, A11, B10, B11, |
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C10, C11, D10, D11, |
|
DQ |
Data I/O |
Input/Output |
|
x36 version |
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|||
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E11, R1, T1, T2, U1, U2, |
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|||||||
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V1, V2, W1, W2 |
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C6 |
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|
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Chip Enable |
Input |
|
Active Low |
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E1 |
|||||||||
|
A4, A8 |
E2 & E3 |
Chip Enable |
Input |
|
Programmable Active High or Low |
|
||||
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||||
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G6, H6 |
EP2 & EP3 |
Chip Enable Program Pin |
Input |
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— |
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||||
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||||
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W9 |
TCK |
Test Clock |
Input |
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Active High |
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||||
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||||
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W4 |
TDI |
Test Data In |
Input |
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— |
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||||
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||||
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W8 |
TDO |
Test Data Out |
Output |
|
— |
|
||||
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||||
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W3 |
TMS |
Test Mode Select |
Input |
|
— |
|
||||
|
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||||
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J6, M6, N6 |
MCH |
Must Connect High |
Input |
|
Active High (all versions) |
|
||||
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B3, C9, D6, K6, L6, P6, |
MCL |
Must Connect Low |
Input |
|
Active Low (all versions) |
|
||||
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T6, W6 |
|
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||||||||
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||||
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B8, C4 |
MCL |
Must Connect Low |
Input |
|
Active Low (x36 version) |
|
||||
|
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|
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|
|
Rev: 1.00e 6/2002 |
4/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
|
|
|
|
|
|
|
|
Preliminary |
|
|
|
|
|
|
|
|
GS8170DD18/36C-333/300/250 |
||
|
|
|
|
|
|
|
|
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|
|
Pin Description Table |
|
|
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|||
|
|
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|
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|
|
||
|
Pin Location |
Symbol |
Description |
Type |
|
Comments |
|
||
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A1, A2, B1, B2, B4, B9, |
|
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C1, C2, C3, C5, C8, D1, |
|
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D2, D4, D5, D7, D8,E1, |
|
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|
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E10, F10, F11, G10, |
|
|
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|
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|
|
|
|
G11, H10, H11, J10, J11, |
NC |
No Connect |
— |
|
Not connected to die (all versions) |
|
||
|
K4, K8, K9, L1, L2, M1, |
|
|
||||||
|
M2, N1, N2, P1, P2, R2, |
|
|
|
|
|
|
|
|
|
R11, T4, T5, T7, T8, T10, |
|
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|
T11, U3, U5, U7, U9, |
|
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U10, U11, V10, V11, |
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W10, W11 |
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C7 |
NC |
No Connect |
— |
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Not connected to die (x36 version) |
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A1, A2, B1, B2, B4, B9, |
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C1, C2, C3, C8, D1, D2, |
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E1, E10, F10, F11, G10, |
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G11, H10, H11, J10, J11, |
NC |
No Connect |
— |
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Not connected to die (x36/x18 versions) |
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L1, L2, M1, M2, N1, N2, |
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P1, P2, R2, R11, T10, |
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T11, U10, U11, V10, |
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V11, W10, W11 |
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A10, A11, B8, B10, B11, |
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C4, C10, C11, D10, D11, |
NC |
No Connect |
— |
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Not connected to die (x18 version) |
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E11, R1, T1, T2, U1, U2, |
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V1, V2, W1, W2 |
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B6 |
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Write |
Input |
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Active Low |
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W |
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E5, E6, E7, G5, G7, J5, |
VDD |
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J7, L5, L7, N5, N7, R5, |
Core Power Supply |
Input |
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1.8 V Nominal |
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R6, R7 |
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E3, E4, E8, E9, J3, J4, |
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J8, J9, L3, L4, L8, L9, |
VDDQ |
Output Driver Power Supply |
Input |
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1.8 V or 1.5 V Nominal |
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N3, N4, N8, N9, R3, R4, |
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R8, R9 |
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E4, E8, R4, R8 |
VDDI |
Input Buffer Power Supply |
Input |
|
1.8 V or 1.5 V Nominal |
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D3, D9, F3, F4, F5, F7, |
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F8, F9, H3, H4, H5, H7, |
VSS |
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H8, H9, K5, K7, M3, M4, |
Ground |
Input |
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— |
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M5, M7, M8, M9, P3, P4, |
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P5, P7, P8, P9, T3, T9 |
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F6 |
ZQ |
Output Impedance Control |
Input |
|
Low = Low Impedance [High Drive] |
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High = High Impedance [Low Drive] |
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Rev: 1.00e 6/2002 |
5/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DD18/36C-333/300/250
Background
The central characteristics of Σ RAMs are that they are extremely fast and consume very little power. Because both operating and interface power is low, Σ RAMs can be implemented in a wide (x36) configuration, providing very high single package bandwidth (in excess of 20 Gb/s in ordinary pipelined configuration) and very low random access latency (5 ns). The use of very low voltage circuits in the core and 1.8 V or 1.5 V interface voltages allow the speed, power and density performance of Σ RAMs.
The Σ RAM family of pinouts has been designed to support a number of different common read and write protocols. The following timing diagrams provide a quick comparison between the late write read and write protocol and the DDR protocol options available in the context of the Σ RAM standard. This particular datasheet covers the Double Data Rate (DDR) Σ RAM.
The character of the applications for fast synchronous SRAMs in networking systems are extremely diverse. Σ RAMs have been developed to address the broad variety of applications in the networking market in a manner that can be supported with a unified development and manufacturing infrastructure. Σ RAMs address each of the bus protocol options commonly found in networking systems. This allows the Σ RAM to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use with older SRAMs, like the NBT, Late Write, or Double Data Rate SRAMs, as well as with new chip sets and ASIC’s that employ the Echo Clocks and realize the full potential of the Σ RAMs.
Mode Selection Truth Table Standard
L6 |
M6 |
J6 |
Name |
Function |
Analogous to... |
In This Data Sheet? |
|
|
|
|
|
|
|
0 |
0 |
0 |
Σ 1x1Ef |
Early Write, Flow through Read |
Flow through Burst RAM |
No |
|
|
|
|
|
|
|
0 |
0 |
1 |
Σ 1x1Lf |
Late Write, Flow through Read |
Flow through NBT SRAM |
No |
|
|
|
|
|
|
|
0 |
1 |
0 |
|
RFU |
|
n/a |
|
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|
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|
|
0 |
1 |
1 |
Σ 1x2Lp |
DDR |
Double Data Rate SRAM |
Yes |
|
|
|
|
|
|
|
1 |
0 |
0 |
Σ 1x1Ep |
Early Write, Pipelined Read |
Pipelined Burst RAM |
No |
|
|
|
|
|
|
|
1 |
0 |
1 |
Σ 1x1Dp |
Double Late Write, Pipelined Read |
Pipelined NBT SRAM |
No |
|
|
|
|
|
|
|
1 |
1 |
0 |
Σ 1x1Lp |
Late Write, Pipelined Read |
Pipelined Late Write SRAM |
No |
|
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|
|
All address and control inputs (with the exception of PE2, PE3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Rev: 1.00e 6/2002 |
6/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DD18/36C-333/300/250
Read Operations
Double Data Rate Read
In applications where a data rate markedly faster than the RAM’s latency is desired, Double Data Rate reads double the data transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In Double Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The output register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to the next falling edge of clock as well. SigmaRAM DDR RAMs burst in linear order only.
Double Data Rate Pipelined Read
|
Read |
Deselect |
Read |
Read |
Read |
|
|
CK |
|
|
|
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|
|
Address |
A |
XX |
C |
D |
E |
|
F |
ADV |
|
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|
|
/E1 |
|
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/W |
|
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|
|
QA0 |
QA1 |
QC0 |
QC1 |
QD0 |
QD1 |
DQ |
|
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CQ |
|
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Key |
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Hi-Z |
Access |
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|
Rev: 1.00e 6/2002 |
7/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DD18/36C-333/300/250
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Double Data Rate Write
A Double Data Rate Write is a specialized form of Late Write. In Double Data Rate mode, the RAM will capture Data In on both rising and falling edges of the RAM clock, CK, beginning with the rising edge of clock that follows the capture of the write address and command.
SigmaRAM Double Data Rate Read and Write
|
Read |
Deselect |
Write |
Read |
|
Read |
|
CK |
|
|
|
|
|
|
|
Address |
A |
B |
C |
D |
|
E |
F |
ADV |
|
|
|
|
|
|
|
/E1 |
|
|
|
|
|
|
|
/W |
|
|
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|
|
|
|
|
|
QA0 |
QA1 |
DC0 |
DC1 |
QD0 |
QD1 |
DQ |
|
|
|
|
|
|
|
CQ |
|
|
|
|
|
|
|
|
|
|
|
Key |
|
|
|
|
|
|
Hi-Z |
Access |
|
|
|
Rev: 1.00e 6/2002 |
8/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8170DD18/36C-333/300/250
Special Functions
Burst Cycles
Σ RAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.
SigmaRAM DDR Burst Read with Counter Wrap-around
|
Read |
|
Continue |
|
Continue |
|
Read |
|
Continue |
|
|
|
CK |
|
|
|
|
|
|
|
|
|
|
|
|
External |
A2 |
|
XX |
|
XX |
|
B0 |
|
XX |
|
XX |
|
Address |
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
||
Internal |
A2 |
A3 |
A0 |
A1 |
A2 |
A3 |
B0 |
B1 |
B2 |
B3 |
B1 |
|
Address |
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
||
ADV |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Counter Wraps |
|
|
|
|
|
|
/E1 |
|
|
|
|
|
|
|
|
|
|
|
|
/W |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
QA2 |
QA3 |
QA0 |
QA1 |
QA2 |
QA3 |
QB0 |
QB1 |
|
DQ |
|
|
|
|
|
|
|
|
|
|
|
|
CQ |
|
|
|
|
|
|
|
|
|
|
|
Rev: 1.00e 6/2002 |
9/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
|
|
|
|
|
|
|
|
|
|
|
Preliminary |
|
|
|
|
|
|
|
|
|
GS8170DD18/36C-333/300/250 |
||||
|
|
|
SigmaRAM DDR Burst Write with Counter Wrap-around |
|
|
|||||||
|
Write |
|
Continue |
|
Continue |
|
Write |
|
Continue |
|
|
|
CK |
|
|
|
|
|
|
|
|
|
|
|
|
External |
A2 |
|
XX |
|
XX |
|
B0 |
|
XX |
|
XX |
|
Address |
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
||
Internal |
A2 |
A3 |
A0 |
A1 |
A2 |
A3 |
B0 |
B1 |
B2 |
B3 |
B1 |
|
Address |
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
Counter Wraps |
|
|
|
|
|
|
ADV |
|
|
|
|
|
|
|
|
|
|
|
|
/E1 |
|
|
|
|
|
|
|
|
|
|
|
|
/W |
|
|
|
|
|
|
|
|
|
|
|
|
DQ |
|
|
DA2 |
DA3 |
DA0 |
DA1 |
DA2 |
DA3 |
DB0 |
DB1 |
DB2 |
|
CQ |
|
|
|
|
|
|
|
|
|
|
|
Burst Order
The burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) have been accessed. SigmaRAMs always count in linear burst order.
Linear Burst Order
|
A[1:0] |
A[1:0] |
|
|
|
|
|
|
1st address (Rising Edge CK) |
00 |
10 |
|
|
|
2nd address (Falling Edge CK) |
01 |
11 |
|
|
|
3rd address (Rising Edge CK) |
10 |
00 |
|
|
|
4th address (Falling Edge CK) |
11 |
01 |
|
|
|
Notes:
1.The burst counter wraps to initial state on the 3rd rising edge of clock.
2.The DDR SigmaRAM always begins an read or write at A0 = 0. A0 is internally set to 0 at the rising edge of clock and is not available to the user.
Rev: 1.00e 6/2002 |
10/31 |
© 2002, GSI Technology, Inc. |
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.