GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
119, 165, & 209 BGA
Commercial Temp
Industrial Temp
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250MHz–133 MHz
2.5V or 3.3 V VDD
2.5V or 3.3 V I/O
Features
•NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
•2.5 V or 3.3 V +10%/–10% core power supply
•2.5 V or 3.3 V I/O supply
•User-configurable Pipeline and Flow Through mode
•ZQ mode pin for user-selectable high/low output drive
•IEEE 1149.1 JTAG-compatible Boundary Scan
•On-chip write parity checking; even or odd selectable
•On-chip parity encoding and error detection
•LBO pin for Linear or Interleave Burst mode
•Pin-compatible with 2M, 4M, and 8M devices
•Byte write operation (9-bit Bytes)
•3 chip enable signals for easy depth expansion
•ZZ Pin for automatic power-down
•JEDEC-standard 119-, 165-, or 209-Bump BGA package
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-250 |
-225 |
-200 -166 -150 -133 Unit |
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Pipeline |
tKQ |
2.5 |
2.7 |
3.0 |
3.4 |
3.8 |
4.0 |
ns |
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3-1-1-1 |
tCycle |
4.0 |
4.4 |
5.0 |
6.0 |
6.7 |
7.5 |
ns |
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3.3 V |
Curr (x18) |
280 |
255 |
230 |
200 |
185 |
165 |
mA |
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Curr (x36) |
330 |
300 |
270 |
230 |
215 |
190 |
mA |
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Curr (x72) |
n/a |
n/a |
350 |
300 |
270 |
245 |
mA |
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2.5 V |
Curr (x18) |
275 |
250 |
230 |
195 |
180 |
165 |
mA |
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Curr (x36) |
320 |
295 |
265 |
225 |
210 |
185 |
mA |
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Curr (x72) |
n/a |
n/a |
335 |
290 |
260 |
235 |
mA |
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Flow |
tKQ |
5.5 |
6.0 |
6.5 |
7.0 |
7.5 |
8.5 |
ns |
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Through |
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tCycle |
5.5 |
6.0 |
6.5 |
7.0 |
7.5 |
8.5 |
ns |
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3.3 V |
Curr (x18) |
175 |
165 |
160 |
150 |
145 |
135 |
mA |
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Curr (x36) |
200 |
190 |
180 |
170 |
165 |
150 |
mA |
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Curr (x72) |
n/a |
n/a |
225 |
115 |
210 |
185 |
mA |
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2.5 V |
Curr (x18) |
175 |
165 |
160 |
150 |
145 |
135 |
mA |
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Curr (x36) |
200 |
190 |
180 |
170 |
165 |
150 |
mA |
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Curr (x72) |
n/a |
n/a |
225 |
115 |
210 |
185 |
mA |
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Functional Description
read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.
The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 & x36), or 209-bump (x72) BGA package.
The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
Rev: 2.18a 12/2002 |
1/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
|
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 Pad Out
209-Bump BGA—Top View (Package C)
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3 |
4 |
5 |
6 |
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8 |
9 |
10 |
11 |
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A |
DQG5 |
DQG1 |
A13 |
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E2 |
A14 |
ADV |
A15 |
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A17 |
DQB1 |
DQB5 |
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E3 |
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B |
DQG6 |
DQG2 |
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NC |
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A16 |
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DQB2 |
DQB6 |
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BC |
BG |
W |
BB |
BF |
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C |
DQG7 |
DQG3 |
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NC |
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NC |
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DQB3 |
DQB7 |
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BH |
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BD |
E1 |
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BE |
BA |
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D |
DQG8 |
DQG4 |
VSS |
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NC |
NC |
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NC |
NC |
VSS |
DQB4 |
DQB8 |
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G |
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E |
DQG9 |
DQC9 |
VDDQ |
VDDQ |
VDD |
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VDD |
VDD |
VDDQ |
VDDQ |
DQF9 |
DQB9 |
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F |
DQC4 |
DQC8 |
VSS |
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VSS |
VSS |
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ZQ |
VSS |
VSS |
VSS |
DQF8 |
DQF4 |
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G |
DQC3 |
DQC7 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
DQF7 |
DQF3 |
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H |
DQC2 |
DQC6 |
VSS |
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VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
DQF6 |
DQF2 |
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J |
DQC1 |
DQC5 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
DQF5 |
DQF1 |
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K |
NC |
NC |
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CK |
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NC |
VSS |
MCL |
VSS |
NC |
NC |
NC |
NC |
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L |
DQH1 |
DQH5 |
VDDQ |
VDDQ |
VDD |
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VDD |
VDDQ |
VDDQ |
DQA5 |
DQA1 |
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FT |
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M |
DQH2 |
DQH6 |
VSS |
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VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
DQA6 |
DQA2 |
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N |
DQH3 |
DQH7 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
DQA7 |
DQA3 |
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P |
DQH4 |
DQH8 |
VSS |
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VSS |
VSS |
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ZZ |
VSS |
VSS |
VSS |
DQA8 |
DQA4 |
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R |
DQD9 |
DQH9 |
VDDQ |
VDDQ |
VDD |
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VDD |
VDD |
VDDQ |
VDDQ |
DQA9 |
DQE9 |
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T |
DQD8 |
DQD4 |
VSS |
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NC |
NC |
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NC |
VSS |
DQE4 |
DQE8 |
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LBO |
PE |
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U |
DQD7 |
DQD3 |
NC |
A12 |
NC |
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A11 |
NC |
A10 |
NC |
DQE3 |
DQE7 |
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V |
DQD6 |
DQD2 |
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A9 |
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A8 |
A7 |
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A1 |
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A6 |
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A5 |
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A4 |
DQE2 |
DQE6 |
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W |
DQD5 |
DQD1 |
TMS |
TDI |
A3 |
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A0 |
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A2 |
TDO |
TCK |
DQE1 |
DQE5 |
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Rev 10 |
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch |
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Rev: 2.18a 12/2002 |
2/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) |
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GS8162Z72 BGA Pin Description |
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Symbol |
Type |
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Description |
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A0, A1 |
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I |
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Address field LSBs and Address Counter Preset Inputs |
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An |
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I |
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Address Inputs |
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DQA1–DQA9 |
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DQB1–DQB9 |
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DQC1–DQC9 |
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DQD1–DQD9 |
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I/O |
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Data Input and Output pins |
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DQE1–DQE9 |
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DQF1–DQF9 |
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DQG1–DQG9 |
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DQH1–DQH9 |
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A, |
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B, |
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C, |
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D, |
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E, |
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F, |
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Byte Write Enable for DQA, DQB, DQC, DQD, DQE, |
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B |
B |
B |
B |
B |
B |
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I |
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BG,BH |
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DQF, DQG, DQH I/Os; active low |
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NC |
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— |
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No Connect |
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CK |
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I |
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Clock Input Signal; active high |
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I |
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Write Enable. Writes all enabled bytes; active low |
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W |
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1, |
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3 |
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I |
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Chip Enable; active low |
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E |
E |
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E2 |
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I |
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Chip Enable; active high |
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I |
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Output Enable; active low |
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G |
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ZZ |
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I |
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Sleep Mode control; active high |
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I |
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Flow Through or Pipeline mode; active low |
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FT |
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I |
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Linear Burst Order mode; active low |
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LBO |
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MCH |
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I |
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Must Connect High |
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MCL |
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Must Connect Low |
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I |
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Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) |
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PE |
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I |
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Byte Enable; active low |
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BW |
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ZQ |
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FLXDrive Output Impedance Control |
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(Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) |
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TMS |
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I |
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Scan Test Mode Select |
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TDI |
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Scan Test Data In |
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TDO |
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Scan Test Data Out |
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TCK |
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Scan Test Clock |
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VDD |
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Core power supply |
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VSS |
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I |
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I/O and Core Ground |
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VDDQ |
|
|
|
I |
|
Output driver power supply |
|
Rev: 2.18a 12/2002 |
3/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
|
1 |
|
|
2 |
3 |
|
4 |
|
5 |
|
6 |
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|
7 |
|
8 |
|
9 |
10 |
11 |
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|||||||||
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A |
|
NC |
A6 |
|
|
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|
NC |
|
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|
|
|
|
|
|
ADV |
A17 |
A8 |
A19 |
A |
|||||||
|
E1 |
|
|
BB |
|
|
E3 |
|
|
CKE |
||||||||||||||||||||
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|||||
B |
|
NC |
A7 |
|
E2 |
NC |
|
|
|
CK |
|
|
|
|
|
|
|
A18 |
A9 |
NC |
B |
|||||||||
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BA |
W |
G |
||||||||||||||||||||||||||
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||||||
C |
|
NC |
NC |
VDDQ |
VSS |
VSS |
VSS |
VSS |
|
VSS |
VDDQ |
NC |
DQA |
C |
||||||||||||||||
D |
|
NC |
DQB |
VDDQ |
VDD |
VSS |
VSS |
VSS |
|
VDD |
VDDQ |
NC |
DQA |
D |
||||||||||||||||
E |
|
NC |
DQB |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
VDDQ |
NC |
DQA |
E |
|||||||||||||||
F |
|
NC |
DQB |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
VDDQ |
NC |
DQA |
F |
|||||||||||||||
G |
|
NC |
DQB |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
VDDQ |
NC |
DQA |
G |
|||||||||||||||
H |
|
|
|
|
|
MCH |
NC |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
NC |
ZQ |
ZZ |
H |
||||||||||||
|
|
FT |
|
|||||||||||||||||||||||||||
J |
DQB |
NC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
VDDQ |
DQA |
NC |
J |
||||||||||||||||
K |
DQB |
NC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
VDDQ |
DQA |
NC |
K |
||||||||||||||||
L |
DQB |
NC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
VDDQ |
DQA |
NC |
L |
||||||||||||||||
M |
DQB |
NC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
|
VDD |
VDDQ |
DQA |
NC |
M |
||||||||||||||||
|
|
|
|
DNU |
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||
N |
DQB |
VDDQ |
VSS |
NC |
NC |
NC |
|
VSS |
VDDQ |
NC |
NC |
N |
||||||||||||||||||
P |
|
NC |
NC |
|
A5 |
|
A4 |
TDI |
|
A1 |
|
TDO |
|
A11 |
A12 |
A14 |
NC |
P |
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||
R |
|
|
|
NC |
|
A3 |
|
A2 |
TMS |
|
A0 |
|
TCK |
|
A10 |
A13 |
A15 |
A16 |
R |
|||||||||||
|
LBO |
|
|
|
|
|||||||||||||||||||||||||
|
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||||||||||||||
|
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|
|
|
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch |
|
|
|
Rev: 2.18a 12/2002 |
4/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
165 Bump BGA—x36 Common I/O—Top View (Package D)
|
1 |
|
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2 |
3 |
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4 |
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5 |
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6 |
|
7 |
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|
8 |
|
9 |
10 |
11 |
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|||||||||
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A |
|
NC |
A6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ADV |
A17 |
A8 |
NC |
A |
|||||
|
E1 |
BC |
BB |
E3 |
CKE |
|||||||||||||||||||||||||
B |
|
NC |
A7 |
|
E2 |
|
|
|
|
|
|
CK |
|
|
|
|
|
|
|
A18 |
A9 |
NC |
B |
|||||||
|
|
BD |
|
BA |
|
W |
G |
|||||||||||||||||||||||
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
C |
DQC |
NC |
VDDQ |
VSS |
VSS |
VSS |
|
VSS |
VSS |
VDDQ |
NC |
DQB |
C |
|||||||||||||||||
D |
DQC |
DQC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQB |
DQB |
D |
|||||||||||||||||
E |
DQC |
DQC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQB |
DQB |
E |
|||||||||||||||||
F |
DQC |
DQC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQB |
DQB |
F |
|||||||||||||||||
G |
DQC |
DQC |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQB |
DQB |
G |
|||||||||||||||||
H |
|
|
|
|
|
MCH |
NC |
VDD |
VSS |
VSS |
|
VSS |
VDD |
NC |
ZQ |
ZZ |
H |
|||||||||||||
|
|
FT |
|
|||||||||||||||||||||||||||
J |
DQD |
DQD |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQA |
DQA |
J |
|||||||||||||||||
K |
DQD |
DQD |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQA |
DQA |
K |
|||||||||||||||||
L |
DQD |
DQD |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQA |
DQA |
L |
|||||||||||||||||
M |
DQD |
DQD |
VDDQ |
VDD |
VSS |
VSS |
|
VSS |
VDD |
VDDQ |
DQA |
DQA |
M |
|||||||||||||||||
N |
DQD |
DNU |
VDDQ |
VSS |
NC |
NC |
|
NC |
VSS |
VDDQ |
NC |
DQA |
N |
|||||||||||||||||
P |
|
NC |
NC |
|
A5 |
|
A4 |
TDI |
|
A1 |
TDO |
A11 |
A12 |
A14 |
NC |
P |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
R |
|
|
|
NC |
|
A3 |
|
A2 |
TMS |
|
A0 |
|
TCK |
A10 |
A13 |
A15 |
A16 |
R |
||||||||||||
|
LBO |
|
|
|
|
|||||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||
|
|
|
|
|
|
|
11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch |
|
|
|
Rev: 2.18a 12/2002 |
5/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z36 Pad Out
119 Bump BGA—Top View (Package B)
|
1 |
2 |
3 |
|
4 |
|
|
|
5 |
|
6 |
7 |
|
|||||||||||
A |
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
VDDQ |
A6 |
|
A7 |
A18 |
|
|
A8 |
|
A9 |
VDDQ |
||||||||||||||
B |
NC |
E2 |
|
A4 |
ADV |
A15 |
|
|
3 |
NC |
||||||||||||||
|
E |
|||||||||||||||||||||||
C |
NC |
A5 |
|
A3 |
VDD |
A14 |
A16 |
NC |
||||||||||||||||
D |
DQC4 |
DQC9 |
VSS |
ZQ |
VSS |
DQB9 |
DQB4 |
|||||||||||||||||
E |
DQC3 |
DQC8 |
VSS |
|
|
|
1 |
|
VSS |
DQB8 |
DQB3 |
|||||||||||||
|
E |
|||||||||||||||||||||||
F |
VDDQ |
DQC7 |
VSS |
|
|
|
|
|
|
VSS |
DQB7 |
VDDQ |
||||||||||||
|
|
G |
||||||||||||||||||||||
G |
DQC2 |
DQC6 |
|
|
C |
A17 |
|
|
|
B |
DQB6 |
DQB2 |
||||||||||||
|
B |
B |
||||||||||||||||||||||
H |
DQC1 |
DQC5 |
VSS |
|
|
|
|
VSS |
DQB5 |
DQB1 |
||||||||||||||
|
W |
|||||||||||||||||||||||
J |
VDDQ |
VDD |
NC |
VDD |
NC |
VDD |
VDDQ |
|||||||||||||||||
K |
DQA1 |
DQA5 |
VSS |
CK |
VSS |
DQA5 |
DQA1 |
|||||||||||||||||
L |
DQA2 |
DQA6 |
|
|
D |
NC |
|
|
|
A |
DQA6 |
DQA2 |
||||||||||||
|
B |
|
B |
|||||||||||||||||||||
M |
VDDQ |
DQA7 |
VSS |
|
|
VSS |
DQA7 |
VDDQ |
||||||||||||||||
CKE |
||||||||||||||||||||||||
N |
DQA3 |
DQA8 |
VSS |
|
A1 |
VSS |
DQA8 |
DQA3 |
||||||||||||||||
|
|
|
|
|||||||||||||||||||||
P |
DQA4 |
DQA9 |
VSS |
|
A0 |
VSS |
DQA9 |
DQA4 |
||||||||||||||||
R |
NC |
A2 |
|
|
VDD |
|
|
|
|
A13 |
|
|
|
|||||||||||
LBO |
|
FT |
PE |
|||||||||||||||||||||
T |
NC |
NC |
A10 |
A11 |
A12 |
NC |
|
ZZ |
||||||||||||||||
U |
VDDQ |
TMS |
TDI |
TCK |
TDO |
NC |
VDDQ |
Rev: 2.18a 12/2002 |
6/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z18 Pad Out
119 Bump BGA—Top View (Package B)
|
1 |
2 |
3 |
|
4 |
|
|
|
5 |
|
6 |
7 |
|
|||||||||||
A |
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
VDDQ |
A6 |
|
A7 |
A18 |
|
|
A8 |
|
A9 |
VDDQ |
||||||||||||||
B |
NC |
E2 |
|
A4 |
ADV |
A15 |
|
|
3 |
NC |
||||||||||||||
|
E |
|||||||||||||||||||||||
C |
NC |
A5 |
|
A3 |
VDD |
A14 |
A16 |
NC |
||||||||||||||||
D |
DQB1 |
NC |
VSS |
ZQ |
VSS |
DQPA9 |
NC |
|||||||||||||||||
E |
NC |
DQB2 |
VSS |
|
|
|
1 |
|
VSS |
NC |
DQA8 |
|||||||||||||
|
E |
|||||||||||||||||||||||
F |
VDDQ |
NC |
VSS |
|
|
|
|
|
|
VSS |
DQA7 |
VDDQ |
||||||||||||
|
|
G |
||||||||||||||||||||||
G |
NC |
DQB3 |
|
|
B |
A17 |
NC |
NC |
DQA6 |
|||||||||||||||
|
B |
|||||||||||||||||||||||
H |
DQB4 |
NC |
VSS |
|
|
|
|
VSS |
DQA5 |
NC |
||||||||||||||
|
W |
|||||||||||||||||||||||
J |
VDDQ |
VDD |
NC |
VDD |
NC |
VDD |
VDDQ |
|||||||||||||||||
K |
NC |
DQB5 |
VSS |
CK |
VSS |
NC |
DQA4 |
|||||||||||||||||
L |
DQB6 |
NC |
NC |
NC |
|
|
|
A |
DQA3 |
NC |
||||||||||||||
|
B |
|||||||||||||||||||||||
M |
VDDQ |
DQB7 |
VSS |
|
|
VSS |
NC |
VDDQ |
||||||||||||||||
CKE |
||||||||||||||||||||||||
N |
DQB8 |
NC |
VSS |
|
A1 |
VSS |
DQA2 |
NC |
||||||||||||||||
P |
NC |
DQPB9 |
VSS |
|
A0 |
VSS |
NC |
DQA1 |
||||||||||||||||
R |
NC |
A2 |
|
|
VDD |
|
|
|
|
A13 |
|
|
|
|||||||||||
LBO |
|
FT |
PE |
|||||||||||||||||||||
T |
NC |
A10 |
A11 |
NC |
A12 |
A19 |
|
ZZ |
||||||||||||||||
U |
VDDQ |
TMS |
TDI |
TCK |
TDO |
NC |
VDDQ |
Rev: 2.18a 12/2002 |
7/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
|
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|
|
|
|
|
|
|
|
|
|
|
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
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|
|
|
|
|
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|
|
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|
|
|
|
|
|
GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description |
||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
||||||||||||||
|
|
|
Symbol |
Type |
|
|
|
Description |
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
A0, A1 |
|
|
|
I |
|
|
|
Address field LSBs and Address Counter Preset Inputs |
|
||||||||||
|
|
|
|
|
|
An |
|
|
|
I |
|
|
|
Address Inputs |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
|
|
DQA1–DQA9 |
|
|
|
|
|
|
|
|
|
||||||||||||
|
|
DQB1–DQB9 |
|
I/O |
|
|
|
Data Input and Output pins |
|
||||||||||||||
|
|
DQC1–DQC0 |
|
|
|
|
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||
|
|
DQD1–DQD0 |
|
|
|
|
|
|
|
|
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
A, |
|
|
B, |
|
C, |
|
D |
|
|
|
I |
|
|
|
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low |
|
||||
|
|
B |
B |
B |
B |
|
|
|
|
|
|||||||||||||
|
|
|
|
|
|
NC |
|
— |
|
|
|
No Connect |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
CK |
|
|
|
I |
|
|
|
Clock Input Signal; active high |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I |
|
|
|
Clock Enable; active low |
|
||
|
|
|
|
|
CKE |
|
|
|
|
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I |
|
|
|
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) |
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PE |
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I |
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Write Enable; active low |
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W |
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1 |
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I |
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Chip Enable; active low |
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E |
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3 |
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I |
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Chip Enable; active low |
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E |
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E2 |
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I |
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Chip Enable; active high |
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I |
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Output Enable; active low |
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G |
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ADV |
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I |
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Burst address counter advance enable; active high |
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ZZ |
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I |
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Sleep mode control; active high |
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I |
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Flow Through or Pipeline mode; active low |
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FT |
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I |
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Linear Burst Order mode; active low |
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LBO |
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ZQ |
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I |
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FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low |
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Drive]) |
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TMS |
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I |
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Scan Test Mode Select |
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TDI |
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I |
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Scan Test Data In |
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TDO |
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O |
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Scan Test Data Out |
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TCK |
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I |
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Scan Test Clock |
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VDD |
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I |
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Core power supply |
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VSS |
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I |
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I/O and Core Ground |
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VDDQ |
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I |
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Output driver power supply |
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BPR1999.05.18 |
Rev: 2.18a 12/2002 |
8/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.
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Function |
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W |
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BA |
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BB |
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BC |
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BD |
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Read |
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H |
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X |
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X |
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X |
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X |
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Write Byte “a” |
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L |
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L |
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H |
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H |
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H |
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Write Byte “b” |
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L |
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H |
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L |
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H |
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H |
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Write Byte “c” |
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L |
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H |
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H |
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L |
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H |
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Write Byte “d” |
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L |
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H |
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H |
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H |
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L |
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Write all Bytes |
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L |
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L |
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L |
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L |
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L |
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Write Abort/NOP |
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L |
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H |
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H |
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H |
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H |
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Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 2.18a 12/2002 |
9/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Synchronous Truth Table
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Operation |
Type |
Address |
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E1 |
E2 |
|
E3 |
ZZ |
ADV |
|
W |
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Bx |
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G |
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CKE |
CK |
DQ |
Notes |
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Deselect Cycle, Power Down |
D |
None |
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H |
X |
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X |
L |
L |
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X |
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X |
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X |
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L |
L-H |
High-Z |
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Deselect Cycle, Power Down |
D |
None |
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X |
X |
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H |
L |
L |
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X |
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X |
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X |
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L |
L-H |
High-Z |
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Deselect Cycle, Power Down |
D |
None |
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X |
L |
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X |
L |
L |
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X |
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X |
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X |
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L |
L-H |
High-Z |
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Deselect Cycle, Continue |
D |
None |
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X |
X |
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X |
L |
H |
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X |
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X |
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X |
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L |
L-H |
High-Z |
1 |
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Read Cycle, Begin Burst |
R |
External |
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L |
H |
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L |
L |
L |
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H |
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X |
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L |
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L |
L-H |
Q |
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Read Cycle, Continue Burst |
B |
Next |
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X |
X |
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X |
L |
H |
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X |
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X |
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L |
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L |
L-H |
Q |
1,10 |
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NOP/Read, Begin Burst |
R |
External |
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L |
H |
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L |
L |
L |
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H |
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X |
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H |
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L |
L-H |
High-Z |
2 |
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Dummy Read, Continue Burst |
B |
Next |
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X |
X |
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X |
L |
H |
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X |
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X |
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H |
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L |
L-H |
High-Z |
1,2,10 |
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Write Cycle, Begin Burst |
W |
External |
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L |
H |
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L |
L |
L |
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L |
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L |
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X |
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L |
L-H |
D |
3 |
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Write Cycle, Continue Burst |
B |
Next |
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X |
X |
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X |
L |
H |
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X |
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L |
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X |
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L |
L-H |
D |
1,3,10 |
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NOP/Write Abort, Begin Burst |
W |
None |
|
L |
H |
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L |
L |
L |
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L |
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H |
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X |
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L |
L-H |
High-Z |
2,3 |
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Write Abort, Continue Burst |
B |
Next |
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X |
X |
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X |
L |
H |
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X |
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H |
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X |
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L |
L-H |
High-Z |
1,2,3,10 |
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Clock Edge Ignore, Stall |
|
Current |
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X |
X |
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X |
L |
X |
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X |
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X |
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X |
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H |
L-H |
- |
4 |
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Sleep Mode |
|
None |
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X |
X |
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X |
H |
X |
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X |
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X |
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X |
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X |
X |
High-Z |
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Notes:
1.Continue Burst cycles, whether Read or Write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first.
2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active, so no write operation is performed.
3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles.
4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z.
5.X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low
6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7.Wait states can be inserted by setting CKE high.
8.This device contains circuitry that ensures all outputs are in High Z during power-up.
9.A 2-bit burst counter is incorporated.
10.The address counter is incriminated for all Burst continue cycles.
Rev: 2.18a 12/2002 |
10/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Pipelined and Flow Through Read Write Control State Diagram
|
|
D |
B |
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Deselect |
W |
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R |
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D |
D |
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New Read |
W |
|
New Write |
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R |
||
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R |
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W |
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B |
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B |
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R |
W |
R |
W |
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Burst Read |
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Burst Write |
|
B |
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B |
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D |
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D |
Key |
Input Command Code |
|
Notes |
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ƒ Transition |
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Current State (n) |
Next State (n+1) |
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n |
n+1 |
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Clock (CK) |
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Command |
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ƒ |
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ƒ |
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Current State |
|
Next State |
1.The Hold command (CKE Low) is not
shown because it prevents any state change.
2.W, R, B, and D represent input command
codes as indicated in the Synchronous Truth Table.
n+2 n+3
ƒ ƒ
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
Rev: 2.18a 12/2002 |
11/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Pipeline Mode Data I/O State Diagram
Intermediate |
|
Intermediate |
|
|
R |
Intermediate |
B W |
R |
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B |
||
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High Z |
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Data Out |
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W |
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|||
(Data In) |
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(Q Valid) |
||
D |
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Intermediate |
Intermediate |
|
D |
|
W R
High Z
B
D
Intermediate
Key |
Input Command Code |
Notes |
||||
|
1. |
The Hold command |
|
Low) is not |
||
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|
|
(CKE |
|||
|
ƒ Transition |
|
|
shown because it prevents any state change. |
||
|
Transition |
2. |
W, R, B, and D represent input command |
|||
|
|
|
||||
Current State (n) Intermediate State (N+1) |
Next State (n+2) |
codes as indicated in the Truth Tables. |
||||
|
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|
n |
n+1 |
n+2 |
n+3 |
Clock (CK)
Command |
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ƒ |
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ƒ |
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ƒ |
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ƒ |
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Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 2.18a 12/2002 |
12/38 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.