GSI GS816273C-250I, GS816273C-250, GS816273C-225I, GS816273C-225, GS816273C-200I Datasheet

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Preliminary

GS816273C-250/225/200/166/150/133

209-Pin BGA

Commercial Temp

Industrial Temp

256K x 72

18Mb S/DCD Sync Burst SRAMs

250 MHz–133MHz

2.5V or 3.3 V VDD

2.5V or 3.3 V I/O

Features

Single/Dual Cycle Deselect selectable

IEEE 1149.1 JTAG-compatible Boundary Scan

ZQ mode pin for user-selectable high/low output drive

2.5 or 3.3 V +10%/–10% core power supply

2.5 V or 3.3 V I/O supply

LBO pin for Linear or Interleaved Burst mode

Internal input resistors on mode pins allow floating mode pins

Byte Write (BW) and/or Global Write (GW) operation

Internal self-timed write cycle

Automatic power-down for portable applications

JEDEC-standard 209-bump BGA package

 

 

-250

-225 -200 -166 -150 -133

Unit

 

 

 

 

 

 

 

 

 

Pipeline

tKQ

2.6

2.6

2.6

2.9

3.3

3.5

ns

3-1-1-1

tCycle

4.0

4.4

5.0

6.0

6.7

7.5

ns

 

 

 

 

 

 

 

 

 

3.3 V

Curr (x72)

430

395

350

300

270

245

mA

 

 

 

 

 

 

 

 

 

2.5 V

Curr (x72)

410

380

335

290

260

235

mA

Functional Description

Applications

The GS816273C is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS816273C operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal

circuits and are 3.3 V and 2.5 V compatible.

Controls

Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.

SCD and DCD Pipelined Reads

The GS816273C is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their

Rev: 1.01 12/2002

1/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Preliminary

GS816273C-250/225/200/166/150/133

GS816273 Pad Out

209 Bump BGA—Top View

Package C

 

1

2

3

4

5

6

 

 

 

 

7

 

 

8

9

10

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

DQG5

DQG1

A15

 

 

E2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A17

DQB1

DQB5

ADSP

ADSC

ADV

E3

B

DQG6

DQG2

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

A16

 

 

 

 

 

 

 

 

DQB2

DQB6

 

BC

BG

 

 

BW

 

BB

BF

C

DQG7

DQG3

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

 

 

 

 

DQB3

DQB7

BH

 

BD

 

 

 

 

E1

 

 

BE

BA

D

DQG8

DQG4

VSS

 

NC

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

NC

VSS

DQB4

DQB8

 

 

 

 

 

 

 

G

 

GW

E

DQG9

DQC9

VDDQ

VDDQ

 

VDD

 

VDD

VDD

VDDQ

VDDQ

DQF9

DQB9

F

DQC4

DQC8

VSS

VSS

 

VSS

 

 

 

ZQ

 

VSS

VSS

VSS

DQF8

DQF4

G

DQC3

DQC7

VDDQ

VDDQ

 

VDD

 

MCH

VDD

VDDQ

VDDQ

DQF7

DQF3

H

DQC2

DQC6

VSS

VSS

 

VSS

 

MCL

 

VSS

VSS

VSS

DQF6

DQF2

J

DQC1

DQC5

VDDQ

VDDQ

 

VDD

 

MCL

VDD

VDDQ

VDDQ

DQF5

DQF1

K

NC

NC

 

CK

 

NC

 

VSS

 

MCL

 

VSS

NC

NC

NC

NC

L

DQH1

DQH5

VDDQ

VDDQ

 

VDD

VDDQ/DNU

VDD

VDDQ

VDDQ

DQA5

DQA1

M

DQH2

DQH6

VSS

VSS

 

VSS

 

MCL

 

VSS

VSS

VSS

DQA6

DQA2

N

DQH3

DQH7

VDDQ

VDDQ

 

VDD

 

SCD

VDD

VDDQ

VDDQ

DQA7

DQA3

P

DQH4

DQH8

VSS

VSS

 

VSS

 

 

 

ZZ

 

VSS

VSS

VSS

DQA8

DQA4

R

DQD9

DQH9

VDDQ

VDDQ

 

VDD

 

VDD

VDD

VDDQ

VDDQ

DQA9

DQE9

T

DQD8

DQD4

VSS

 

NC

 

NC

 

 

 

 

 

 

NC

NC

VSS

DQE4

DQE8

 

 

 

 

LBO

 

 

U

DQD7

DQD3

NC

A14

 

A13

 

 

A12

 

 

A11

A10

NC

DQE3

DQE7

V

DQD6

DQD2

 

A9

 

 

A8

 

A7

 

 

 

 

A1

 

 

A6

 

 

A5

 

 

A4

DQE2

DQE6

W

DQD5

DQD1

TMS

TDI

 

A3

 

 

 

 

A0

 

 

A2

TDO

TCK

DQE1

DQE5

Rev 10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch

 

 

 

 

 

 

 

Rev: 1.01 12/2002

2/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preliminary

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GS816273C-250/225/200/166/150/133

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GS816273 BGA Pin Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Type

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0, A1

 

 

I

 

Address field LSBs and Address Counter Preset Inputs.

 

 

 

 

 

 

 

 

 

 

 

 

An

 

 

I

 

Address Inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQA1–DQA9

 

 

 

 

 

 

 

 

 

 

 

 

 

DQB1–DQB9

 

 

 

 

 

 

 

 

 

 

 

 

 

DQC1–DQC9

 

 

 

 

 

 

 

 

 

 

 

 

 

DQD1–DQD9

 

 

I/O

 

Data Input and Output pins

 

 

 

 

 

 

DQE1–DQE9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQF1–DQF9

 

 

 

 

 

 

 

 

 

 

 

 

 

DQG1–DQG9

 

 

 

 

 

 

 

 

 

 

 

 

 

DQH1–DQH9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A,

 

 

B,

 

 

 

 

C,

 

D,

 

E,

 

F,

 

 

 

 

 

 

Byte Write Enable for DQA, DQB, DQC, DQD, DQE,

 

 

 

B

B

B

B

B

B

 

 

I

 

 

 

 

 

 

 

BG,BH

 

 

 

DQF, DQG, DQH I/Os; active low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

 

 

No Connect

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CK

 

 

I

 

Clock Input Signal; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

Global Write Enable—Writes all bytes; active low

 

 

 

 

 

 

 

 

 

 

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1,

 

 

3

 

 

 

I

 

Chip Enable; active low

 

 

 

 

 

 

 

 

E

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E2

 

 

I

 

Chip Enable; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

Output Enable; active low

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

Burst address counter advance enable; active low

 

 

 

 

 

 

 

 

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

Address Strobe (Processor, Cache Controller); active low

 

 

 

 

 

ADSP,

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

 

 

I

 

Sleep Mode control; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

Linear Burst Order mode; active low

 

 

 

 

 

 

 

 

 

 

LBO

 

 

 

 

 

 

 

 

 

 

SCD

 

 

I

 

Single Cycle Deselect/Dual Cycle Deselect Mode Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCH

 

 

I

 

Must Connect High

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCL

 

 

 

 

 

 

Must Connect Low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rev: 1.01 12/2002

3/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

 

 

 

 

 

 

 

 

 

 

 

Preliminary

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GS816273C-250/225/200/166/150/133

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GS816273 BGA Pin Description

 

 

 

 

 

 

 

 

 

Symbol

Type

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BW

 

 

 

I

 

Byte Enable; active low

 

 

 

ZQ

 

 

I

 

FLXDrive Output Impedance Control

 

 

 

 

 

 

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

 

I

 

Scan Test Mode Select

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

 

I

 

Scan Test Data In

 

 

 

 

 

 

 

 

 

 

TDO

 

 

O

 

Scan Test Data Out

 

 

 

 

 

 

 

 

 

 

TCK

 

 

I

 

Scan Test Clock

 

 

 

 

 

 

 

 

 

 

VDD

 

 

I

 

Core power supply

 

 

VSS

 

 

I

 

I/O and Core Ground

 

 

VDDQ

 

 

I

 

Output driver power supply

 

 

VDDQ/DNU

 

 

 

VDDQ or VDD (must be tied high)

 

 

 

 

 

or

 

 

 

 

 

 

 

 

 

 

 

 

Do Not Use (must be left floating)

 

Mode Pin Functions

Mode Name

 

Pin

State

Function

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

L

Linear Burst

Burst Order Control

LBO

H

Interleaved Burst

 

 

 

 

 

 

 

 

 

 

Power Down Control

 

ZZ

L or NC

Active

 

 

 

 

H

Standby, IDD = ISB

 

 

 

 

Single/Dual Cycle Deselect Control

SCD

L

Dual Cycle Deselect

 

 

H or NC

Single Cycle Deselect

 

 

 

 

 

 

 

 

 

 

FLXDrive Output Impedance Control

 

ZQ

L

High Drive (Low Impedance)

 

 

 

 

H or NC

Low Drive (High Impedance)

 

 

 

 

 

 

 

 

 

 

Note:

Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables.

Rev: 1.01 12/2002

4/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273C-250/225/200/166/150/133

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte.

Burst Counter Sequences

Linear Burst Sequence

 

A[1:0]

A[1:0]

A[1:0]

A[1:0]

 

 

 

 

 

 

 

 

 

 

1st address

00

01

10

11

 

 

 

 

 

2nd address

01

10

11

00

 

 

 

 

 

3rd address

10

11

00

01

 

 

 

 

 

4th address

11

00

01

10

 

 

 

 

 

Note: The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

 

A[1:0]

A[1:0]

A[1:0]

A[1:0]

 

 

 

 

 

 

 

 

 

 

1st address

00

01

10

11

 

 

 

 

 

2nd address

01

00

11

10

 

 

 

 

 

3rd address

10

11

00

01

 

 

 

 

 

4th address

11

10

01

00

 

 

 

 

 

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Byte Write Truth Table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function

 

GW

 

 

BW

BA

BB

 

BC

 

BD

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

H

 

 

H

 

X

 

X

 

X

 

X

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

H

 

 

L

 

H

 

H

 

H

 

H

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write byte a

 

H

 

 

L

 

L

 

H

 

H

 

H

2, 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write byte b

 

H

 

 

L

 

H

 

L

 

H

 

H

2, 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write byte c

 

H

 

 

L

 

H

 

H

 

L

 

H

2, 3, 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write byte d

 

H

 

 

L

 

H

 

H

 

H

 

L

2, 3, 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write all bytes

 

H

 

 

L

 

L

 

L

 

L

 

L

2, 3, 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write all bytes

 

L

 

 

X

 

X

 

X

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2.Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4.Bytes “C” and “D” are only available on the x36 version.

Rev: 1.01 12/2002

5/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273C-250/225/200/166/150/133

Synchronous Truth Table

 

 

State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Address Used

Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

DQ4

E

ADSP

ADSC

ADV

1

 

 

 

 

 

 

 

W

 

 

Key5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

None

X

 

H

 

X

 

L

 

X

 

 

X

High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

R

 

L

 

L

 

X

 

X

 

 

X

Q

Read Cycle, Begin Burst

External

R

 

L

 

H

 

L

 

X

 

 

F

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Begin Burst

External

W

 

L

 

H

 

L

 

X

 

 

T

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

CR

 

X

 

H

 

H

 

L

 

 

F

Q

Read Cycle, Continue Burst

Next

CR

 

H

 

X

 

H

 

L

 

 

F

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

CW

 

X

 

H

 

H

 

L

 

 

T

D

Write Cycle, Continue Burst

Next

CW

 

H

 

X

 

H

 

L

 

 

T

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

 

X

 

H

 

H

 

H

 

 

F

Q

Read Cycle, Suspend Burst

Current

 

 

H

 

X

 

H

 

H

 

 

F

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

 

X

 

H

 

H

 

H

 

 

T

D

Write Cycle, Suspend Burst

Current

 

 

H

 

X

 

H

 

H

 

 

T

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.X = Don’t Care, H = High, L = Low

2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding

3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).

4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.

5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.01 12/2002

6/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GSI GS816273C-250I, GS816273C-250, GS816273C-225I, GS816273C-225, GS816273C-200I Datasheet

Preliminary

GS816273C-250/225/200/166/150/133

Simplified State Diagram

X

 

 

 

 

Deselect

 

 

 

 

W

R

 

Operation

 

W

 

R

 

X

First Write

R

First Read

X

SynchronousSimple

CW

 

CR

 

CR

 

 

 

Operation

 

W

 

R

 

Synchronous

 

 

 

 

 

R

 

 

 

 

 

 

 

Burst

X

Burst Write

 

Burst Read

X

 

 

CR

 

 

Simple

 

CW

 

CR

 

 

 

 

 

Notes:

1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low.

3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low.

Rev: 1.01 12/2002

7/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273C-250/225/200/166/150/133

Simplified State Diagram with G

X

 

 

 

Deselect

 

 

 

W

R

 

 

W

 

R

 

X

First Write

R

W

X

 

First Read

CW

 

CR

CW

CR

 

W

 

R

 

X

Burst Write

R

W

X

 

CR

Burst Read

 

 

CW

 

 

 

 

 

 

CW

 

CR

 

Notes:

1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2.Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time.

Rev: 1.01 12/2002

8/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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