GSI GS72108TP-8I, GS72108TP-8, GS72108TP-15I, GS72108TP-15, GS72108TP-12I Datasheet

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GS72108TP/J

SOJ, TSOP

Commercial Temp

Industrial Temp

256K x 8

2Mb Asynchronous SRAM

8, 10, 12, 15 ns 3.3 V VDD Center VDD and VSS

Features

Fast access time: 8, 10, 12, 15 ns

CMOS low power operation: 150/125/110/90 mA at minimum cycle time.

Single 3.3 V ± 0.3 V power supply

All inputs and outputs are TTL-compatible

Fully static operation

Industrial Temperature Option: –40° to 85°C

Package line up

J:400 mil, 36-pin SOJ package

TP: 400 mil, 44-pin TSOP Type II package

Description

The GS72108 is a high speed CMOS Static RAM organized as 262,144 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTL-com- patible. The GS72108 is available in 400 mil SOJ and 400 mil TSOP Type-II packages.

Pin Descriptions

Symbol

Description

 

 

A0–A17

Address input

DQ1–DQ8

Data input/output

 

 

 

 

 

 

 

 

 

 

 

Chip enable input

 

CE

 

 

 

 

 

Write enable input

 

WE

 

 

 

 

Output enable input

 

OE

VDD

+3.3 V power supply

VSS

Ground

 

NC

No connect

 

 

 

 

 

 

SOJ 256K x 8-Pin Configuration

A4

 

1

36

 

 

 

 

A3

 

2

35

 

 

 

 

A2

 

3

34

 

 

A1

 

4

33

 

 

 

 

A0

 

 

5

32

 

 

 

 

 

 

6

31

CE

 

 

DQ1

 

 

7

30

 

 

DQ2

 

8

36-pin

29

 

 

 

 

VDD

 

9

400 mil SOJ

28

 

 

 

 

VSS

 

 

10

27

 

 

 

 

 

 

DQ3

 

11

 

26

 

 

 

DQ4

 

 

12

 

25

 

 

 

 

 

 

 

13

 

24

WE

 

 

 

 

 

 

A17

 

 

14

 

23

 

 

 

A16

 

 

15

 

22

 

 

 

A15

 

 

16

 

21

 

 

 

A14

 

17

 

20

 

 

 

A13

 

 

18

 

19

 

 

 

NC

A5

A6

A7

A8

OE

DQ8 DQ7

VSS

VDD

DQ6

DQ5

A9

A10

A11

A12

NC

NC

Rev: 1.08 7/2002

1/12

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GSI GS72108TP-8I, GS72108TP-8, GS72108TP-15I, GS72108TP-15, GS72108TP-12I Datasheet

GS72108TP/J

TSOP-II 256K x 8-Pin Configuration

NC

 

1

 

44

 

 

 

NC

 

 

 

 

 

 

NC

 

 

2

 

43

 

 

 

NC

 

 

 

 

 

 

A4

 

 

3

 

42

 

 

 

NC

 

 

 

 

 

A3

 

4

 

41

 

 

 

A5

 

 

 

 

 

 

 

 

 

 

A2

 

5

 

40

 

 

 

A6

 

 

 

 

 

A1

 

6

 

39

 

 

 

A7

 

 

 

 

 

 

 

 

 

 

A0

 

7

 

38

 

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

37

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

DQ1

 

9

 

36

 

 

 

DQ8

 

 

 

 

 

 

 

 

 

 

DQ2

 

10

44-pin

35

 

 

 

DQ7

 

 

 

 

 

 

 

 

VDD

 

11

34

 

 

 

VSS

 

 

 

 

 

 

 

 

VSS

 

12

400 mil TSOP II

33

 

 

 

VDD

 

 

 

 

 

 

 

 

DQ3

 

13

 

32

 

 

 

DQ6

 

 

 

 

 

 

 

 

 

 

DQ4

 

14

 

31

 

 

 

DQ5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

30

 

 

 

A9

WE

 

 

 

 

 

 

 

 

A17

 

 

16

 

29

 

 

 

A10

 

 

 

 

 

A16

 

 

17

 

28

 

 

 

A11

 

 

 

 

 

A15

 

 

18

 

27

 

 

 

A12

 

 

 

 

 

 

 

 

 

 

A14

 

19

 

26

 

 

 

NC

A13

 

 

20

 

25

 

 

 

NC

NC

 

21

 

24

 

 

 

NC

 

 

 

 

 

 

NC

 

 

22

 

23

 

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Block Diagram

A0

Row

Decoder

Address

Input

Buffer

A17

CE

WE

OE Control

Memory Array

Column

Decoder

I/O Buffer

DQ1 DQ8

Rev: 1.08 7/2002

2/12

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GS72108TP/J

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Truth Table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

 

OE

 

 

 

 

WE

 

DQ1 to DQ8

VDD Current

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

X

 

 

 

X

Not Selected

ISB1, ISB2

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

 

 

 

H

Read

 

 

 

 

 

 

 

 

 

 

 

IDD

 

 

L

 

X

 

 

 

L

Write

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

 

 

H

High Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: X: “H” or “L”

Absolute Maximum Ratings

Parameter

Symbol

 

Rating

Unit

 

 

 

 

 

 

 

 

Supply Voltage

VDD

–0.5 to +4.6

V

 

 

 

 

Input Voltage

VIN

–0.5 to VDD +0.5

V

 

 

(

4.6 V max.)

 

Output Voltage

VOUT

–0.5 to VDD +0.5

V

 

 

(

4.6 V max.)

 

Allowable power dissipation

PD

 

0.7

W

 

 

 

 

 

Storage temperature

TSTG

 

–55 to 150

oC

Note:

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

Rev: 1.08 7/2002

3/12

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS72108TP/J

Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

Supply Voltage for -10/12/15

VDD

3.0

3.3

3.6

V

Supply Voltage for -8

VDD

3.135

3.3

3.6

V

Input High Voltage

VIH

2.0

VDD +0.3

V

Input Low Voltage

VIL

–0.3

0.8

V

 

 

 

 

 

 

Ambient Temperature,

TAc

0

70

oC

Commercial Range

 

 

 

 

 

 

 

 

 

 

 

Ambient Temperature,

TAI

–40

85

oC

Industrial Range

 

 

 

 

 

 

 

 

 

 

 

Note:

1.Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.

2.Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Capacitance

Parameter

Symbol

Test Condition

Max

Unit

 

 

 

 

 

 

 

 

 

 

Input Capacitance

CIN

VIN = 0 V

5

pF

 

 

 

 

 

Output Capacitance

COUT

VOUT = 0 V

7

pF

 

 

 

 

 

Notes:

1.Tested at TA = 25°C, f = 1 MHz

2.These parameters are sampled and are not 100% tested.

DC I/O Pin Characteristics

 

Parameter

Symbol

Test Conditions

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Leakage

IIL

VIN = 0 to VDD

– 1 uA

1 uA

 

 

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Leakage

ILO

Output High Z

–1 uA

1 uA

 

 

Current

VOUT = 0 to VDD

 

 

 

 

 

 

 

Output High Voltage

VOH

IOH = –4mA

2.4

 

 

 

 

 

 

 

 

 

Output Low Voltage

VOL

ILO = +4mA

0.4 V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rev: 1.08 7/2002

 

4/12

 

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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