GS71116TP/J/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
64K x 16
1Mb Asynchronous SRAM
10, 12, 15ns 3.3V VDD Center VDD & VSS
Features
•Fast access time: 10, 12, 15ns
•CMOS low power operation: 100/85/70 mA at min. cycle time.
•Single 3.3V ± 0.3V power supply
•All inputs and outputs are TTL compatible
•Byte control
•Fully static operation
•Industrial Temperature Option: -40° to 85°C
•Package line up
J:400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS71116 is a high speed CMOS static RAM organized as 65,536-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3V power supply and all inputs and outputs are TTL compatible. The GS71116 is available in a 6x8 mm Fine Pitch BGA package as well as in 400 mil SOJ and 400 mil TSOP Type-II packages.
SOJ 64K x 16 Pin Configuration
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A4 |
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44 |
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A5 |
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A3 |
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A6 |
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A2 |
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A7 |
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A1 |
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Top view |
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OE |
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A0 |
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UB |
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CE |
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LB |
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DQ1 |
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DQ16 |
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DQ2 |
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DQ15 |
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DQ3 |
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DQ14 |
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DQ4 |
10 |
44 pin |
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DQ13 |
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VDD |
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VSS |
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VSS |
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SOJ |
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VDD |
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DQ5 |
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DQ12 |
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DQ6 |
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DQ11 |
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DQ7 |
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DQ10 |
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DQ8 |
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DQ9 |
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WE |
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NC |
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A15 |
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A8 |
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A14 |
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A9 |
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A13 |
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A10 |
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A12 |
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A11 |
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NC |
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23 |
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NC |
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Pin Descriptions |
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Fine Pitch BGA 64K x 16 Bump Configuration |
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Description |
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A0 to A15 |
Address input |
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1 |
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6 |
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DQ1 to DQ16 |
Data input/output |
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Chip enable input |
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CE |
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A |
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LB |
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OE |
A0 |
A1 |
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A2 |
NC |
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Lower byte enable input |
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LB |
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(DQ1 to DQ8) |
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B |
DQ16 |
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UB |
A3 |
A4 |
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CE |
DQ1 |
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Upper byte enable input |
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C |
DQ14 |
DQ15 |
A5 |
A6 |
DQ2 |
DQ3 |
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UB |
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(DQ9 to DQ16) |
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D |
VSS |
DQ13 |
NC |
A7 |
DQ4 |
VDD |
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WE |
Write enable input |
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Output enable input |
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E |
VDD |
DQ12 |
NC |
NC |
DQ5 |
VSS |
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OE |
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VDD |
+3.3V power supply |
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F |
DQ11 |
DQ10 |
A8 |
A9 |
DQ7 |
DQ6 |
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VSS |
Ground |
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G |
DQ9 |
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NC |
A10 |
A11 |
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WE |
DQ8 |
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NC |
No connect |
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H |
NC |
A12 |
A13 |
A14 |
A15 |
NC |
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6mm x 8mm, 0.75mm Bump Pitch |
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Top View |
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Rev: 1.06 6/2000 |
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1/15 |
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© 1999, Giga Semiconductor, Inc. |
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
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M |
GS71116TP/J/U
TSOP-II 64K x 16 Pin Configuration
A4 |
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1 |
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A3 |
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2 |
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A2 |
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3 |
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A1 |
4 |
Top view |
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A0 |
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6 |
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CE |
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DQ1 |
7 |
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DQ2 |
8 |
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DQ3 |
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DQ4 |
10 |
44 pin |
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VDD |
11 |
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VSS |
12 |
TSOP II |
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DQ5 |
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DQ6 |
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DQ7 |
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DQ8 |
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17 |
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WE |
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A15 |
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A14 |
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A13 |
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A12 |
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NC |
22 |
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44 |
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A5 |
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43 |
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A6 |
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42 |
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A7 |
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41 |
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OE |
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40 |
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UB |
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39 |
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LB |
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38 |
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DQ16 |
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DQ15 |
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36 |
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DQ14 |
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DQ13 |
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34 |
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VSS |
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33 |
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VDD |
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32 |
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DQ12 |
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DQ11 |
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DQ10 |
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DQ9 |
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28 |
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NC |
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27 |
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A8 |
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26 |
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A9 |
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25 |
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A10 |
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24 |
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A11 |
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NC |
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Block Diagram
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A0 |
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Row |
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Memory Array |
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Address |
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Decoder |
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Input |
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Buffer |
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Column |
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A15 |
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Decoder |
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WE |
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Control |
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I/O Buffer |
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OE |
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UB _____ |
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LB _____ |
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DQ1 |
DQ16 |
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Rev: 1.06 6/2000 |
2/15 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS71116TP/J/U |
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Truth Table |
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CE |
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OE |
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WE |
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LB |
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UB |
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DQ1 to DQ8 |
DQ9 to DQ16 |
VDD Current |
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H |
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X |
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Not Selected |
Not Selected |
ISB1, ISB2 |
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L |
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L |
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Read |
Read |
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L |
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H |
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Read |
High Z |
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H |
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L |
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High Z |
Read |
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L |
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Write |
Write |
IDD |
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L |
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X |
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Write |
Not Write, High Z |
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Not Write, High Z |
Write |
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X |
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High Z |
High Z |
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L |
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High Z |
High Z |
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Note: X: “H” or “L” |
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Absolute Maximum Ratings |
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Parameter |
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Rating |
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Supply Voltage |
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VDD |
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-0.5 to +4.6 |
V |
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Input Voltage |
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VIN |
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(≤ 4.6V max.) |
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Output Voltage |
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VOUT |
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V |
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(≤ 4.6V max.) |
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Allowable power dissipation |
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PD |
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0.7 |
W |
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Storage temperature |
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TSTG |
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-55 to 150 |
oC |
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Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.06 6/2000 |
3/15 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116TP/J/U
Recommended Operating Conditions
Parameter |
Symbol |
Min |
Typ |
Max |
Unit |
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Supply Voltage for -12/15 |
VDD |
3.0 |
3.3 |
3.6 |
V |
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Supply Voltage for -10 |
VDD |
3.135 |
3.3 |
3.6 |
V |
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Input High Voltage |
VIH |
2.0 |
- |
VDD+0.3 |
V |
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Input Low Voltage |
VIL |
-0.3 |
- |
0.8 |
V |
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Ambient Temperature, |
TAc |
0 |
- |
70 |
oC |
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Commercial Range |
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Ambient Temperature, |
TAI |
-40 |
- |
85 |
oC |
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Industrial Range |
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Note:
1.Input overshoot voltage should be less than VDD+2V and not exceed 20ns.
2.Input undershoot voltage should be greater than -2V and not exceed 20ns.
Capacitance
Parameter |
Symbol |
Test Condition |
Max |
Unit |
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Input Capacitance |
CIN |
VIN=0V |
5 |
pF |
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Output Capacitance |
COUT |
VOUT=0V |
7 |
pF |
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Notes:
1.Tested at TA=25°C, f=1MHz
2.These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter |
Symbol |
Test Conditions |
Min |
Max |
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Input Leakage |
IIL |
VIN = 0 to VDD |
-1uA |
1uA |
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Current |
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Output Leakage |
ILO |
Output High Z |
-1uA |
1uA |
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Current |
VOUT = 0 to VDD |
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Output High Voltage |
VOH |
IOH = - 4mA |
2.4 |
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Output Low Voltage |
VOL |
ILO = + 4mA |
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0.4V |
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Rev: 1.06 6/2000 |
4/15 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116TP/J/U
Power Supply Currents
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0 to 70°C |
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-40 to 85°C |
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Parameter |
Symbol |
Test Conditions |
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10ns |
12ns |
15ns |
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10ns |
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12ns |
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15ns |
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£ VIL |
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CE |
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Operating |
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All other inputs |
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Supply |
IDD (max) |
³ VIH or £ VIL |
100mA |
85mA |
70mA |
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115mA |
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100mA |
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85mA |
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Current |
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Min. cycle time |
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IOUT = 0 mA |
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³ VIH |
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CE |
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Standby |
ISB1 (max) |
All other inputs |
45mA |
40mA |
35mA |
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50mA |
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45mA |
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40mA |
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Current |
³ VIH or £VIL |
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Min. cycle time |
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Standby |
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CE ³ VDD - 0.2V |
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ISB2 (max) |
All other inputs |
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10mA |
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15mA |
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Current |
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||||||||
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³ VDD - 0.2V or £ 0.2V |
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Rev: 1.06 6/2000 |
5/15 |
© 1999, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.