GS71108ATP/J/SJ/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
128K x 8
1Mb Asynchronous SRAM
7, 8, 10, 12 ns 3.3 V VDD Center VDD and VSS
Features
•Fast access time: 7, 8, 10, 12 ns
•CMOS low power operation: 140/120/95/80 mA at minimum cycle time
•Single 3.3 V power supply
•All inputs and outputs are TTL-compatible
•Fully static operation
•Industrial Temperature Option: –40° to 85°C
•Package line up
J: 400 mil, 32-pin SOJ package
TP: 400 mil, 32-pin TSOP Type II package SJ: 300 mil, 32-pin SOJ package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS71108A is a high speed CMOS Static RAM organized as 131,072 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS71108A is available in a 6 mm x 8 mm Fine Pitch BGA package, as well as in 300 mil and 400 mil SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions
Symbol |
Description |
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A0–A16 |
Address input |
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DQ1–DQ8 |
Data input/output |
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Chip enable input |
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CE |
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Write enable input |
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WE |
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Output enable input |
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OE |
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VDD |
+3.3 V power supply |
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VSS |
Ground |
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NC |
No connect |
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SOJ & TSOP-II 128K x 8-Pin Configuration
A3 |
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1 |
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32 |
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A4 |
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A2 |
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A5 |
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A1 |
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A6 |
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A0 |
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A7 |
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CE |
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32-pin |
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OE |
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DQ1 |
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400 mil SOJ |
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DQ8 |
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DQ2 |
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7 |
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DQ7 |
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VDD |
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25 |
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VSS |
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VSS |
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9 |
300 mil SOJ |
24 |
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VDD |
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DQ3 |
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& |
23 |
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DQ6 |
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DQ4 |
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11 |
22 |
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DQ5 |
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400 mil TSOP II |
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12 |
21 |
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WE |
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A8 |
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A16 |
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13 |
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20 |
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A9 |
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A15 |
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14 |
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19 |
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A10 |
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A14 |
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15 |
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18 |
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A11 |
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A13 |
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16 |
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17 |
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A12 |
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Packages J, TP, and SJ
Fine Pitch BGA 128K x 8-Bump Configuration
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6 |
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A |
NC |
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A2 |
A6 |
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A7 |
NC |
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OE |
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B |
DQ1 |
NC |
A1 |
A5 |
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DQ8 |
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CE |
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C |
DQ2 |
NC |
A0 |
A4 |
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NC |
DQ7 |
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D |
VSS |
NC |
NC |
A3 |
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NC |
VDD |
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E |
VDD |
NC |
NC |
NC |
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NC |
VSS |
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F |
DQ3 |
NC |
A14 |
A11 |
DQ5 |
DQ6 |
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G |
DQ4 |
NC |
A15 |
A12 |
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A8 |
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WE |
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H |
NC |
A10 |
A16 |
A13 |
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A9 |
NC |
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Package U
6 mm x 8 mm, 0.75 mm Bump Pitch Top View
Rev: 1.04a 10/2002 |
1/14 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Block Diagram
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A0 |
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Row |
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Memory Array |
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Address |
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Decoder |
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Input |
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Buffer |
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A16 |
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Decoder |
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CE |
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WE |
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Control |
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I/O Buffer |
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OE |
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DQ |
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1 |
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Truth Table |
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DQ8 |
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CE |
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OE |
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WE |
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DQ1 to DQ8 |
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VDD Current |
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H |
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X |
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X |
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Not Selected |
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ISB1, ISB2 |
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L |
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L |
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H |
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Read |
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IDD |
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L |
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X |
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L |
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Write |
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L |
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H |
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H |
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High Z |
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Note: X: “H” or “L”
Rev: 1.04a 10/2002 |
2/14 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Absolute Maximum Ratings
Parameter |
Symbol |
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Rating |
Unit |
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Supply Voltage |
VDD |
–0.5 to +4.6 |
V |
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Input Voltage |
VIN |
–0.5 to VDD +0.5 |
V |
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(≤ |
4.6 V max.) |
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Output Voltage |
VOUT |
–0.5 to VDD +0.5 |
V |
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(≤ |
4.6 V max.) |
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Allowable power dissipation |
PD |
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0.7 |
W |
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Storage temperature |
TSTG |
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–55 to 150 |
oC |
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter |
Symbol |
Min |
Typ |
Max |
Unit |
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Supply Voltage for -7/-8/-10/-12 |
VDD |
3.0 |
3.3 |
3.6 |
V |
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Input High Voltage |
VIH |
2.0 |
— |
VDD +0.3 |
V |
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Input Low Voltage |
VIL |
–0.3 |
— |
0.8 |
V |
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Ambient Temperature, |
TAc |
0 |
— |
70 |
oC |
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Commercial Range |
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Ambient Temperature, |
TAI |
–40 |
— |
85 |
oC |
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Industrial Range |
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Notes:
1.Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2.Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Rev: 1.04a 10/2002 |
3/14 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Capacitance
Parameter |
Symbol |
Test Condition |
Max |
Unit |
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Input Capacitance |
CIN |
VIN = 0 V |
5 |
pF |
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Output Capacitance |
COUT |
VOUT = 0 V |
7 |
pF |
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Notes:
1.Tested at TA = 25°C, f = 1 MHz
2.These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter |
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Symbol |
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Test Conditions |
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Min |
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Max |
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Input Leakage |
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IIL |
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VIN = 0 to VDD |
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–1 uA |
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1 uA |
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Current |
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Output Leakage |
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ILO |
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Output High Z |
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–1 uA |
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1 uA |
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Current |
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VOUT = 0 to VDD |
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Output High Voltage |
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VOH |
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IOH = –4 mA |
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2.4 |
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— |
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Output Low Voltage |
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VOL |
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ILO = +4 mA |
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— |
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0.4 V |
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Power Supply Currents |
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Parameter |
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Symbol |
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Test Conditions |
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0 to 70°C |
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–40 to 85°C |
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7 ns |
8 ns |
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10 ns |
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12 ns |
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7 ns |
8 ns |
10 ns |
12 ns |
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≤ VIL |
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CE |
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Operating |
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All other inputs |
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Supply |
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IDD |
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≥ |
VIH or ≤ VIL |
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140 mA |
120 mA |
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95 mA |
80 mA |
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145 mA |
125 mA |
100 mA |
85 mA |
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Current |
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Min. cycle time |
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IOUT = 0 mA |
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≥ VIH |
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CE |
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Standby |
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ISB1 |
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All other inputs |
25 mA |
20 mA |
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20 mA |
15 mA |
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30 mA |
25 mA |
25 mA |
20 mA |
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Current |
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≥ |
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VIH or ≤ VIL |
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Min. cycle time |
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≥ VDD – 0.2 V |
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Standby |
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CE |
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ISB2 |
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All other inputs |
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2 mA |
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5 mA |
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Current |
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≥ VDD – 0.2 V or ≤ |
0.2 V |
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Rev: 1.04a 10/2002 |
4/14 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
AC Test Conditions
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Output Load 1 |
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Parameter |
Conditions |
DQ |
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Input high level |
VIH = 2.4 V |
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30pF1 |
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50Ω |
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Input low level |
VIL = 0.4 V |
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Input rise time |
tr = 1 V/ns |
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VT = 1.4 V |
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Input fall time |
tf = 1 V/ns |
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Input reference level |
1.4 V |
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Output Load 2 |
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Output reference level |
1.4 V |
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3.3 V |
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Output load |
Fig. 1& 2 |
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DQ |
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589Ω |
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Note: |
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5pF1 |
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434Ω |
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1. Include scope and jig capacitance. |
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2. Test conditions as specified with output loading as shown in Fig. 1 |
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unless otherwise noted. |
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3.Output load 2 for tLZ, tHZ, tOLZ and tOHZ
AC Characteristics
Read Cycle
Parameter |
Symbol |
-7 |
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-8 |
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-10 |
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-12 |
Unit |
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Min |
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Max |
Min |
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Max |
Min |
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Max |
Min |
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Max |
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Read cycle time |
tRC |
7 |
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— |
8 |
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— |
10 |
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— |
12 |
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— |
ns |
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Address access time |
tAA |
— |
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7 |
— |
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8 |
— |
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10 |
— |
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12 |
ns |
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Chip enable access time |
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tAC |
— |
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7 |
— |
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8 |
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10 |
— |
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12 |
ns |
(CE) |
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Output enable to output valid |
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tOE |
— |
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3 |
— |
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3.5 |
— |
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4 |
— |
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5 |
ns |
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(OE) |
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Output hold from address change |
tOH |
3 |
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— |
3 |
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3 |
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3 |
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ns |
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Chip enable to output in low Z |
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tLZ* |
3 |
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— |
3 |
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3 |
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3 |
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— |
ns |
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(CE) |
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Output enable to output in low Z |
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tOLZ* |
0 |
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— |
0 |
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— |
0 |
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— |
0 |
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— |
ns |
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(OE) |
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Chip disable to output in High Z |
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tHZ* |
— |
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3.5 |
— |
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4 |
— |
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5 |
— |
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6 |
ns |
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(CE) |
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Output disable to output in High Z |
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tOHZ* |
— |
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3 |
— |
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3.5 |
— |
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4 |
— |
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5 |
ns |
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(OE) |
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* These parameters are sampled and are not 100% tested
Rev: 1.04a 10/2002 |
5/14 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.