Preliminary
GS88237BB-333/300/275/250/225/200
119-Bump BGA
Commercial Temp
Industrial Temp
256K x 36
9Mb SCD/DCD Sync Burst SRAM
333MHz–200 MHz
2.5V or 3.3 V VDD
2.5V or 3.3 V I/O
Features
•Single/Dual Cycle Deselect selectable
•IEEE 1149.1 JTAG-compatible Boundary Scan
•ZQ mode pin for user-selectable high/low output drive
•2.5 V or 3.3 V +10%/–10% core power supply
•2.5 V or 3.3 V I/O supply
•LBO pin for Linear or Interleaved Burst mode
•Internal input resistors on mode pins allow floating mode pins
•Default to SCD x18/x36 Interleaved Pipeline mode
•Byte Write (BW) and/or Global Write (GW) operation
•Internal self-timed write cycle
•Automatic power-down for portable applications
•JEDEC-standard 119-bump BGA package
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-333 |
-300 |
-275 |
-250 -225 -200 Unit |
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Pipeline |
tKQ |
2.0 |
2.2 |
2.3 |
2.3 |
2.5 |
2.7 |
ns |
3-1-1-1 |
tCycle |
3.0 |
3.3 |
3.6 |
4.0 |
4.4 |
5.0 |
ns |
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3.3 V |
Curr (x36) |
435 |
395 |
360 |
330 |
300 |
270 |
mA |
2.5 V |
Curr (x36) |
435 |
395 |
360 |
330 |
300 |
270 |
mA |
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Functional Description
Applications
The GS88237BB is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88237BB operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
SCD and DCD Pipelined Reads
The GS88237BB is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their
Rev: 1.00b 12/2002 |
1/26 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88237BB-333/300/275/250/225/200
GS88237B Pad Out
119 Bump BGA—Top View
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VDDQ |
A6 |
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A7 |
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A8 |
A9 |
VDDQ |
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ADSP |
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B |
NC |
NC |
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A4 |
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A15 |
A17 |
NC |
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ADSC |
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C |
NC |
A5 |
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A3 |
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VDD |
A14 |
A16 |
NC |
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D |
DQC4 |
DQC9 |
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VSS |
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ZQ |
VSS |
DQB9 |
DQB4 |
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E |
DQC3 |
DQC8 |
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VSS |
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1 |
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VSS |
DQB8 |
DQB3 |
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E |
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F |
VDDQ |
DQC7 |
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VSS |
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VSS |
DQB7 |
VDDQ |
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G |
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G |
DQC2 |
DQC6 |
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B |
DQB6 |
DQB2 |
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ADV |
B |
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H |
DQC1 |
DQC5 |
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VSS |
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VSS |
DQB5 |
DQB1 |
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GW |
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J |
VDDQ |
VDD |
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NC |
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VDD |
NC |
VDD |
VDDQ |
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K |
DQD1 |
DQD5 |
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VSS |
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CK |
VSS |
DQA5 |
DQA1 |
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L |
DQD2 |
DQD6 |
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D |
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SCD |
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A |
DQA6 |
DQA2 |
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B |
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B |
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M |
VDDQ |
DQD7 |
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VSS |
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VSS |
DQA7 |
VDDQ |
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BW |
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N |
DQD3 |
DQD8 |
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VSS |
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A1 |
VSS |
DQA8 |
DQA3 |
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P |
DQD4 |
DQD9 |
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VSS |
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A0 |
VSS |
DQA9 |
DQA4 |
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R |
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VDDQ/ |
A13 |
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NC |
A2 |
LBO |
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VDD |
PE |
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DNU |
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T |
NC |
NC |
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A10 |
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A11 |
A12 |
NC |
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ZZ |
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U |
VDDQ |
TMS |
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TDI |
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TCK |
TDO |
NC |
VDDQ |
Rev: 1.00b 12/2002 |
2/26 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88237BB-333/300/275/250/225/200
GS88237B (PE = 0) Block Diagram
A0–An |
Register |
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D |
Q |
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A0 |
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A0 |
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D0 |
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Q0 |
A1 |
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A1 |
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Q1 |
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D1 |
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Counter |
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A |
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Load |
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LBO |
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Memory |
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ADV |
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CK |
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Array |
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ADSC |
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ADSP |
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Register |
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Q |
D |
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GW |
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36 |
36 |
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BW |
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D |
Q |
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BA |
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Register |
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D |
Q |
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BB |
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Register |
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4 |
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D |
Q |
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BC |
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Register Q D |
Register D Q |
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D Q |
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Register |
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Register |
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D |
Q |
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BD |
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Register |
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36 |
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D |
Q |
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36 |
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36 |
E1 |
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Register |
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D |
Q |
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36 |
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4 |
32 |
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Register |
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Parity |
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Encode |
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Q |
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Parity |
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1 |
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Compare |
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G |
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36 |
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ZZ |
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Power Down |
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SCD |
DQx1–DQx9 |
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NC |
NC |
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Control |
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Note: Only x36 version shown for simplicity.
Rev: 1.00b 12/2002 |
3/26 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS88237B (PE = 1) x32 Mode Block Diagram
A0–An |
Register |
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D |
Q |
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A0 |
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A0 |
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D0 |
Q0 |
A1 |
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A1 |
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Q1 |
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D1 |
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Counter |
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Load |
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LBO |
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ADV |
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CK |
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ADSC |
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ADSP |
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GW |
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Register |
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BW |
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D |
Q |
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BA |
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B |
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B |
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Register
D Q
Register
E1 D Q
Register
D Q
1 G
ZZ |
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Power Down |
SCD |
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Control |
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Note: Only x36 version shown for simplicity.
Rev: 1.00b 12/2002 |
4/26 |
Preliminary
GS88237BB-333/300/275/250/225/200
A
Memory
Array
Q |
D |
36 |
36 |
4
Parity
Encode
32 |
4
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Register Q D |
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Register D Q |
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32 |
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36 |
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D |
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D |
Q |
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Parity |
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4 |
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Parity |
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Compare |
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32 |
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DQx1–DQx9 |
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NC |
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NC |
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88237BB-333/300/275/250/225/200
Mode Pin Functions
Mode Name |
|
Pin |
State |
Function |
||
Name |
||||||
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L |
Linear Burst |
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Burst Order Control |
LBO |
|||||
H |
Interleaved Burst |
|||||
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Power Down Control |
|
ZZ |
L or NC |
Active |
||
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||||
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H |
Standby, IDD = ISB |
||||
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|||
Single/Dual Cycle Deselect Control |
SCD |
L |
Dual Cycle Deselect |
|||
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H or NC |
Single Cycle Deselect |
|||||
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FLXDrive Output Impedance Control |
|
ZQ |
L |
High Drive (Low Impedance) |
||
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H or NC |
Low Drive (High Impedance) |
||||
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Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte.
Burst Counter Sequences
Linear Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
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1st address |
00 |
01 |
10 |
11 |
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2nd address |
01 |
10 |
11 |
00 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
00 |
01 |
10 |
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Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
|
A[1:0] |
A[1:0] |
A[1:0] |
A[1:0] |
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1st address |
00 |
01 |
10 |
11 |
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2nd address |
01 |
00 |
11 |
10 |
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3rd address |
10 |
11 |
00 |
01 |
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4th address |
11 |
10 |
01 |
00 |
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Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00b 12/2002 |
5/26 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88237BB-333/300/275/250/225/200
Byte Write Truth Table
|
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Function |
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GW |
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BW |
BA |
BB |
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BC |
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BD |
Notes |
|||||||
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Read |
|
H |
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H |
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X |
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X |
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X |
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X |
1 |
|||||
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Read |
|
H |
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L |
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H |
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H |
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H |
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H |
1 |
|||||
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|||||
Write byte a |
|
H |
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L |
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L |
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H |
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H |
|
H |
2, 3 |
|||||
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|||||
Write byte b |
|
H |
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L |
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H |
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L |
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H |
|
H |
2, 3 |
|||||
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|||||
Write byte c |
|
H |
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L |
|
H |
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H |
|
L |
|
H |
2, 3, 4 |
|||||
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|||||
Write byte d |
|
H |
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L |
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H |
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H |
|
H |
|
L |
2, 3, 4 |
|||||
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|||||
Write all bytes |
|
H |
|
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L |
|
L |
|
L |
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L |
|
L |
2, 3, 4 |
|||||
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|||||
Write all bytes |
|
L |
|
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X |
|
X |
|
X |
|
X |
|
X |
|
|||||
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|
Notes:
1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2.Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4.Bytes “C” and “D” are only available on the x36 version.
Rev: 1.00b 12/2002 |
6/26 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88237BB-333/300/275/250/225/200
Synchronous Truth Table
|
|
State |
|
|
|
|
|
|
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|
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|
|
|
Operation |
Address Used |
Diagram |
|
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|
|
|
3 |
DQ4 |
|
E |
ADSP |
ADSC |
ADV |
||||||||||||||||
1 |
|
|
|
|
|
|
|
W |
|||||||||||
|
|
Key5 |
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|
|||||
Deselect Cycle, Power Down |
None |
X |
|
H |
|
X |
|
L |
|
X |
|
|
X |
High-Z |
|||||
|
|
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|
|
|
|
|
Read Cycle, Begin Burst |
External |
R |
|
L |
|
L |
|
X |
|
X |
|
|
X |
Q |
|||||
Read Cycle, Begin Burst |
External |
R |
|
L |
|
H |
|
L |
|
X |
|
|
F |
Q |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write Cycle, Begin Burst |
External |
W |
|
L |
|
H |
|
L |
|
X |
|
|
T |
D |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Read Cycle, Continue Burst |
Next |
CR |
|
X |
|
H |
|
H |
|
L |
|
|
F |
Q |
|||||
Read Cycle, Continue Burst |
Next |
CR |
|
H |
|
X |
|
H |
|
L |
|
|
F |
Q |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write Cycle, Continue Burst |
Next |
CW |
|
X |
|
H |
|
H |
|
L |
|
|
T |
D |
|||||
Write Cycle, Continue Burst |
Next |
CW |
|
H |
|
X |
|
H |
|
L |
|
|
T |
D |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Read Cycle, Suspend Burst |
Current |
|
|
X |
|
H |
|
H |
|
H |
|
|
F |
Q |
|||||
Read Cycle, Suspend Burst |
Current |
|
|
H |
|
X |
|
H |
|
H |
|
|
F |
Q |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Write Cycle, Suspend Burst |
Current |
|
|
X |
|
H |
|
H |
|
H |
|
|
T |
D |
|||||
Write Cycle, Suspend Burst |
Current |
|
|
H |
|
X |
|
H |
|
H |
|
|
T |
D |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes:
1.X = Don’t Care, H = High, L = Low
2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).
4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.00b 12/2002 |
7/26 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88237BB-333/300/275/250/225/200
Simplified State Diagram
X |
|
|
|
|
Deselect |
|
|
|
|
|
W |
R |
|
|
Operation |
|
W |
|
R |
|
|
X |
First Write |
R |
First Read |
X |
||
SynchronousSimple |
||||||
CW |
|
CR |
|
CR |
||
|
|
|
||||
Operation |
|
W |
|
R |
|
|
Synchronous |
|
|
|
|||
|
|
R |
|
|
||
|
|
|
|
|
||
Burst |
X |
Burst Write |
|
Burst Read |
X |
|
|
|
CR |
|
|
||
Simple |
|
CW |
|
CR |
|
|
|
|
|
|
Notes:
1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low.
3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low.
Rev: 1.00b 12/2002 |
8/26 |
© 2002, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.