GSI GS842Z36AB-180I, GS842Z36AB-180, GS842Z36AB-166I, GS842Z36AB-166, GS842Z36AB-150I Datasheet

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Preliminary

GS842Z18/36AB-180/166/150/100

Commercial Temp

4Mb Pipelined and Flow Through

3.3 V V

119-Bump BGA

 

180 MHz–100 MHz

 

 

DD

Industrial Temp

Synchronous NBT SRAMs 2.5 V and 3.3 V VDDQ

 

 

 

Features

256K x 18 and 128K x 36 configurations

User configurable Pipeline and Flow Through mode

NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization

Fully pin compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs

Pin-compatible with 2M, 8M, and 16M devices

3.3 V +10%/–10% core power supply

2.5 V or 3.3 V I/O supply

LBO pin for Linear or Interleave Burst mode

Byte write operation (9-bit Bytes)

3 chip enable signals for easy depth expansion

Clock Control, registered address, data, and control

ZZ Pin for automatic power-down

JEDEC-standard 119-bump BGA package

 

 

–180

–166

–150

–100

Pipeline

tCycle

5.5 ns

6.0 ns

6.6 ns

10 ns

tKQ

3.2 ns

3.5 ns

3.8 ns

4.5 ns

3-1-1-1

IDD

335 mA

310 mA

280 mA

190 mA

 

 

 

 

 

 

 

Flow

tKQ

8 ns

8.5 ns

10 ns

12 ns

Through

tCycle

9.1 ns

10 ns

12 ns

15 ns

2-1-1-1

IDD

210 mA

190 mA

165 mA

135 mA

Functional Description

The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS842Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

The GS842Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump BGA package.

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

 

 

 

 

 

 

 

Address

A

B

C

D

E

F

 

Read/Write

R

W

R

W

R

W

 

Flow Through

 

QA

DB

QC

DD

QE

 

Data I/O

 

 

 

 

 

 

 

 

 

Pipelined

 

 

QA

DB

QC

DD

QE

Data I/O

 

 

Rev: 1.02 11/2002

1/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

Preliminary

GS842Z18/36AB-180/166/150/100

GS842Z18A Pad Out

119 Bump BGATop View

 

1

2

3

 

4

 

 

 

5

 

6

7

A

 

 

 

 

 

 

 

 

 

 

 

VDDQ

A6

 

A7

NC

 

 

A8

 

A9

VDDQ

B

NC

E2

 

A4

ADV

A15

 

 

3

NC

 

E

C

NC

A5

 

A3

VDD

A14

A16

NC

D

DQB1

NC

VSS

ZQ

VSS

DQA9

NC

E

NC

DQB2

VSS

 

 

 

1

 

VSS

NC

DQA8

 

E

F

VDDQ

NC

VSS

 

 

 

 

 

 

VSS

DQA7

VDDQ

 

 

G

G

NC

DQB3

 

 

B

NC

NC

NC

DQA6

 

B

H

DQB4

NC

VSS

 

 

 

 

VSS

DQA5

NC

 

W

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB5

VSS

CK

VSS

NC

DQA4

L

DQB6

NC

NC

NC

 

 

 

A

DQA3

NC

 

B

M

VDDQ

DQB7

VSS

 

 

VSS

NC

VDDQ

CKE

N

DQB8

NC

VSS

 

A1

VSS

DQA2

NC

P

NC

DQB9

VSS

 

A0

VSS

NC

DQA1

R

NC

A2

 

 

VDD

 

 

 

 

A13

NC

LBO

 

FT

T

NC

A10

A11

NC

A12

A17

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Rev: 1.02 11/2002

2/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS842Z18/36AB-180/166/150/100

GS842Z36A Pad Out

119 Bump BGATop View

 

1

2

3

 

4

 

 

 

5

 

6

7

A

 

 

 

 

 

 

 

 

 

 

 

VDDQ

A6

 

A7

NC

 

 

A8

 

A9

VDDQ

B

NC

E2

 

A4

ADV

A15

 

 

3

NC

 

E

C

NC

A5

 

A3

VDD

A14

A16

NC

D

DQC4

DQC9

VSS

ZQ

VSS

DQB9

DQB4

E

DQC3

DQC8

VSS

 

 

 

1

 

VSS

DQB8

DQB3

 

E

F

VDDQ

DQC7

VSS

 

 

 

 

 

 

VSS

DQB7

VDDQ

 

 

G

G

DQC2

DQC6

 

 

C

NC

 

 

 

B

DQB6

DQB2

 

B

B

H

DQC1

DQC5

VSS

 

 

 

 

VSS

DQB5

DQB1

 

W

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD1

DQD5

VSS

CK

VSS

DQA5

DQA1

L

DQD2

DQD6

 

 

D

NC

 

 

 

A

DQA6

DQA2

 

B

 

B

M

VDDQ

DQD7

VSS

 

 

VSS

DQA7

VDDQ

CKE

N

DQD3

DQD8

VSS

 

A1

VSS

DQA8

DQA3

P

DQD4

DQD9

VSS

 

A0

VSS

DQA9

DQA4

R

NC

A2

 

 

VDD

 

 

 

 

A13

NC

LBO

 

FT

T

NC

NC

A10

A11

A12

NC

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Rev: 1.02 11/2002

3/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS842Z18/36AB-180/166/150/100

GS842Z18/36A Pin Description

 

 

Symbol

Type

Description

 

 

 

 

 

 

 

 

 

A0, A1

I

Address field LSBs and Address Counter Preset Inputs

 

 

 

 

 

 

An

I

Address Inputs

 

 

 

 

 

DQA1–DQA9

 

 

 

DQB1–DQB9

I/O

Data Input and Output pins

 

DQC1–DQC9

 

 

 

 

DQD1–DQD9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A,

 

 

B,

 

 

 

 

 

C,

 

D

I

Byte Write Enable for DQA, DQB, DQC, DQA I/Os; active low ( x36 Version)

 

B

B

B

B

 

 

 

 

 

CK

I

Clock Input Signal; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

Clock Input Buffer Enable; active low

 

 

 

 

CKE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

Write Enable. Writes all enabled bytes; active low

 

 

 

 

 

 

 

W

 

 

 

 

 

 

1,

 

 

 

 

 

3

I

Chip Enable; active low

 

 

 

E

E

 

 

 

 

 

 

E2

I

Chip Enable; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

Output Enable; active low

 

 

 

 

 

 

 

G

 

 

 

 

ADV

I

Burst address counter advance enable; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZZ

I

Sleep Mode control; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

Flow Through or Pipeline mode; active low

 

 

 

 

 

 

FT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

Linear Burst Order mode; active low

 

 

 

 

LBO

 

 

 

 

 

ZQ

I

FLXDrive Output Impedance Control

 

 

 

 

 

(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

No Connect

 

 

 

 

 

 

 

 

 

TMS

I

Scan Test Mode Select

 

 

 

 

 

 

 

 

 

 

 

TDI

I

Scan Test Data In

 

 

 

 

 

 

 

 

 

TDO

O

Scan Test Data Out

 

 

 

 

 

 

 

 

 

 

 

TCK

I

Scan Test Clock

 

 

 

 

 

 

 

 

 

 

 

VDD

I

Core power supply

 

 

 

 

VSS

I

I/O and Core Ground

 

 

 

VDDQ

I

Output driver power supply

 

 

 

 

 

CK

I

Clock Input Signal; active high

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rev: 1.02 11/2002

4/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS842Z18/36AB-180/166/150/100

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipelined Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function

 

W

 

 

BA

 

BB

 

BC

 

BD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

H

 

 

X

 

X

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte “a”

 

L

 

 

L

 

H

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte “b”

 

L

 

 

H

 

L

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte “c”

 

L

 

 

H

 

H

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte “d”

 

L

 

 

H

 

H

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

Write all Bytes

 

L

 

 

L

 

L

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

Write Abort/NOP

 

L

 

 

H

 

H

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.

Flow through Mode Read and Write Operations

Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.

Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.

Rev: 1.02 11/2002

5/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS842Z18/36AB-180/166/150/100

Synchronous Truth Table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Type

Address

 

E1

E2

 

E3

ZZ

ADV

 

W

 

 

Bx

 

G

 

CKE

CK

DQ

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

D

None

 

H

X

 

X

L

L

 

X

 

 

X

 

X

 

L

L-H

High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

D

None

 

X

X

 

H

L

L

 

X

 

 

X

 

X

 

L

L-H

High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Power Down

D

None

 

X

L

 

X

L

L

 

X

 

 

X

 

X

 

L

L-H

High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselect Cycle, Continue

D

None

 

X

X

 

X

L

H

 

X

 

 

X

 

X

 

L

L-H

High-Z

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

R

External

 

L

H

 

L

L

L

 

H

 

 

X

 

L

 

L

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

B

Next

 

X

X

 

X

L

H

 

X

 

 

X

 

L

 

L

L-H

Q

1,10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Read, Begin Burst

R

External

 

L

H

 

L

L

L

 

H

 

 

X

 

H

 

L

L-H

High-Z

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dummy Read, Continue Burst

B

Next

 

X

X

 

X

L

H

 

X

 

 

X

 

H

 

L

L-H

High-Z

1,2,10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Begin Burst

W

External

 

L

H

 

L

L

L

 

L

 

 

L

 

X

 

L

L-H

D

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

B

Next

 

X

X

 

X

L

H

 

X

 

 

L

 

X

 

L

L-H

D

1,3,10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOP/Write Abort, Begin Burst

W

None

 

L

H

 

L

L

L

 

L

 

 

H

 

X

 

L

L-H

High-Z

2,3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Abort, Continue Burst

B

Next

 

X

X

 

X

L

H

 

X

 

 

H

 

X

 

L

L-H

High-Z

1,2,3,10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Edge Ignore, Stall

 

Current

 

X

X

 

X

L

X

 

X

 

 

X

 

X

 

H

L-H

-

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode

 

None

 

X

X

 

X

H

X

 

X

 

 

X

 

X

 

X

X

High-Z

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.Continue Burst cycles, whether read or write, use the same control inputs; a Deselect continue cycle can only be entered into if a Deselect cycle is executed first

2.Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A write abort occurs when the W pin is sampled low, but no byte write pins are active, so no write operation is performed.

3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles.

4.If CKE high occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE high occurs during a write cycle, the bus will remain in High Z.

5.X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are low

6.All inputs, except G and ZZ, must meet setup and hold times of rising clock edge.

7.Wait states can be inserted by setting CKE high.

8.This device contains circuitry that ensures all outputs are in High Z during power-up.

9.A 2-bit burst counter is incorporated.

10.The address counter is incriminated for all Burst continue cycles.

Rev: 1.02 11/2002

6/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

GSI GS842Z36AB-180I, GS842Z36AB-180, GS842Z36AB-166I, GS842Z36AB-166, GS842Z36AB-150I Datasheet

Preliminary

GS842Z18/36AB-180/166/150/100

Pipelined and Flow Through Read-Write Control State Diagram

 

 

D

B

 

 

 

Deselect

W

 

 

 

R

 

 

 

D

D

 

 

New Read

W

 

New Write

 

 

R

 

R

 

 

W

 

 

 

 

 

B

 

 

B

 

 

 

 

 

R

W

R

W

 

 

 

 

 

Burst Read

 

 

Burst Write

 

B

 

 

B

 

D

 

 

D

Key

Input Command Code

 

Notes

 

 

 

 

 

 

ƒ Transition

 

 

 

 

 

 

 

 

 

 

Current State (n)

Next State (n+1)

 

 

 

 

 

 

 

n

n+1

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock (CK)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Command

 

 

 

 

ƒ

 

 

ƒ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Current State

 

Next State

1.The Hold command (CKE Low) is not

shown because it prevents any state change.

2.W, R, B, and D represent input command

codes as indicated in the Synchronous Truth Table.

n+2 n+3

ƒ ƒ

Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram

Rev: 1.02 11/2002

7/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS842Z18/36AB-180/166/150/100

Pipeline Mode Data I/O State Diagram

Intermediate

 

Intermediate

 

 

R

Intermediate

B W

R

 

 

B

 

 

 

 

 

 

High Z

 

 

 

 

Data Out

 

 

W

 

(Data In)

 

 

 

(Q Valid)

D

 

Intermediate

Intermediate

 

D

 

W R

High Z

B

D

Intermediate

Key

Input Command Code

Notes

 

1.

The Hold command

 

Low) is not

 

 

 

(CKE

 

ƒ Transition

 

 

shown because it prevents any state change.

 

Transition

2.

W, R, B, and D represent input command

 

 

 

Current State (n) Intermediate State (N+1)

Next State (n+2)

codes as indicated in the Truth Tables.

 

 

 

n

n+1

n+2

n+3

Clock (CK)

Command

 

 

 

 

ƒ

 

 

 

ƒ

 

 

 

ƒ

 

 

 

ƒ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Current State

 

Intermediate

 

Next State

 

 

 

 

 

 

 

 

 

 

 

State

 

 

 

 

 

 

 

 

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.02 11/2002

8/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS842Z18/36AB-180/166/150/100

Flow Through Mode Data I/O State Diagram

B W

R

 

R B

 

 

 

High Z

 

 

 

Data Out

 

W

 

(Data In)

 

 

(Q Valid)

D

 

 

 

D

W R

High Z

B

D

Key

Input Command Code

Notes

 

1.

The Hold command

 

Low) is not

 

 

 

 

(CKE

 

ƒ Transition

 

 

 

shown because it prevents any state change.

 

 

 

2.

W, R, B, and D represent input command

 

 

 

 

Current State (n)

Next State (n+1)

 

codes as indicated in the Truth Tables.

 

 

 

 

 

n

 

n+1

n+2

n+3

Clock (CK)

Command

 

 

 

 

ƒ

 

 

 

ƒ

 

 

 

ƒ

 

 

 

ƒ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Current State

 

Next State

 

 

 

 

 

 

 

 

Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram

Rev: 1.02 11/2002

9/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS842Z18/36AB-180/166/150/100

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name

Pin Name

State

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

Linear Burst

Burst Order Control

LBO

H or NC

Interleaved Burst

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

Flow Through

Output Register Control

 

FT

 

 

 

 

H or NC

Pipeline

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Down Control

 

ZZ

L or NC

Active

 

 

 

 

H

Standby, IDD = ISB

 

 

 

 

 

 

FLXDrive Output Impedance Control

 

ZQ

L

High Drive (Low Impedance)

 

 

 

 

H or NC

Low Drive (High Impedance)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

There is a are pull-up devices on the LBO, ZQ, and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.

Burst Counter Sequences

Linear Burst Sequence

 

A[1:0]

A[1:0]

A[1:0]

A[1:0]

 

 

 

 

 

 

 

 

 

 

1st address

00

01

10

11

 

 

 

 

 

2nd address

01

10

11

00

 

 

 

 

 

3rd address

10

11

00

01

 

 

 

 

 

4th address

11

00

01

10

 

 

 

 

 

Note: The burst counter wraps to initial state on the 5th clock.

Interleaved Burst Sequence

 

A[1:0]

A[1:0]

A[1:0]

A[1:0]

 

 

 

 

 

 

 

 

 

 

1st address

00

01

10

11

 

 

 

 

 

2nd address

01

00

11

10

 

 

 

 

 

3rd address

10

11

00

01

 

 

 

 

 

4th address

11

10

01

00

 

 

 

 

 

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.02 11/2002

10/32

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

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