Fairchild Semiconductor SCAN18541TSSC, SCAN18541TSSCX Datasheet
© 2000 Fairchild Semiconductor Corporation DS010965 www.fairchildsemi.com
October 1991
Revised April 2000
SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs
SCAN18541T
Non-Inverting Line Driver with 3-STATE Outputs
General Description
The SCAN18541T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriente d paired output enable control signals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architectu re with the
incorporation of the defined boun dary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), an d Test Clock
(TCK).
Features
■ IEEE 1149.1 (JTAG) Compliant
■ Dual output enable signals per byte
■ 3-STATE outputs for bus-oriented applications
■ 9-bit data busses for parity applications
■ Reduced-swing outputs source 32 mA/sink 64 mA
■ Guaranteed to drive 50Ω transmission line to TTL input
levels of 0.8V and 2.0V
■ TTL compatible inputs
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP and HIGHZ instructions
■ Member of Fairchild’s SCAN Products
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram Pin Names
Tru th Tables
H = HIGH Voltage Level X = Immaterial
L = LOW Voltage Level Z = High Impedance
Order Number Package Number Package Description
SCAN18541TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names Description
AI
(0–8)
Input Pins, A Side
BI
(0–8)
Input Pins, B Side
AOE
1
, AOE23-STATE Output Enable Input Pins, A Side
BOE
1
, BOE23-STATE Output Enable Input Pins, B Side
AO
(0–8)
Output Pins, A Side
AO
(0–8)
Output Pins, B Side
Inputs
AO
(0–8)
AOE
1
AOE
2
AI
(0–8)
LLHH
HXXZ
XHXZ
LLLL
Inputs
BO
(0–8)
BOE
1
BOE
2
BI
(0–8)
LLHH
HXXZ
XHXZ
LLLL
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SCAN18541T
Block Diagrams
Byte A
Tap Controller
Byte B
Note: BSR stands for Boun dary Scan Register.
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SCAN18541T
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the followin g two types de pending upon t heir location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is locate d at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate their respective o utputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
The INSTRUCTION register is an 8-bit register which captures the default value of 1000 0001. The two least signifi -
cant bits of this captured value (0 1) are required by IEEE
Std 1149.1. The upper six bits are unique to the
SCAN18541T device. SCAN CMOS Test Access Logic
devices do not include the IEEE 1149.1 optional identifi cation register. Therefore, this un ique captu red value can be
used as a “pseudo ID” code to confirm that the correct
device is placed in the appropriate location in the boundary
scan chain.
Instruction Register Scan Chain Definition
MSB→LSB
Scan Cell TYPE1
Scan Cell TYPE2
Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGH-Z
All Others BYPASS
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SCAN18541T
Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register
Scan Chain Definition (42 Bits i n Length)
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