Fairchild Semiconductor SCAN18373TSSC, SCAN18373TSSCX Datasheet
© 2000 Fairchild Semiconductor Corporation DS010962 www.fairchildsemi.com
October 1991
Revised May 2000
SCAN18373T Tr ansparent Latch with 3-STATE Outputs
SCAN18373T
Transparent Latch with 3-STATE Outputs
General Description
The SCAN18373T is a high sp eed, low-powe r transparent
latch featuring separat e data input s organized into d ual 9bit bytes with byte-oriented latch enabl e and ou tput ena ble
control signals. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture with the incorporat ion of the defined boundary-scan
test logic and test access port consisting of Test Data Input
(TDI), Test Data Out (TDO), Test Mode Select (TMS ), and
Test Clock (TCK).
Features
■ IEEE 1149.1 (JTAG) Compliant
■ Buffered active-low latch enable
■ 3-STATE outputs for bus-oriented applications
■ 9-bit data busses for parity applications
■ Reduced-swing outputs source 32 mA/sink 64 mA
■ Guaranteed to drive 50
Ω transmission line to TTL input
levels of 0.8V and 2.0V
■ TTL compatible inputs
■ 25 mil pitch SSOP (Shrink Small Outline Package)
■ Includes CLAMP and HIGHZ instructions
■ Member of Fairchild’s SCAN Products
Ordering Code:
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Tru th Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
AO
0
= Previous AO before H-to-L transition of ALE
BO
0
= Previous BO before H-to-L transition of BLE
Order Number Package Number Package Description
SCAN1837TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names Description
AI
(0–8)
, BI
(0–8)
Data Inputs
ALE, BLE Latch Enable Inputs
AOE
1
, BOE
1
3-STATE Output Enable Inputs
AO
(0–8)
, BO
(0–8)
3-STATE Latch Outputs
Inputs
AO
(0–8)
ALE
AOE
1
AI
(0–8)
XH X Z
HL L L
HL H H
LL X AO
0
Inputs
BO
(0–8)
BLE
BOE
1
BI
(0–8)
XH X Z
HL L L
HL H H
LL X BO
0
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SCAN18373T
Functional Description
The SCAN18373T consists of two sets of nine D-type
latches with 3-STATE standard outputs. When the Latch
Enable (ALE or BLE) input is HIGH, data on the inputs
(AI
(0–8)
or BI
(0–8)
) enters the latches. In this condition the
latches are transparent, i.e., a latch output will change
state each time its inp ut changes. When Latch Enable is
LOW, the latches store the information that was present on
the inputs a set-up t ime preced ing the HIGH-to-LO W transition of the Latch E nable. The 3 -STATE standard outputs
are controlled by the Outpu t En able (A OE
1
or BOE1) input.
When Output Enabl e is LOW, the standard outp uts are in
the 2-state mode. When Output E nable is HIGH, the standard outputs are in the high impedance mode, but this
does not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Block Diagrams
Byte-A
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SCAN18373T
Block Diagrams (Continued)
Tap Controller
Byte-B
Note: BSR stands for Bounda ry Sc an Register.
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SCAN18373T
Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the follow ing two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data.
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activit y of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition Logic 0
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18373T device. SCAN CMOS Test Access
Logic devices do not include the IEEE 1149.1 optional
identification register. Therefore, this unique captured
value can be used as a “pseudo ID” code to confirm that
the correct device is pla ced in the appropria te location in
the boundary scan chain.
Instruction Register Scan Chain Definition
MSB
→ LSB
Scan Cell TYPE1
Scan Cell TYPE2
Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGHZ
All Others BYPASS
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