October 1995
Revised June 2000
NC7S02
TinyLogic HS 2-Input NOR Gate
General Description
The NC7S02 is a single 2-Input high performance CMOS NOR Gate. Advanced Silicon Gate CMOS fabrication assures high speed and low power circuit operation over a broad VCC range. ESD protection diodes inherently guard both inputs and output with respect to the VCC and GND rails. Three stages of gain between inputs and outputs assures high noise immunity and reduced sensitivity to input edge rate.
Features
■Space saving SOT23 or SC70 5-lead packages
■High Speed; tPD 3.5 ns typ
■Low Quiescent Power; ICC < 1 µ A
■Balanced Output Drive; 2 mA IOL, − 2 mA IOH
■Broad VCC Operating Range; 2V–6V
■Balanced Propagation Delays
■Specified for 3V operation
Ordering Code:
Order Number |
Package |
Product Code |
Package Description |
Supplied As |
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Number |
Top Mark |
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NC7S02M5 |
MA05B |
7S02 |
5-Lead SOT23, JEDEC MO-178, 1.6mm |
250 Units on Tape and Reel |
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NC7S02M5X |
MA05B |
7S02 |
5-Lead SOT23, JEDEC MO-178, 1.6mm |
3k Units on Tape and Reel |
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NC7S02P5 |
MAA05A |
S02 |
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide |
250 Units on Tape and Reel |
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NC7S02P5X |
MAA05A |
S02 |
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide |
3k Units on Tape and Reel |
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Logic Symbol |
Connection Diagram |
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IEEE/IEC |
(Top View)
Pin Descriptions |
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Function Table |
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Pin Names |
Description |
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Y = |
A + B |
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A, B |
Inputs |
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Inputs |
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Output |
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Y |
Output |
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A |
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B |
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Y |
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L |
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L |
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H |
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L |
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H |
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L |
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H |
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L |
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L |
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H |
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H |
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L |
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H = HIGH |
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Logic Level |
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L = LOW Logic Level |
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TinyLogic is a trademark of Fairchild Semiconductor Corporation.
Gate NOR Input-2 HS TinyLogic NC7S02
© 2000 Fairchild Semiconductor Corporation |
DS012140 |
www.fairchildsemi.com |
NC7S02
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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@ VIN ≤ |
− |
0.5V |
− 20 mA |
@ VIN ≥ |
VCC + 0.5V |
+ 20 mA |
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DC Input Voltage (VIN) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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@ VOUT < |
− 0.5V |
− 20 mA |
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@ VOUT > |
VCC + 0.5V |
+ 20 mA |
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DC Output Voltage (VOUT) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IOUT) |
± 12.5 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± 25 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
150° C |
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Lead Temperature (TL) |
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(Soldering, 10 seconds) |
260° C |
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Power Dissipation (PD) @ + 85° C |
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SOT23-5 |
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200 mW |
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SC70-5 |
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150 mW |
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC) |
2.0V to 6.0V |
Input Voltage (VIN) |
0V to VCC |
Output Voltage (VOUT) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Input Rise and Fall Time (tr, tf) |
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VCC @ 2.0V |
0 to 1000 ns |
VCC @ 3.0V |
0 to 750 ns |
VCC @ 4.5V |
0 to 500 ns |
VCC @ 6.0V |
0 to 400 ns |
Thermal Resistance (θ JA) |
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SOT23-5 |
300° C/W |
SC70-5 |
425° C/W |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
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TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Min |
Typ |
Max |
Min |
Max |
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VIH |
HIGH Level Input Voltage |
2.0 |
1.50 |
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1.50 |
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V |
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3.0-6.0 |
0.7 VCC |
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0.7 VCC |
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VIL |
LOW Level Input Voltage |
2.0 |
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0.50 |
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0.50 |
V |
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3.0-6.0 |
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0.3 VCC |
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0.3 VCC |
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VOH |
HIGH Level Output Voltage |
2.0 |
1.90 |
2.0 |
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1.90 |
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3.0 |
2.90 |
3.0 |
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2.90 |
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V |
IOH = |
− |
20 µ A |
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4.5 |
4.40 |
4.5 |
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4.40 |
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VIN = |
VIL |
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6.0 |
5.90 |
6.0 |
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5.90 |
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VIN = |
VIL |
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3.0 |
2.68 |
2.85 |
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2.63 |
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V |
IOH = |
− |
1.3 mA |
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4.5 |
4.18 |
4.35 |
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4.13 |
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IOH = |
− |
2 mA |
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6.0 |
5.68 |
5.85 |
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5.63 |
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IOH = |
− |
2.6 mA |
VOL |
LOW Level Output Voltage |
2.0 |
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0.0 |
0.10 |
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0.10 |
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3.0 |
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0.0 |
0.10 |
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0.10 |
V |
IOL = |
20 µ A |
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4.5 |
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0.0 |
0.10 |
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0.10 |
VIN = |
VIH |
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6.0 |
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0.0 |
0.10 |
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0.10 |
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VIN = |
VIH |
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3.0 |
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0.1 |
0.26 |
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0.33 |
V |
IOL = |
1.3 mA |
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4.5 |
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0.1 |
0.26 |
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0.33 |
IOL = |
2 mA |
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6.0 |
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0.1 |
0.26 |
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0.33 |
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IOL = |
2.6 mA |
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IIN |
Input Leakage Current |
6.0 |
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± 0.1 |
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± 1.0 |
µ A |
VIN = |
VCC, GND |
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ICC |
Quiescent Supply Current |
6.0 |
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1.0 |
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10.0 |
µ A |
VIN = |
VCC, GND |
www.fairchildsemi.com |
2 |
AC Electrical Characteristics
Symbol |
Parameter |
VCC |
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TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
Conditions |
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Fig. No. |
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(V) |
Min |
Typ |
Max |
Min |
Max |
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tPLH, |
Propagation Delay |
5.0 |
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3.5 |
15 |
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ns |
CL = |
15 pF |
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tPHL |
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2.0 |
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19 |
100 |
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125 |
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Figures |
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3.0 |
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10.5 |
27 |
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35 |
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ns |
CL = |
50 pF |
1, 3 |
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4.5 |
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7.5 |
20 |
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25 |
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6.0 |
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6.5 |
17 |
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21 |
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tTLH, |
Output Transition Time |
5.0 |
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3 |
10 |
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CL = |
15 pF |
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tTHL |
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2.0 |
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25 |
125 |
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155 |
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Figures |
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3.0 |
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16 |
35 |
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45 |
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ns |
CL = |
50 pF |
1, 3 |
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4.5 |
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11 |
25 |
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31 |
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6.0 |
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9 |
21 |
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26 |
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CIN |
Input Capacitance |
Open |
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2 |
10 |
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10 |
pF |
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CPD |
Power Dissipation Capacitance |
5.0 |
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6 |
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pF |
(Note 3) |
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Figure 2 |
Note 3: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD)(VCC)(fIN) + (ICCstatic).
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tw = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 3. AC Waveforms
Input = AC Waveform;
PRR = variable; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
NC7S02
3 |
www.fairchildsemi.com |