October 1987
Revised January 1999
CD4013BC
Dual D-Type Flip-Flop
General Description
The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent data, set, reset, and clock inputs and “Q” and “Q ” outputs. These devices can be used for shift register applications, and by connecting “Q” output to the data input, for counter and toggle applications. The logic level present at the “D” input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line respectively.
Features
■Wide supply voltage range: 3.0V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL: fan out of 2 driving 74L compatibility: or 1 driving 74LS
Applications
•Automotive
•Data terminals
•Instrumentation
•Medical electronics
•Alarm system
•Industrial electronics
•Remote metering
•Computers
Ordering Code:
Order Number |
Package Number |
Package Description |
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CD4013BCM |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
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CD4013BCSJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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CD4013BCN |
N14A |
14-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
Pin Assignments for DIP, SOIC and SOP
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CL |
D |
R |
S |
Q |
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Q |
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(Note 1) |
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0 |
0 |
0 |
0 |
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1 |
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1 |
0 |
0 |
1 |
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0 |
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x |
0 |
0 |
Q |
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Q |
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x |
x |
1 |
0 |
0 |
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1 |
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x |
x |
0 |
1 |
1 |
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0 |
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x |
x |
1 |
1 |
1 |
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1 |
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No Change
x = Don't Care Case
Note 1: Level Change
Top View
Flop-Flip Type-D Dual CD4013BC
© 1999 Fairchild Semiconductor Corporation |
DS005946.prf |
www.fairchildsemi.com |
CD4013BC
Schematic Diagrams
Logic Diagram
www.fairchildsemi.com |
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