Size:
3.03 Mb
Download

Common Switch Region:Ethernet Core Switch (optional)

Figure 4-2: VSC7376 GbE Switch Block Diagram

Frame Bus

 

Shared RX and

 

 

Shared RX and

 

TX FIFO

 

 

TX FIFO

Port Block

Policer

Shaper

 

Port Block

Policer

Shaper

Categorizer

Rewriter

 

Categorizer

Rewriter

 

10/100/1000

 

 

10/100/1000

 

MAC

 

 

MAC

 

 

 

 

 

 

 

 

 

SGMII/SerDes

 

 

 

SGMII/SerDes

Switch Configuration

Analyzer/Arbiter

8051 CPU (iCPU)

 

RS232 Interface

 

Serial Interface

RS232

Parallel Interface

 

MII Management Interface

MIIM

Control/Status

Registers

 

 

GPIO

 

 

SI

PI or iCPU

 

RAM/Flash

The processor has a local bus connection to the Ethernet core switch and the fat pipe switch module (reads and writes directly to the registers). On power-up,the configuration values are read from flash and the chip is initialized.

To configure the switch, see the KAT4000 Quick Start Guide,#10008585-xx.For theno-CPUKAT4000 Ethernet switch configuration, see Appendix A or theKAT4000 Quick Start Guide for the No-CPU Carrier Board,#10008506-xx.

High-SpeedSerial Data Path Configuration

The KAT4000 design implements several types of high-speedserial protocols: Gbe, sRIO, and PCIe. Proper setup of the devices driving data onto and receiving data from the interconnecting transmission lines is important for optimal performance. Configurable device parameters include drive strength, gain, impedance, equalization, andpre-emphasis.The configuration of some serial paths has been set by Emerson and should not be changed. For paths that go off the board (e.g., to AMC sites, the backplane), the user must be aware of device register settings for devices at both ends of the transmission line and set them appropriately to meet device specifications and achieve full bandwidth performance.

10007175-02

KAT4000 User’s Manual

4-3

 

 

 

Common Switch Region:Ethernet Core Switch (optional)

On-BoardPath Device Settings

Caution: On-boarddevice values are determined by Emerson. Do not change these values. Altering

!on-boarddevice values could cause system failure.

Note: Proprietary information regarding register function or effect is not available in this user’s manual. Please contact the PHY or switch manufacturer directly for details.

Table 4-1 lists the KAT4000 PHYs and their respective addresses.

Table 4-1: KAT4000 PHYs and Address Values

PHY:

Address:

Base Channel 1/TSEC2

0x2

 

 

Base Channel 2/TSEC3

0x3

 

 

TSEC2 (from CPU to Ethernet switch)

0x4

 

 

TSEC3 (from CPU to Ethernet switch)

0x5

 

 

Fat Pipe/TSEC4

0x6

 

 

The Ethernet core switch has the following on-boardports: 14, 15, 16 and 17. The Ethernet switch on the GbE fat pipe switch module useson-boardport 13.

Off-BoardPath Device Settings

Modify off-boardregister values with the switch_reg or phy commands. See “phy” on page14-25or “switch_reg” on page14-27for details.

Note: Proprietary information regarding register function or effect is not available in this user’s manual. Please contact the switch manufacturer directly for details.

Table 4-2 shows the Ethernet core switch defaultoff-boardports.

Table 4-2: Ethernet Core SwitchOff-BoardPorts

Destination:

Port:

Update Channel

7,8,9,10

 

 

Zone 3

4,6

 

 

AMC1-4

12,13,18,20,1

 

 

4-4

KAT4000 User’s Manual

10007175-02

 

 

 

Table 4-4

Common Switch Region:Ethernet Address for the KAT4000

Table 4-3 shows the GbE fat pipe’s Ethernet switch defaultoff-boardports.

Table 4-3: GbE Fat Pipe Module Ethernet SwitchOff-BoardPorts

Destination:

Port:

AMC1

22,23,24,25

 

 

AMC2

18,19,20,21

 

 

AMC3

8,9,10,11

 

 

AMC4

14,15,16,17

 

 

Fabric Channel 1

4,5,6,7

 

 

Fabric Channel 2

0,1,2,3

 

 

Ethernet Transceivers

The Marvell 88E1111 gigabit Ethernet transceivers are used to interface between the processor MACs and the Ethernet switch ports. They are also used to connect two switch ports to the backplane base channel 1 and 2 interfaces. The 88E1111 device is 10/100/1000BASE-TIEEE 802.3 compliant.

The Broadcom BCM5241 10/100BASE-TX/FXtransceiver provides a physical interface to the processor’s debug Ethernet MAC (eTSEC1). The BCM5241 complies with the IEEE 802.3 standard.

ETHERNET ADDRESS FOR THE KAT4000

The Ethernet address for your board is a unique identifier on a network and must not be altered. The address consists of 48 bits (Medium Access Control—MAC[47:0]) divided into two equal parts. The upper 24 bits define a unique identifier that has been assigned to Artesyn Communication Products by IEEE. The lower 24 bits are defined by Artesyn for identification of each of our products.

The Ethernet address for the KAT4000 is a binary number referenced as 12 hexadecimal digits separated into pairs, with each pair representing eight bits. The address assigned to the KAT4000 has the following form:

00 80 F9 xx yy zz

00 80 F9 is Artesyn’s identifier. The last three bytes of the Ethernet address comprise the data for the Ethernet addresses in non-volatilememory (NVRAM). The KAT4000 has been assigned the Ethernet address range 00:80:F9:92:00:00 to 00:80:F9:95:FF:FF. The format is shown in .

10007175-02

KAT4000 User’s Manual

4-5

 

 

 

Common Switch Region:Ethernet Address for the GbE Fat Pipe

Table 4-4: Ethernet Port Address Numbering

 

 

 

Ethernet

 

 

 

Identifier

Offset:

MAC:

Description:

(Hex):

Byte 5

15:0

LSB of (serial number -1000)

 

 

 

 

Byte 4

 

MSB of (serial number -1000)

 

 

 

 

Byte 3

23:16

Port 4 (eTSEC4)

95

 

 

 

 

 

 

Port 3 (eTSEC3)

94

 

 

 

 

 

 

Port 2 (eTSEC2)

93

 

 

 

 

 

 

Port 1 (eTSEC1)

92

 

 

 

 

Byte 2

47:24

Assigned to Artesyn by IEEE

F9

 

 

 

 

Byte 1

 

 

80

 

 

 

 

Byte 0

 

 

00

 

 

 

 

The last pair of hex numbers correspond to the following formula: n — 1000, wheren is the unique serial number assigned to each board. For example, if the serial number of a KAT4000 is 2867, the calculated value is 1867 (74B16). Therefore, the board’s port 2 Ethernet address is 00:80:F9:93:07:4B. The ports are assigned as follows:eTSEC1—Ethernetdebug port,eTSEC2—Ethernetcore switch,eTSEC3—Ethernetcore switch, andeTSEC4—fatpipe switch module.

ETHERNET ADDRESS FOR THE GBE FAT PIPE SWITCH MODULE

The GbE fat pipe switch module has been assigned the Ethernet address range 00:80:F9:06:C0:00 to 00:80:F9:06:FF:FF. The address format is the same as described in “Ethernet Address for the KAT4000”.

4-6

KAT4000 User’s Manual

10007175-02

 

 

 

Common Switch Region:PCI Express Switch (optional)

PCI EXPRESS SWITCH (OPTIONAL)

The optional PLX Technology, Inc. PEX 8524 PCI Express switch device contains 24 PCI

Express lanes and up to six ports. The PCIe switch supports the following:

One port connected from each AMC site to the switch (AMC.0 and AMC.1)

One port connected from the processor to the switch (one x1 or one x4 port)

Four lanes connected from the fat pipe switch module to the switch with these possible port configurations: four x1 ports, two x2 ports or one x4 port.

Features of the switch include:

PCI Express interface at 2.5 Gbps transfer rate

24 PCI Express lanes (SerDes [7:0] and [32:16]) and up to six ports (assign x1, x2, or x4 lanes to ports 0, 1, 8, 9, 10 or 11)

Link power management states (L0, L0s, L1, L2/L3 Ready and L3) and device power management states (D0 and D3hot)

EEPROM interface signals

JTAG boundary scan interface signals

Compliant with PCI Express Base 1.0aand PCI Standard Hot Plug r1.0

Note: The device ID for the PEX 8524 switch reads “8532h” because the PEX 8524 and PEX 8532 share the same base device.

For more information, reference the PEX 8524 Versatile PCI Express™ Switches Data Book.

Note: Proprietary information on the PCIe switch is not available in this user’s manual. Please refer to the PLX

Technology web site for documentation, http://www.plxtech.com.

10007175-02

KAT4000 User’s Manual

4-7

 

 

 

Common Switch Region:PCI Express Switch (optional)

PCI Express Interface

Figure 4-3: PEX 8524 Block Diagram

 

Station 0

 

 

 

 

 

 

 

 

Station 1

Ingress

 

 

 

 

 

Egress

 

 

 

 

 

 

 

 

 

 

 

Lanes

Scheduler

 

 

 

 

 

Scheduler

 

Lanes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Crossbar

 

 

 

 

Crossbar

 

 

 

 

 

 

Switch

 

 

 

 

Switch

 

 

 

 

 

 

Ingress

 

 

 

 

Egress

 

 

 

 

PCI Express

 

 

 

 

Non-Blocking

 

 

 

 

PCI Express

 

 

 

 

 

 

 

 

 

 

 

 

Upstream

 

 

 

 

Crossbar

 

 

 

 

Downstream

 

 

Station 0

 

 

 

 

Switch Fabric

 

 

 

 

Station 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Crossbar

 

 

 

 

Crossbar

 

 

 

 

 

 

Switch

 

 

 

 

Switch

 

 

 

 

 

 

Egress

 

 

 

 

Ingress

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Egress

 

 

 

 

Ingress

 

 

 

 

 

 

 

 

 

 

 

 

 

Scheduler

 

 

 

Scheduler

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The stations implement the PCI Express Base 1.0a Physical, Data Link, and Transaction layers. Each PCI Express station is able to support up to 16 integratedSerializer/De-serializer1000Base-BX(SerDes) modules, which provide PCI Express hardware interface lanes. These lanes can be configured to support up to four PCI Express ports per station. The PEX 8524 contains two stations (Station 0 and Station 1), connected bynon-blockingCrossbar Switch fabric.

From the system model viewpoint, each PCI Express port is a virtual PCI-to-PCIbridge device and contains its own set of PCI Express Configuration registers. One of the ports on either station can be designated the Upstream port (or primary bus in PCI terms). Through use of the Upstream port, the firmware configures the other ports during standard PCI enumeration.

Note: The PCI Express Upstream Station supports Upstream ports and Downstream ports at the same time, but lanes from different stations cannot be combined to form ports.

4-8

KAT4000 User’s Manual

10007175-02

 

 

 

Common Switch Region:PCI Express Switch (optional)

EEPROM Interface

The PEX 8524 has an embedded 64-kilobyteSPI EEPROM controller. This direct interface provides the 7.8 MHz serial clock (EE_SK), chip select (EE_CS*), and data output (EE_DO) for the EEPROM; and receives data input (EE_DI) from the EEPROM.

Figure 4-4: PEX 8524 SPI EEPROM Interface

+3.3 V

+3.3 V

EE_CS*

Initialization EE_DI

Serial EE_DO

EEPROM

Configuration Data

Port 0

Port 1

Port 8 Port 9 Port 10

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Controller Interface

The PEX 8524 supports a five pin JTAG interface that complies with IEEE standard 1149.1 and 1149.6 Boundary-Scansignals. The JTAG interface consists of the following signals:

Table 4-5: PEX 8524 JTAG Signals

 

Signal

 

 

Signal:

Name:

Type:

Description:

JTAG_ TCK

Test clock

in

This is the clock source for the PEX 8524

 

 

 

Test Access Port (TAP) and may be any

 

 

 

frequency from 0 to 10 MHz.

 

 

 

 

JTAG_ TDI

Test data input

in

This inputs data to the TAP.

 

 

 

 

JTAG_ TDO

Test data

out

This transmits serial data from the TAP.

 

output

 

 

 

 

 

 

JTAG_ TMS

Test mode

in

The TAP state machine uses the TMS to

 

select

 

determine the TAP mode.

 

 

 

 

JTAG_ TRST*

Test reset

in

This resets JTAG and the TAP. It should be

 

 

 

toggled or held at 0 for the PEX 8524 to

 

 

 

function properly.

 

 

 

 

10007175-02

KAT4000 User’s Manual

4-9

 

 

 

(blank page)

4-10

KAT4000 User’s Manual

10007175-02

 

 

 

Section 5

Fat PipeSwitch Module

The fat pipe switch module is a plug-overmodule that provides ahigh-speedinterconnect between the AMC modules, the ATCAhigh-speedfabric ports, the processor, and the Ethernet core switch or the PCIe switch on the KAT4000. There are four configurations of the fat pipe switch module: GbE, 10GbE-1GbE, 10GbE-10GbE and sRIO.

Note: The 10GbE-10GbE and sRIO modules are not yet available for order.

All fat pipe switch configurations support:

Four ports connected from each AMC site to the fat pipe switch capable of interchangeably using GbE, sRIO or 10 GbE protocols

Eight GbE 1000Base-BX(SerDes) ports connected from the backplanehigh-speedfabric to the fat pipe switch

Two ports connected from the fat pipe switch to Zone 3 for (optional) RTM access

The GbE and 10 GbE configurations also provide:

One port for a dedicated GbE channel from the MPC8548 processor to the fat pipe switch

One port for a dedicated GbE channel from the Ethernet core switch to the fat pipe switch

The sRIO configuration also provides:

One or four ports for a dedicated sRIO channel from the MPC8548 processor to the fat pipe switch

10007175-02

KAT4000 User’s Manual

5-1

 

 

 

Fat PipeSwitch Module: GbE Fat Pipe Switch Module

GBE FAT PIPE SWITCH MODULE

Fig. 5-1 shows how the GbE fat pipe switch module maps to ports defined by the AMC.0 specification; seeFig. 1-3 for the full port mapping diagram.

Figure 5-1: AMC Port Map Fat PipesRegion–GbE

Basic

Connector

Port # Port Mapping

4

 

 

GbE x1

 

5

Fat Pipes Region

 

GbE x1

 

6

 

 

 

 

GbE x1

 

 

 

 

7

 

 

GbE x1

 

 

AMC.0 Definition

GbE Fat Pipe

 

 

Switch Module

Implementation

Fat Pipes: This region supports data path connections such as GbE. It can carry large amounts of data without significantly degrading the speed of transmission.

x1: This refers to the link width of the port (the number of lanes that can be used to interconnect between two link partners).

The following diagram shows the implementation of the GbE fat pipe switch module on the KAT4000:

Figure 5-2: Signal Routing of the GbE Fat Pipe Switch Module on the KAT4000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AMC (x4) Single Wide,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Half/Full/Extended Height

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AMC.0 Common

AMC.z

Extended

 

 

 

 

 

 

 

 

 

 

Fat Pipes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSC7376

 

 

 

 

 

 

 

 

 

 

 

 

Ethernet Core Switch

 

 

 

 

4 GbE

 

 

 

 

 

 

 

 

Layer 2

 

 

 

 

 

 

 

 

 

 

 

 

RGMII GbE

GbE

Fat Pipe Switch Module

2 GbE

 

I2C

 

PHY

 

 

 

 

 

 

 

 

 

MPC8548

 

 

 

GbE

 

 

 

 

 

 

Fat Pipe

 

 

 

 

 

 

 

 

 

 

 

 

Processor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Local bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 GbE

4 GbE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base

 

 

 

High Speed

High Speed Clock

RTM I/O

 

 

 

 

 

 

 

 

Fabric A

Fabric B

 

(Optional)

 

 

 

 

 

 

 

 

J23

 

J20

 

Zone 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5-2

KAT4000 User’s Manual

10007175-02