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Central Processing Unit: Interrupts and Exception Processing

Noncritical: The processor is able to change program flow to handle conditions generated by external signals, errors, or unusual conditions. The Save and Restore registers, SRR0/SRR1, save state when they are taken and use the rfi instruction to restore state. The external interrupt enable bit, MSR[EE], can mask these asynchronous interrupts.

Critical: The Critical Save and Restore registers, CSRR0/CSRR1, save state when they are taken during a noncritical interrupt or regular program flow and use the rfci instruction to restore state. The critical enable bit, MSR[CE], can mask these interrupts. This interrupt also includes watchdog timertime-outinputs.

Machine State Register

The Machine State register (MSR) configures the state of the MPC8548. On initial power-upof the KAT4000, most of the MSR bits are cleared. Please refer to theMPC8548 PowerQuicc III Integrated Communications Processor Reference Manual for more detailed descriptions of the individual bit fields.

Register 3-4: CPU Machine State Register (MSR)

32

 

 

 

36

37

38

39

 

 

 

44

45

46

47

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

UCLE

SPE

 

reserved

 

 

WE

CE

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48

49

50

51

52

53

54

55

57

58

59

60

61

62

63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EE

PR

R

ME

R

UBLE

DE

reserved

 

IS

D

R

PM

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R: Reserved should be cleared.

UCLE: User-modeCache LockEnable—restrictsuser-modecache-linelocking by the operating system.

0Any cache lock instruction takes a cache-lockingDSI exception

1A cache-lockingDSI is not taken

SPE: Signal Processing Engine enable

0An SPE APU unavailable exception occurs

1Software can execute supported SPE and SPFP APU instructions

WE: Wait stateEnable—allowsthe core complex to signal a request for power management.

0CPU continues processing

1CPU enters wait state

CE: Critical Enable

0Critical input and watchdog timer interrupts disabled

1Critical input and watchdog timer interrupts enabled

10007175-02

KAT4000 User’s Manual

3-9

 

 

 

Central Processing Unit:Peripheral Interface

EE:External interrupt Enable—allowsthe processor to take external input,fixed-intervaltimer, system management, performance monitor, or decrementer interrupts.

0 Disabled

1 Enabled

PR: Privilege level

0Supervisor-levelinstructions are executed

1User-levelinstructions are executed

ME: Machine check Enable

0Machine check interrupts disabled

1Machine check interrupts enabled

UBLE: User BTB Lock Enable

0Execution of the BTB lock instructions for user mode disabled

1Execution of the BTB lock instructions for user mode enabled

IS: Instruction address Space

0CPU directs all instruction fetches to address space 0

1CPU directs all instruction fetches to address space 1

DS: Data address Space

0CPU directs data memory accesses to address space 0

1CPU directs data memory accesses to address space 1

PM: Marks a process for the Performance Monitor

0Process is not marked

1Process is marked

PERIPHERAL INTERFACE

The MPC8548 uses the peripheral bus to communicate with its peripherals. Table 3-3 lists the order in which the processor handles requests from peripherals.

Table 3-3: MPC8548 Peripheral Request Priority

Priority:

Function:

Request:

Highest

1

Reset in the Communication Processor Command register (CPCR)

 

 

or System Reset (SRESET*)

 

 

 

 

2

SDMA bus error

 

 

 

 

3

Commands issued to the CPCR

 

 

 

 

4

Emergency (from FCCs, MCCs, and SCCs)

 

5

IDMA(1-4)emulation (default option 1)11

 

6

FCC1 receive

 

 

 

 

7

FCC1 transmit

 

 

 

3-10

KAT4000 User’s Manual

10007175-02

 

 

 

Central Processing Unit: MPC8548 Peripheral Modules

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Priority:

 

Function:

 

Request: (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

MCC1 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

MCC2 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

MCC1 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

MCC2 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

FCC2 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

FCC2 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

 

 

FCC3 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

 

 

 

 

FCC3 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

SCC1 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

 

 

 

 

 

 

 

SCC1 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

 

 

 

 

 

SCC2 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

 

 

 

 

 

 

SCC2 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

SCC3 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

 

 

 

 

 

SCC3 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

 

 

 

 

 

 

 

SCC4 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

 

 

 

 

 

 

 

SCC4 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

 

 

 

 

 

 

 

IDMA(1-4)Emulation (option 2)11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

 

 

 

 

 

 

SMC1 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

 

 

 

 

SMC1 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

 

 

 

 

 

 

SMC2 receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

 

 

 

 

 

SMC2 transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

 

 

 

 

 

 

SPI receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

 

 

 

 

 

 

SPI transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

 

 

I2C receive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

 

 

 

 

 

 

I2C transmit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

 

 

 

 

 

 

RISC timer table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Lowest

 

34

 

 

 

 

 

 

 

IDMA(1-4)emulation (option 3)11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. The priority of each IDMA channel is programmed independently.

MPC8548 PERIPHERAL MODULES

Three-SpeedEthernet Controllers (TSEC)

Two TSECs incorporate a MAC sublayer that supports 10 Mbps, 100 Mbps, and 1 Gbps

Ethernet networks. See Chapter 4 for information on the Ethernet interface.

10007175-02

KAT4000 User’s Manual

3-11

 

 

 

Table 3-4

Central Processing Unit: Processor Reset and Clocking Signals

Local Bus Controller (LBC)

The MPC8548 LBC connects to external memory, DSP and ASIC devices. There are three separate state machines:

General-PurposeChip Select Machine (GPCM) controls access to asynchronous devices

User Programmable Machine (UPM) interfaces synchronous devices

The Synchronous DRAM (SDRAM) controller provides access to standard SDRAM

Chip Select Generation

The MPC8548 memory controller functions as a chip select (CS) generator to access onboard memory devices, saving the board’s area which results in reduced cost, power consumption, and increased flexibility. lists the chip selects for the KAT4000 module.

Table 3-4: MPC8548 Chip Select

Select:

Assignment:

CS0*

Boot (Socketed or NOR Flash)22

CS1*

Flash 0

 

 

CS2*

Flash 1

 

 

CS3*

Socketed Flash

 

 

CS4*

KSL Programmable Logic Device (PLD)

 

 

CS5*

NAND Flash

 

 

CS6*

Ethernet Core Switch

 

 

CS7*

Fat Pipe

 

 

2. Jumper selectable (see “Jumpers” on page 2-5for jumper options).

PROCESSOR RESET AND CLOCKING SIGNALS

The MPC8548 external reset and clocking signals include:

HRESET*: Hard Reset input completely resets the MPC8548 and causes apower-onreset (POR) sequence.

HRESET_REQ*: Hard Reset Request output causes internal block requests that HRESET* be asserted. This can be requested by a hardware device, for example a watchdog timer event.

SRESET*: Soft Reset input causes a machine check interrupt assertion to the e500 core to undergo its soft reset sequence.

READY: Ready output means the MPC8548 has completed the reset operation and is not in apower-down(nap, doze, or sleep) or debug state.

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Central Processing Unit: MPC8548 Exception Handling

SYSCLK: System Clock is the primary clock input to the e500 core and all the devices and interfaces that operate synchronously with the core.

RTC: Real-TimeClock is an input to the MPC8548. Optionally, it can be used to clock the e500 core timer facilities and by the MPC8548 PIC global timer facilities.

MPC8548 EXCEPTION HANDLING

Each type of CPU exception transfers control to a different address in the vector table. The vector table normally occupies the first 8 kilobytes of RAM (with a base address of 0000,000016) or Flash (with a base address of E000,000016). An unassigned vector position may be used to point to an error routine or for code or data storage.

Table 3-5 lists the exceptions recognized by the MPC8548 and the conditions that cause them.

Table 3-5: MPC8548 Exceptions

 

 

Vector

 

 

 

OffsetHex

 

IVOR:

Type:

Address:

Notes:

 

reserved

00000

IVOR0

Critical Input

00100

Caused when MSR[CE]=1

 

 

 

 

IVOR1

Machine Check

00200

Caused when MSR[ME]=1

 

 

 

 

IVOR2

Data Storage

00300

Caused by one of the following exception conditions: read

 

Interrupt (DSI)

 

access control, write access control, byte-ordering,cache

 

 

 

locking or storage synchronization

 

 

 

 

IVOR3

Instruction Storage

00400

Caused by one of the following exception conditions:

 

Interrupt (ISI)

 

execute access control or byte-ordering

 

 

 

 

IVOR4

External Interrupt

00500

Caused when MSR[EE]=1

 

 

 

 

IVOR5

Alignment

00600

Caused when the processor core cannot perform a

 

 

 

memory access

 

 

 

 

IVOR6

Program Check

00700

Caused by one of the following exception conditions:

 

 

 

illegal instruction, privileged instruction, trap or

 

 

 

unimplemented operation

 

 

 

 

IVOR7

Floating-Point

00800

If MSR[FP]=0, the floating point registers are disabled and

 

Unavailable

 

attempting to execute any floating point instruction

 

 

 

causes a floating point unavailable exception

 

 

 

 

IVOR8

System Call

00900

Caused by the execution of a System Call (sc) instruction

 

 

 

 

IVOR10

Decrementer

00A00

Caused when TSR[DIS]=1, TCR[DIE]=1 and MSR[EE]=1

 

 

 

 

IVOR11

Interval Timer

00B00

Caused when TSR[FIS]=1, TCR[FIE]=1 and MSR[EE]=1

 

 

 

 

IVOR12

Watchdog Timer

00C00

Caused when TSR[WIS]=1, TCR[WIE]=1 and MSR[CE]=1

 

 

 

 

IVOR13

Data TLB Error

00D00

Caused by a Data TLB Miss exception condition

 

 

 

 

IVOR14

Instruction TLB Error

00E00

Caused by an Instruction TLB Miss exception condition

 

 

 

 

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Central Processing Unit:JTAG/COP Interface

 

 

Vector

 

 

 

OffsetHex

 

IVOR:

Type:

Address:

Notes: (continued)

IVOR15

Debug

00F00

Caused when a debug exception exists in the DBSR and

 

 

 

when DBCR0[IDM]=1 and MSR[DE]=1

JTAG/COP INTERFACE

Caution:

!

A single JTAG/COP header is provided for debug purposes for the processor. This interface provides for boundary-scantesting of the CPU (seeFig. 3-2)and is compliant with the IEEE 1149.1 standard. The header pin assignments are defined inTable 3-6.

Installa shunt on JP1 pins 1:2 before using the JTAG/COP interface (P1) to enable CPU JTAG/COP access. Attempting to use the JTAG/COP interface without this shunt in place may cause damage to the board. Refer toTable 7-3 for JP1 pin details.

Figure 3-2: Processor JTAG/COP Diagram

Internal PU

TDO

TDI

TCK

MPC8548 TMS Processor

CKSTP_OUT*

TRST*

CPU_TDO

CPU_TDI

CPU_TCK

CPU_TMS

CPU_CKSTP_OUT*

CPU_HRESET* CPU_SRESET* CPU_TRST*

 

 

 

 

 

3_3V (2.5V optional)

 

 

 

 

 

.75A

 

3_3V

 

 

 

PICO_FUSE

 

 

 

 

COP

 

5.11K

5.11K

CPU_TDO

Debug

 

 

 

 

 

 

TDO

2

 

 

 

CPU_TDI

TDI

TRST*

 

 

 

CPU_TCK

 

5.11K

 

 

 

CPU_TMS

 

 

 

 

 

 

3_3V

5.11K

DEBUG_SRESET*

 

 

 

DEBUG_HRESET*

 

 

CPU_CKSTP_OUT*

KSL

PLD

Figure 3-3: Processor JTAG/COP Header

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Central Processing Unit: No Processor Configuration

Table 3-6: Processor JTAG/COP Pin Assignments (P1)

Pin:

Signal:

Pin:

Signal:

1

CPU_TDO

2

Not connected

3

CPU_TDI

4

DEBUG_TRST*

 

 

 

 

5

Not connected

6

JT_3_ 3V (fused)

7

CPU_TCK

8

Not connected

9

CPU_TMS

10

Not connected

11

DEBUG_SRESET*

12

GND

 

 

 

 

13

DEBUG_HRESET*

14

Not connected

15

CPU_CKSTP_OUT*

16

GND

 

 

 

 

CPU_CKSTP_OUT*: CheckstopOutput—whenasserted, this output signal indicates that the CPU has detected a checkstop condition and has ceased operation.

CPU_TCK: Test ClockInput—scandata is latched at the rising edge of this signal.

CPU_TDI: Test DataInput—thissignal acts as the input port for scan instructions and data.

CPU_TDO: Test DataOutput—thissignal acts as the output port for scan instructions and data.

CPU_TMS: Test ModeSelect—thisinput signal is the test access port (TAP) controller mode signal.

DEBUG_HRESET*: HardReset—thisinput signal indicates that a completePower-onReset must be initiated by the processor.

DEBUG_SRESET*: SoftReset—thisinput signal indicates that the processor must initiate a System Reset interrupt.

DEBUG_TRST*: TestReset—thisinput signal resets the test access port.

NO PROCESSOR CONFIGURATION

If a processor is not used on the KAT4000, the Ethernet core switch and GbE fat pipe switch module (optional) are managed by an 8051 microcontroller internal to each switch. Custom configuration of the switch is possible through one of two user interfaces on each switch. See “Appendix A” for more information.

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Section 4

Common Switch Region

The KAT4000 supports multiple interfaces. This chapter describes the Ethernet core switch, switch configuration, Ethernet address and PCI Express switch. The board area network (BAN) refers to the routing of the Ethernet ports using the Vitesse VSC7376 Gigabit Ethernet (GbE) core switch or the PCIe ports using the PEX 8524 PCI Express switch. The Ethernet core switch provides the interconnect between the fat pipe switch module, the Ethernet ports on the AMC sites, the processor, two channels on the ATCA backplane base fabric, Zone 3, and the Update Channel (optional) (see Fig. 4-1).The PCI Express switch provides the interconnect between the AMC sites, the processor, and the fat pipe switch module. Both switches are optional, however at least one of the two must be used on the board. The board can also use both switches.

Figure 4-1: Board Area Network

PEX8524

PCI Express Switch (Optional)

0

8:B1

9:B2

PCIe

 

 

 

10:B3

11:B4

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

7–10

 

To Update

Channel

 

 

4,6

 

 

GbE

on J20

(Optional)

 

 

 

0,2:B1 12,13:B2

 

 

 

 

 

 

GbE

 

 

 

 

 

 

18,20:B3 22,24:B4

 

 

 

 

 

 

GbE

 

 

 

 

 

11

 

 

 

 

 

GbE

 

 

 

 

15,17

14,16

 

 

PCIe

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GbE

10/100 Debug Eth (MII)

TSEC1

SERDES

10/100 PHY

Xfmr

Xfmr (2)

 

To Zone 3 (Optional)

IPMB Base

P10

AMC (x4) Single Wide,

Mid-Sizeor Compact

Port 0

Port 1

Ports 4-7Ports12-20

 

 

PCIe or GbE on port 1

SERDES

4 SERDES

 

GbE Fat Pipe

8–11:B3

 

14–17:B4

12

Switch Module 18–21:B2

 

(Optional)

22–25:B1

134–7

0–3

4 SERDES

 

4 SERDES

To

Core To

Eth Core

Switch Eth

(Opt.) Switch

 

 

Zone 3

 

 

Connections

4

2

(Opt.)

 

High Speed

High Speed Clock

RTM I/O

Fabric A

Fabric B

(Optional)

J23

J20

Zone 3

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Common Switch Region:Ethernet Core Switch (optional)

ETHERNET CORE SWITCH (OPTIONAL)

The optional Vitesse VSC7376 GbE switch is a multilayer switch with 26 tri-speed(10/100/1000 Mbps) SGMII Ethernet ports and integrated1000Base-BX(SerDes) interfaces. The GbE switch supports the following:

Two SGMII Ethernet ports connected from the switch to the ATCA backplane base fabric via PHYs (PICMG 3.0)

Two 1000Base-BX(SerDes) Ethernet ports routed between the processor and the switch

Up to two 1000Base-BX(SerDes) Ethernet ports routed between each AMC site and the switch (AMC.2)

One 1000Base-BX(SerDes) Ethernet port routed between the fat pipe switch module and the switch (AMC.2)

Four 1000Base-BX(SerDes) Ethernet ports connected from the switch to the Update Channel interface on J20 on the backplane (optional)

Two 1000Base-BX(SerDes) Ethernet ports routed between the switch and Zone 3 Features of the switch include:

Layer 2 switching capable of running 26 GbE ports at full bit rate

Layer 2 features implemented: jumbo frames, port mirroring, quality-of-serviceand traffic shaping

Automatic configuration to a user definable default state at power-up;these includenon-volatileVirtual Local Area Network (VLAN) table settings with the ability to modify in the field. The configuration and management of the switch is done via the processor local bus. In theno-CPUconfiguration, theon-chip8051 microprocessor controls configuration and management of the switch.

IEEE 802.1Q and port-basedVLANs, IEEE 802.1D spanning tree protocol, and IEEE 802.3AD link aggregation control protocol

See Fig. 4-2 for a block diagram of the switch. For more information, reference theHawX-

G26 – 26-Port10/100/1000 Managed Layer 2 Ethernet Switch, VSC7376 Data Sheet.

Note: Proprietary information on the Vitesse switch is not available in this user’s manual. Please refer to the Vitesse web site for documentation, http://www.vitesse.com.

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