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Setup: Troubleshooting

Cooling requirements are a function of operating software, AMC power consumption and AMC airflow resistance. The KAT4000 thermal performance must be verified in the end user’s operating environment. Contact Emerson Technical Support at 1-800-327-1251for more information.

TROUBLESHOOTING

For instructions on how to properly install and configure the KAT4000 in a system, see the

KAT4000 Quick Start Guide, #10008585-xx, or the KAT4000 Quick Start Guide for theNo-CPUCarrier Board, #10008506-xx. If difficulty persists after referencing the Quick Start Guide, use this checklist:

Be sure all modules are seated firmly: the AMC modules on the KAT4000, the RTM on the KAT4000 (if used), and the KAT4000 in the card cage.

Verify the jumper settings (see Table 2-3).

Be sure the system is not overheating.

Check the cables and connectors to be certain they are secure.

Check your power supply for proper DC voltages.

Check that your terminal is connected to a console port.

Technical Support

If you need help resolving a problem with your KAT4000, visit http://www.artesyncp.com/support/index.html#postsales on the Internet or send e-mailto support@artesyncp.com. Please have the following information available:

KAT4000 serial number

monitor revision level

product identification from the sticker on the KAT4000 board

version and part number of the operating system (if applicable)

whether your board has been customized for options such as a higher processor speed or additional memory

license agreements (if applicable)

If you do not have Internet access, please call Emerson for further assistance:

(800) 327-1251or (608)826-8006(US)

44-131-475-7070(UK)

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Setup: Troubleshooting

Product Repair

If you plan to return the board to Emerson Network Power for service, visit http://www.artesyncp.com/support on the internet or send e-mailto serviceinfo@artesyncp.com to obtain a Return Merchandise Authorization (RMA) number. We will ask you to list which items you are returning and the board serial number, plus your purchase order number and billing information if your KAT4000 hardware is out of warranty. Contact our Test Services Department for any warranty questions. If you return the board, be sure to enclose it in an antistatic bag, such as the one in which it was originally shipped. Send it prepaid to:

Emerson Network Power, Embedded Computing

Test Services Department

8310 Excelsior Drive

Madison, WI 53717

RMA #____________

Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA number.

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Section 3

Central Processing Unit

This chapter is an overview of the processor logic (optional) on the KAT4000. It includes information on the CPU, exception handling, and the I/O parallel port pin assignments. The KAT4000 uses a Freescale MPC8548 PowerQUICC III™ microprocessor. For more detailed information, refer to the MPC8548E PowerQUICC III™ Integrated Host Processor Family Reference Manual. Refer toFig. 3-1 for a block diagram of the MPC8548. The MPC8548 is divided into two main system blocks as outlined in the following table:

Table 3-1: MPC8548 Features

Category:

MPC8548 Key Features:

Microprocessor Core

 

 

 

Embedded e500 Core

Full 32-bitBook E architecture, integer data types of 8, 16, and 32 bits,

 

32-bitfloating-pointdata type, capable of issuing and completing two

 

instructions per clock cycle, 7 pipeline stages, Auxiliary Processing

 

Units (APUs), page address translation, core registers, memory

 

management unit

 

 

L1 Cache

32-kilobytedata and32-kilobyteinstruction cache,32-byteline,

 

eight-wayset associative, parity protection

 

 

L2 Cache

512 kilobytes, eight-wayset associative

 

 

CPU Core Speed

1 GHz or 1.3 GHz, with a 400 MHz or 533 MHz DDR2 bus, respectively

 

 

Peripheral Modules

 

 

 

Ethernet

Four 10/100/1000 enhanced three-speedcontrollers (eTSEC), full-

 

/half-duplexsupport, forhigh-speedinterconnect, a set of multiplexed

 

pins support two high-speedinterface standards: 1x/4x serial RapidIO

 

(with message unit) and up to x4 PCI Express

 

 

Local Bus Controller (LBC)

DDR2 SDRAM memory controller, General Purpose Chip Select

 

Machine (GPCM), and three User-ProgrammableMachines (UPM)

 

 

High-SpeedSerial

PCIe, sRIO

Interfaces

 

 

 

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Central Processing Unit:

Figure 3-1: MPC8548 Block Diagram

Serial

DUART

XOR

 

 

 

Engine

 

 

 

 

 

 

 

 

I2C

I2C Controller

Security

512 KB

 

 

 

 

Engine

 

 

 

 

 

L2 Cache/

e500 Core

I2C

I2C Controller

 

SRAM

 

 

 

IRQs

Interrupt Controller (PIC)

e500

 

32 KB L1

32 KB L1

Coherency

 

Instruction

Data

 

 

 

DDR2 SDRAM

 

Module

 

Cache

Cache

DDR2 Controller

 

Core Complex

 

 

 

 

 

 

 

 

 

 

Bus

 

 

Flash GPIO

Local Bus Controller

 

 

 

 

 

 

OCeaN

Serial RapidIO or

4x RapidIO

MII, GMII,

eTSEC

Switch

PCI Express Controller

8x PCI Express

Fabric

 

 

 

TBI, RTBI,

 

 

 

10/100/1 Gb

 

 

 

PCI-X

RGMII, RMII

 

64-bitPCI-XController

 

 

133 MHz

MII, GMII,

eTSEC

 

TBI, RTBI,

 

 

 

 

10/100/1 Gb

 

 

 

 

RGMII, RMII

 

4-ChannelDMA Controller

 

MII, GMII,

eTSEC

 

 

TBI, RTBI,

 

 

 

 

RGMII, RMII

10/100/1 Gb

 

 

 

 

RTBI, RGMII,

eTSEC

 

 

 

 

RMII

10/100/1 Gb

 

 

 

 

 

 

 

 

 

 

The MPC8548 PowerQUICC III version follows the PowerQUICC II communications processor. Some new MPC8548 features used on the KAT4000 include:

e500 core 32-bitimplementation of the Book E architecture

Serial Management Channel (SMC) UART functionality implemented in SCC

Four integrated 10/100/1000 Ethernet controllers

Double Data Rate Two (DDR2) SDRAM memory controller

4-portOn-ChipNetwork (OCeaN) full crossbar switch fabric

Enhanced debug features

For more detailed information, reference the Freescale application note Migrating from

PowerQUICC II to PowerQUICC III.

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Central Processing Unit:MPC8548 Functions

MPC8548 FUNCTIONS

The MPC8548 provides the following functions on the KAT4000 module.

Dual UART devices

Two I2C controllers

Programmable interrupt controller

DDR2 SDRAM memory controller

General-purposeI/O (GPIO)

Chip select generation for the local bus devices

DMA capability

PCI-Xbus interface

sRIO or PCIe controller

Four three-speedEthernet controllers

MICROPROCESSOR CORE (E500)

L1 Cache

The MPC8548 processor implements two separate 32-kilobyte,level-one(L1) instruction and data caches that areeight-way,set-associative.The L1 supports afour-statemodified/exclusive/shared/invalid (MESI) cache coherency protocol. The caches also employpseudo-leastrecently used (PLRU) replacement algorithms within each way.

L2 Cache

The internal 512 kilobyte L2 cache is an eight-wayset associative instruction and data cache. The L2 cache is fully pipelined to provide 32 bytes per clock to the L1 caches. The L2 Control (L2CTL) register configures and operates the L2 SRAM array. The L2CTL is read/write and contents are cleared duringpower-onreset.

The L2 cache is cleared following a power-onor hard reset. Before enabling the L2 cache, configuration parameters must be set in the L2CR and the L2 tags must be globally invalidated. Initialize the L2 cache during systemstart-upper the following sequence:

1Power-onreset is automatically performed by the assertion of HRESET* signal.

2Verify that L2CR[L2E] = 0.

3Perform an L2 global invalidate by setting L2CR[L21].

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Central Processing Unit: Microprocessor Core (e500)

4Poll L2CR[L2I] until it is cleared.

5Enable the L2 cache for normal operation and then set the L2CR[L2E].

Timer/Counter

Each of the four 32-bitwide timer/counters can be selected to operate as a timer or a counter. Each timer/counter increments with every TCLK rising edge. In counter mode, the counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the timer counts down, issues an interrupt on terminal count, reloads itself to the programmed value, and continues to count. Reads from the counter or timer are completed directly from the counter, and writes are to the timer/counter register.

PCI Device and Vendor ID Assignment

The KAT4000 has been assigned the following PCI identification number:

Table 3-2: PCI Device and Vendor ID

Vendor ID:

Device ID:

Description:

0x1223

0x001B

Reported by the PCI bridge

 

 

 

The KAT4000 sets the PCI revision ID to the hardware version number located in the CPLD’s

Hardware Version register (Register Map 7-2).

L2 Control Register (L2CR)

Register 3-1: L2 Control Register (L2CR)

0

1

2

3

4

5

6

 

8

9

10

11

12

13

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L2E

L2I

 

L2SIZ

 

 

reserved

 

 

L2

L2I0

R

L2IN

 

L2SRAM

 

 

 

 

 

 

 

 

 

 

 

DO

 

 

TDIS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

17

18

19

20

21

22

23

24

 

 

27

28

29

30

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

L2

 

L2

R

L2LF

L2LFRID

 

reserved

 

L2STA

R

L2STASH

 

 

LO

 

SLC

 

R

 

 

 

 

 

 

SHDIS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L2E: L2Enable—enablesL2 cache ormemory-mappedSRAM (L2 array).

0L2 array disabled

1L2 array enabled

L2I: L2 Flash Invalidate

0L2 status and LRU bits are not being cleared

1Clears all L2 status bits and LRU

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Central Processing Unit: Microprocessor Core (e500)

L2SIZ: L2 SRAMSize—indicatesthe total available L2 SRAM size(read-only).00 Reserved

01 256 kilobyte

10512 kilobyte

111024 kilobyte

L2DO: L2Data-Onlymode (reserved in fullmemory-mappedSRAM mode)

0L2 cache allocates entries for instruction fetches that miss in the L2

1L2 cache allocates entries for processor data loads that miss in the L2

L2IO: L2 InstructionOnly—causesL2 cache to allocate lines for instruction cache transactions only (reserved in fullmemory-mappedSRAM mode).

0L2 cache entries allocated for data loads that miss in the L2 and for processor L1 castouts

1L2 cache allocates entries for instruction fetch misses

L2INTDIS: L2 read Intervention Disable (reserved for fullmemory-mappedSRAM mode)

0Cache intervention enabled

1Cache intervention disabled

L2SRAM: L2cache/memory-mappedSRAM block assignmentL2SIZ = L2BLKSIZ (1 block):

000 Block 0 = cache

001 Block 0 = SRAM0

010-111Reserved

L2SIZ = L2BLKSIZx2 (2 blocks):

 

Block 0

Block 1

000

Not used

Cache

001

SRAM0

Not used

010

SRAM0

Cache

011

SRAM0

SRAM1

100-111Reserved

L2LO: L2 cache LockOverflow—stickybit sets when an overlook condition is detected in L2 cache (reserved in fullmemory-mappedSRAM mode).

0Lock overflow not detected (clear L2LO in software)

1Lock overflow condition detected

L2SLC: L2 Snoop LockClear—stickybit sets when a snoop invalidated a locked data cache line (reserved in fullmemory-mappedSRAM mode).

0Snoop did not invalidate (clear L2LO in software)

1Snoop invalidated a locked line

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Central Processing Unit: Microprocessor Core (e500)

L2LFR: L2 cache Lock bits FlashReset—L2cache must be enabled for reset to occur (reserved in fullmemory-mappedSRAM mode).

0L2 cache lock bits are not cleared or the clear operation completed

1Reset operation clears each L2 cache line’s lock bits

L2LFRID: L2 cache Lock bits Flash Reset select Instruction orData—indicateswhether data, instruction, or both bits are reset.

00 Not used

01 Reset data locks if L2LFR=1

10Reset instruction locks if L2LFR=1

11Reset both data and instruction locks if L2LFR=1

L2STASHDIS: L2 Stash allocateDisable—disablesallocation of lines for stashing. 00 L2 allocates lines

01 L2 does not allocate lines

L2STASH: L2 Stashconfiguration—reservesregions of cache forstash-onlyoperation. 00 Nostash-onlyregion

01 One-halfof the array isstash-only

10One-quarterof the array isstash-only

11One-eighthof the array isstash-only

Hardware Implementation Dependent 0 Register

The Hardware Implementation Dependent 0 (HID0) register contains bits for CPU-specificfeatures. Most of these bits are cleared on initialpower-upof the KAT4000. Please refer to theMPC8548 PowerQuicc III Integrated Communications Processor Reference Manual for more detailed descriptions of the HIDx registers. The following register map summarizes HID0 for the MPC8548 processor:

Register 3-2: MPC8548 Hardware Implementation Dependent Register 0 (HID0)

32

33

 

 

39

40

41

42

43

 

47

 

 

 

 

 

 

 

 

 

 

 

EM

 

 

 

reserved

DOZ

NAP

SLP

 

reserved

 

CP

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

48

49

50

51

55

56

57

58

 

62

63

 

 

 

 

 

 

 

 

 

 

 

R

TB

STB

 

reserved

EN_

DCF

 

 

reserved

NOP

 

EN

CLK

 

 

MAS7

A

 

 

 

TI

 

 

 

 

 

 

 

 

 

 

 

EMCP: Enable Machine CheckPin—masksfurther machine check exceptions caused by assertion of

MCP*.

0MCP* is disabled

1MCP* is enabled

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Central Processing Unit: Microprocessor Core (e500)

R: Reserved should be cleared.

DOZE: Doze power management mode

0Doze mode disabled

1Doze mode enabled

NAP: Nap power management mode

0Nap mode disabled

1Nap mode enabled

SLP: Sleep power management mode enable

0Sleep mode disabled

1Sleep mode enabled

TBEN: Time Base Enable

0Time base disabled (no counting)

1Time base enabled

STBCLK: Select Time BaseClock—functionsif the time base is enabled.

0Time base is based on the processor clock

1Time base is based on the TBCLK (RTC) input

EN_MAS7: Enable MAS7update—enablesupdating MAS7 by tibre and tibsx.

0MAS7 is not updated

1MAS7 is updated

DCFA: Data Cache FlushAssist—forcesdata cache to ignore invalid sets on miss replacement selection.

0DCFA is disabled

1DCFA is enabled

NOPTI: No-opthe data and instruction cache touch instructions

0dcbt, dcbst, and icbt are enabled

1dcbt, dcbst, and icbt are treated as no-ops

Hardware Implementation Dependent 1 Register

One of the functions of the Hardware Implementation Dependent 1 (HID1) register is to display the state of the PLL_CFG[0:4] signals. The following register map summarizes HID1 for the MPC8548 CPU:

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Central Processing Unit: Interrupts and Exception Processing

Register 3-3: MPC8548 Hardware Implementation Dependent Register 1 (HID1)

32

33

34

 

 

39

40

45

46

47

 

 

 

 

 

 

 

 

 

PLL_MODE

 

 

PLL_CFG

 

reserved

 

RFXE

R

 

 

 

 

 

 

 

 

 

 

48

49

50

51

52

 

 

 

 

63

 

 

 

 

 

 

 

 

 

reserved

AST

ABE

 

 

reserved

 

 

 

 

 

ME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL_MODE: Read-onlyfor integrated devices 01 Fixed value for MPC8548

PLL_CFG: This is reflected directly from configuration input pins(read-only).PLL_CFG[0-4]corresponds to the integer divide ratio and PLL_CFG is thehalf-modebit.

00010 0 ratio of 2:1

00010 1 ratio of 5:2 (2.5:1)

00011 0 ratio of 3:1

00011 1 ratio of 7:2 (3.5:1)

R: Reserved should be cleared.

RFXE: Read Fault ExceptionEnable—controlswhether assertion ofcore_fault_in causes a machine check interrupt.

0Assertion of core_fault_in cannot cause a machine check

1A machine check can occur due to assertion of core_fault_in

ASTME: Address bus Streaming Mode Enable

0Mode disabled

1Mode enabled

ABE: Address Broadcast Enable for dcbf, dcbst, dcbi, dcbic, icbic, mbar, msync, tlbsync

0Disable address broadcasting for cache and TLB control operations

1Enable address broadcasting for cache and TLB control operations

INTERRUPTS AND EXCEPTION PROCESSING

The interrupt process begins when an exception occurs. The MPC8548 e500 core processes three types of interrupts: machine check, critical, or noncritical. Each interrupt type has separate control and status register sets as listed in the following priority:

Machine Check (highest priority):

Machine Check Save and Restore registers (MCSRR0/MCSRR1) save state when they are taken, and use rfmci instruction to restore state. The machine check enable bit, MSR[ME], can mask these interrupts.

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