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System Management:Firmware Upgrade

This command is only supported by the Boot Loader. If the IPMC firmware receives this command, it sends a reply with the 0xC1 (Invalid Command) completion code.

Table 9-49: Firmware Upgrade Restore Backup Command

Type:

Byte:

Data Field:

Request Data

1

Checksum

 

 

 

Response Data

1

Completion Code

 

 

 

Firmware Upgrade Backup Revision Command

The Firmware Upgrade Backup Revision command reads the revision of the backup firmware images stored in the master H8S flash memory. When the Boot Loader receives this command, it validates the checksums of the backup firmware images of the master and slave H8Ss. If either of the images is corrupted (the checksum is bad), the 0xCB (Requested Data Not Present) completion code is returned. Otherwise, the Boot Loader extracts the major and minor revision of the backup firmware and returns them.

This command is only supported by the Boot Loader. If the IPMC firmware receives this command, it sends a reply with the 0xC1 (Invalid Command) completion code.

Table 9-50: Firmware Upgrade Backup Revision Command

Type:

Byte:

Data Field:

Request Data

1

Checksum

 

 

 

Response Data

1

Completion Code

 

 

 

 

2:3

Major and Minor Revisions of the backup firmware

 

 

 

Firmware Upgrade Termination

The Boot Loader exits the upgrade mode upon an explicit request (the Firmware Upgrade Complete command) from the upgrade initiator. Additionally, the Boot Loader tracks the traffic coming from the firmware upgrade initiator and, if the upgrade data channel has been idle for more than a configurable amount of time, the Boot Loader closes the current upgrade session and reverts to the normal mode. This ensures that the Boot Loader does not get stuck if the upgrade initiator accidentally loses its connection to the KAT4000 or shelf, or does not communicate for another reason.

Firmware Upgrade Sequence

The normal IPMC firmware upgrade sequence is as follows (in the simple configuration).

1The IPMC firmware receives a Firmware Upgrade Start command. After parsing this command, the firmware sends a Node Busy reply and reboots to the Boot Loader. The Boot Loader enters the upgrade node.

10007175-02

KAT4000 User’s Manual

9-51

 

 

 

System Management:Firmware Upgrade

2The upgrade initiator resends the Firmware Upgrade Start command and the Boot Loader returns a success reply indicating that an upgrade session has been opened.

3The upgrade initiator issues a Firmware Upgrade Prepare (master H8S flash) command to erase the master H8S flash. The Boot Loader erases the master H8S flash and returns a success reply.

4The upgrade initiator sequentially writes the new master H8S firmware to the master H8S flash using the Flash Upgrade Write command. The Boot Loader acknowledges each write by sending a success reply to the upgrade initiator.

5The upgrade initiator issues a Firmware Upgrade Prepare (slave H8S flash) command to erase the slave H8S flash. The Boot Loader writes the cached data to the master H8S flash, erases the slave H8S flash, and returns a success reply.

6The upgrade initiator sequentially writes the new slave H8S firmware to the slave H8S flash using the Flash Upgrade Write command. The Boot Loader acknowledges each write by sending a success reply to the upgrade initiator.

7The upgrade initiator sends a Firmware Upgrade Complete command to finish the firmware upgrade. The Boot Loader writes the remaining cached data to the slave H8S flash and reboots the IPMC. After reset, the Boot Loader validates the master H8S firmware checksum and passes control to the IPMC.

9-52

KAT4000 User’s Manual

10007175-02

 

 

 

Section 10

Synchronization Clocks

The KAT4000 implements a flexible clocking circuit based on a clock selection/holdover chip with a PLD wrapper. This PLD wrapper allows local software control of the source clock selection from these input options: backplane CLK1A/B, backplane CLK2A/B, backplane CLK3A/B, AMCn TCLKA, AMCn TCLKB or AMCn FCLKA. Any of these clock sources can be sent to the following output clocks: backplane CLK3A/B, AMCn TCLKA, AMCn TCLKB or AMCn FCLKA. Transceiver buffers are used to convert all M-LVDSclocks to/from TTL levels. CLK1 and CLK2 on the backplane are inputs only. SeeFig. 10-1 for a diagram of this circuitry. See “Clock Synchronizer Registers” on page7-13for information on configuring the stratum clock buffers, selecting the primary and secondary clock sources, and selecting the output source.

Note: The pins for TCLKC and TCLKD are routed to the Zone 3 connector interface. If these signals are used on a rear transition module, there could be a conflict with an AMC module that uses these clocks.

Figure 10-1: Synchronization Clock Circuit Diagram

AMC 1

AMC 2

AMC 3

AMC 4

 

<200 MHz

100 MHz

<200 MHz

100 MHz

<200 MHz

100 MHz

<200 MHz

100 MHz

 

TCLKA TCLKB

FCLKA*

TCLKA TCLKB

FCLKA*

TCLKA TCLKB

FCLKA*

TCLKA TCLKB

FCLKA*

 

Clock

 

Clock

 

Clock

Clock

 

 

 

 

 

PCIe REFCLK

Transceiver

Transceiver

Transceiver

Transceiver

 

 

 

 

 

 

 

 

Distribution

 

 

 

 

 

 

 

 

PCIe Clock

 

 

 

PLD Wrapper

 

 

 

Source

Processor

Interface via Local Bus

Control Path

 

3

Primary

Secondary

Control Path

 

3

Primary

Secondary

Control Path

3

Clock

Selection 3

Primary

Secondary

Three Frequency

Output Paths:

19.44 MHz

1.54 MHz

2.048 MHz

Primary and Secondary

Clock Inputs

 

Clock

 

Clock

 

Clock

E-keyEnable

Transceiver

Transceiver

Transceiver

from Processor

8 KHz

8 KHz

19.44 MHz

19.44 MHz

User Clock

User Clock

 

 

CLK1

 

CLK2

 

CLK3

 

ATCA J20

* FCLKA is either a PCIe REFCLK or standard clock signal.

10007175-02

KAT4000 User’s Manual

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Synchronization Clocks:MT9045 and MT9046 Clock

All clock circuitry and the synchronization clock interface meets all hard requirements as stated in the latest PICMG3.0 and AMC.0 specifications, as well as those in all relevant AMC subspecifications.

Backplane CLK1A/B and CLK2A/B inputs are Stratum Level 4E and Stratum Level 3 or 3E sources, respectively, from the main system clock source. There are no specific Stratum level requirements for the on-boardoutput clocks that may be driven from these Stratum level input clocks.

Backplane CLK3A/B output is selectable as 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.

Backplane CLK3A/B is a derived REF clk and has no specific Stratum level quality requirements.

Backplane clock interfaces are designed to work within the specified bused M-LVDSelectrical requirements.

AMC synchronization clocks are sourced from or drive the ATCA backplane synchronization clock interface.

AMC clock interfaces are designed to work within the specified point-to-pointM-LVDSelectrical requirements.

Clocks received from and transmitted to AMC sites have no specific Stratum level quality requirements.

A configuration of this board is available with no clock interface circuitry.

MT9045 AND MT9046 CLOCK SYNCHRONIZERS

The MT9045 and MT9046 T1/E1 System Synchronizers contain a digital phase-lockedloop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The devices have reference switching and frequency holdover capabilities to help maintain connectivity during temporary synchronization interruptions. The MT9045 is compliant to Stratum 3 and Stratum 4/4E specifications. The MT9046 can be used to provide acost-reducedclock interface, compliant to only Stratum 4/4E specifications.

10-2

KAT4000 User’s Manual

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Section 11

Real-TimeClock

The standard Real-TimeClock (RTC) for the KAT4000 is provided by an M41T00 device from STMicroelectronics. This device has power sense circuitry and uses eight bytes ofnon-vola-tile RAM for the clock/calendar function. The M41T00 is powered from the +3.3 volt rail during normal operation, and uses a single, super capacitor which provides a minimum two hour backup.

BLOCK DIAGRAM

Figure 11-1: M41T00Real-TimeClock Block Diagram

OSC1

 

 

 

 

Oscillator

 

Divider

1Hz

Seconds

 

 

 

 

 

OSC0

32.768 KHz

 

 

 

 

 

 

 

 

 

 

 

FT/OUT

 

 

 

 

Minutes

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

Century/Hours

 

Voltage

 

Control

 

 

 

 

 

 

VSS

Sense and

 

 

 

 

 

Logic

 

Day

 

Switch

 

 

 

VBAT

Circuitry

 

 

 

 

 

 

 

 

 

Date

 

 

 

 

 

 

 

 

 

 

 

 

Month

 

 

 

 

 

 

 

SCL

Serial

 

 

 

 

 

Bus

 

 

 

Year

 

 

 

 

 

 

SDA

Interface

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

Register

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPERATION

The M41T00 clock operates as a slave device on the serial bus. To obtain access, the RTC implements a start condition followed by the correct slave address (D0h). Access the eight bytes in the following order:

1Seconds register

2Minutes register

3Century/Hours register

4Day register

5Date register

6Month register

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KAT4000 User’s Manual

11-1

 

 

 

Real-TimeClock:Clock Operation

7Years register

8Control register

The M41T00 clock continually monitors the supply voltage (Vcc) for an out of tolerance condition. If Vcc falls below switch-overvoltage (Vso), the M41T00:

Terminates an access in progress

Resets the device address counter

Does not recognize inputs (prevents erroneous data from being written)

At power-up,the M41T00 uses Vcc at Vso and recognizes inputs.

CLOCK OPERATION

Read the seven Clock registers one byte at a time or in a sequential block. Access the Control register (address location 7) independently. An update to the Clock registers is delayed for 250 ms to allow the read to be completed before the update occurs. This delay does not alter the actual clock time. The eight byte clock register sets the clock and reads the date and time from the clock, as summarized in Table 11-1.

Table 11-1: RTC Register Map

 

 

Address:

 

 

 

 

 

 

Data:

 

 

 

 

 

Function/Range:

 

 

 

D7

 

D6

 

D5

 

D4

 

D3

 

D2

 

D1

D0

BCD Format

 

 

00

ST

 

 

10 Seconds

 

 

 

 

Seconds

 

Seconds

00—59

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

01

X

 

 

10 Minutes

 

 

 

 

Minutes

 

Minutes

00—59

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

02

CEB

 

CB

 

10 Hours

 

 

 

Hours

 

Century/

0-1/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hours

00-23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

03

X

 

X

 

X

 

X

 

X

 

 

 

Day

 

Day

01—07

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

04

X

 

X

 

10 Date

 

 

 

 

Date

 

Date

01—31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

05

X

 

X

 

X

 

10 M

 

 

 

Month

 

Month

01—12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

06

 

 

10 Years

 

 

 

 

Years

 

Years

00—99

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

07

OUT

 

FT

 

S

 

 

 

 

Calibration

 

Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ST:

Stop bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Stops the oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

Restarts the oscillator within one second

 

 

 

 

 

 

 

 

CEB:

Century Enable Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century

 

 

0

CB will not toggle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CB:

Century Bit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11-2

KAT4000 User’s Manual

10007175-02

 

 

 

Real-TimeClock:Clock Operation

Day: Day of the week

Date: Day of the month

OUT: Output level

1 Default at initial power-up

0 FT/OUT (pin 7) driven low when FT is also zero

FT: Frequency Test bit

1When oscillator is running at 32,768 Hz, the FT/OUT pin will toggle at 512 Hz

0The FT/OUT pin is an output driver (default at initial power-up)

S:Sign bit

1Positive calibration

 

0 Negative calibration

Calibration:

Calibration bits The calibration circuit adds or subtracts counts from the oscillator divider

 

circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, neg-

 

ative calibration) or split (added, positive calibration) depends on this five-bitbyte. Adding

 

counts accelerates the clock, and subtracting counts slows the clock down.

X:

Don’t care bit

10007175-02

KAT4000 User’s Manual

11-3

 

 

 

(blank page)

11-4

KAT4000 User’s Manual

10007175-02

 

 

 

Section 12

Connectors

There are multiple connectors on the KAT4000. Reference Fig. 2-1 andFig. 2-2 for their locations. Whether individual backplane connectors are populated on the KAT4000 depends on the specific product configuration. The backplane connectors, Zones 1 through 3, are described in this chapter.

ZONE 1

Connector P10 provides the ATCA Zone 1 power (dual redundant -48VDC) and system management connections. Four levels of sequential mating provide proper functionality during live insertion or extraction.

Figure 12-1: Zone 1 Connector, P10

1

Table 12-1: Zone 1 Connector, P10 Pin Assignments

Pin:

Signal:

Insertion Sequence:

1

reserved

NA

2

reserved

NA

3

reserved

NA

4

reserved

NA

5

Hardware Address bit 0 (HA0)

third

 

 

 

6

HA1

third

 

 

 

7

HA2

third

 

 

 

8

HA3

third

 

 

 

9

HA4

third

 

 

 

10

HA5

third

 

 

 

11

HA6

third

 

 

 

12

HA7 (odd parity bit)

third

 

 

 

10007175-02

KAT4000 User’s Manual

12-1

 

 

 

Connectors:Zone 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin:

 

 

Signal:

 

Insertion Sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

IPMBA Clock (SCL port A)

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

 

 

 

 

IPMBA Data (SDA port A)

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

 

 

 

 

IPMBB Clock (SCL port B)

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16

 

 

 

 

 

IPMBB Data (SDA port B)

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

17

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

23

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

 

 

 

 

 

no connect

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

 

 

 

 

Shelf ground

 

first

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

 

 

Logic ground

 

first

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

 

 

 

 

Enable B

 

fourth

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

 

 

 

Voltage Return A (-48RTNA)

 

first

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

29

 

 

 

 

 

Voltage Return B (-48RTNB)

 

first

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

30

 

 

 

 

 

-48volt Early A

 

first

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

 

 

 

 

 

-48volt Early B

 

first

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32

 

 

 

 

 

Enable A

 

fourth

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

33

 

 

 

 

 

-48volt A(-48A)

 

second

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

 

 

 

 

 

-48volt B(-48B)

 

third

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZONE 2

Zone 2 (ZD) defines five backplane connectors, J20 through J24, which support the data transport interface. The KAT4000 is a Base node board supporting two Base channels, therefore only the J23 connector is installed to support the 10BASE-T,and/or100BASE-TX,and/or1000BASE-TEthernet. Connector J20 is also used for the optional Update Channel and synchronization clock interface. Each connector provides 40 differential signal contact pairs, with each pair carrying an individualL-shapedground contact. TheZD-styleconnector provides three levels of sequential mating, the third and shortest signal level is not used with PICMG 3.0 backplanes. The Zone 2 connector array supports four different interfaces to the ATCA backplane:

Base Node Interface (J23) supports two Base channels

Fabric Interface (J23) supports two Fabric channels (The fabric interface connection is controlled by the system E-keyingprocess)

12-2

KAT4000 User’s Manual

10007175-02