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Section 6

Memory Configuration

The KAT4000 includes the following memory devices:

Two banks of NOR Flash (32 MB total) and one bank of socketed Flash (512 KB)

Up to 1gigabyte of DDR2 Synchronous DRAM (SDRAM)

Up to 1 gigabyte of NAND Flash

Two 8-kilobytebanks ofnon-volatileserial EEPROM memory

BOOT MEMORY CONFIGURATION

The KAT4000 boot default is the 8-bitROM socket which occupies the physical address space beginning at FC80,0000. Removing the shunt on jumper JP7, pins 1:2, uses the onboard Flash as the boot device. Read bit 5 of Jumper Settings register at FC40,0018 (seeRegister Map 7-7)for the boot device selection.

Table 6-1: Memory Configuration Jumper

 

 

 

Default

Jumper:

Function:

Options:

Configuration:

JP7

Selects monitor

Jumper out, User Flash

Jumper in, ROM socket

pins 1:2

boot device

Jumper in, ROM socket

 

 

 

 

 

USER FLASH

The KAT4000 supports three independent Flash regions, one socketed and two NOR. The KAT4000 will boot from either region and is selected by jumper JP7 (1:2); socketed Flash is the default. User Flash starts at location E000,000016 with one megabyte at the base of Flash reserved for the monitor.

Two banks of NOR Flash are available, 16 MB each (see Table 14-3 for memory address details).

One bank of socketed Flash in a 32-pinPLCC includes up to 512 kilobytes.

The Flash devices interface to the most significant data bits of the PowerPC data bus. For example, if the data path is 64 bits wide, the PowerPC data bus is declared as D[0:63], where D0 is the most significant bit and D63 is the least significant bit. The interface to NOR flash memory is 16-bits,which uses bits 0 to 15 on the processor data bus.

If booting from user Flash, the processor initially maps one megabyte addressing of Flash memory (beginning at FFF0,000016) at the top of the address space. When an8-bitFlash device is installed in the PLCC socket, it always appears at FC80,000016 (and is mirrored at FFF0,000016 when the socket is the boot device).

10007175-02

KAT4000 User’s Manual

6-1

 

 

 

Memory Configuration:On-Card SDRAM

Caution:

!

When removing socketed PLCC devices, always use an extraction tool designed specifically for that task. Otherwise, you risk damaging the PLCC device.

The KAT4000 supports a redundant boot bank. This boot bank is automatically used if the primary bank fails to boot properly. The primary and redundant banks are designated from the local processor as well as remotely over IPMI. The watchdog timer on the MPC8548 will be used to change the boot select direction after a watchdog expiration event.

ON-CARDSDRAM

The KAT4000 supports 512 megabytes and 1 gigabyte of 72-bitwide DDR2 SDRAM. This interface implements eight additional bits to permit the use ofError-CorrectingCode (ECC). ECC can also be disabled for specific configurations. The SDRAM interface clock speed is 200 MHz.

A low profile, small-outline,dual inline memory module(SO-DIMM)is installed in a200-pinsocket to reduce board density and routing constraints. An I2C serial EEPROM on the SODIMM provides the serial presence detects (SPD). SDRAM occupies physical addresses from 0000,000016 to 3FFF,FFFF16.

In addition to the basic SDRAM control functions, the chip provides several additional DRAM-relatedfunctions and contains the following performance enhancing features:

Supports page mode—minimizingSDRAM cycles on multiple transactions to the same SDRAM page and can be configured to support up to 16 simultaneously opened pages

Supports Error-CorrectingCode (ECC) andRead-Modify-Write(RMW) in the case of partial writes (smaller than64-bit)to DRAM

ECC provides single bit error correction and two bit error detection

NAND FLASH

The KAT4000 uses 512 MB or 1 GB of M-systemsDiskOnChip NAND Flash, starting at physical address FC00,0000, fornon-volatileRAM storage and True Flash File System (TFFS). The DiskOnChip incorporates an embedded flash controller and memory, and features hardware protection andsecurity-enablingfeatures, an enhanced programmable boot block enabling eXecute In Place (XIP) functionality using16-bitaccess,user-controlledOne Time Programmable (OTP) partitions, and6-bitError Detection Code/Error Correction Code (EDC/ECC).

6-2

KAT4000 User’s Manual

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Table 6-3
Table 6-2

Memory Configuration:NVRAM Allocation

NVRAM ALLOCATION

The KAT4000 uses two eight-kilobyteI2C SROMs for storingnon-volatileinformation such as board, monitor, and operating system configurations, as well as information specific to a user’s application. AllEmerson-specificdata is stored in the upper two kilobits of each device. The remainder of each device is available for the user’s application. and

define the organization of data within the SROMs.

Table 6-2: NVRAM Memory Map, User EEPROM 1 (write protected)1

Address Offset (hex):

Name:

Window Size (bytes):

0x1FF0-0x1FFF

Boot verify secondary area2

16

0x1FE0-0x1FEF

Boot verify primary area2

16

0x1EE0-0x1EEF

Operating system parameters3

256

0x0000-0x1EDF

User defined

7903

 

 

 

1.EEPROM 1 is write protected to facilitate securing data.

2.The boot verify areas are for redundancy (e.g., if an application stops working, access the secondary boot data area to bring up a working application).

3.The operating system parameters area is for future VxWorks implementation.

Table 6-3: NVRAM Memory Map, User EEPROM 2

Address Offset (hex):

Name:

Window Size (bytes):

0x1FF0-0x1FFF

Emerson reserved area4

5887

0x0800-0x08FF

Miscellaneous

256

 

 

 

0x07F0-0x07FF

Power-onself test (POST)

16

 

 

 

0x0000-0x07EF

User defined

2032

 

 

 

4.The Emerson reserved area is for Emerson internal use only for test software error logging and miscellaneous data storage.

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KAT4000 User’s Manual

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(blank page)

6-4

KAT4000 User’s Manual

10007175-02

 

 

 

Section 7

CPLD

In addition to reset and interrupt registers, the complex programmable logic device (CPLD) provides the peripheral bus interface for: user LEDs, configuration jumpers, board revision, boot device selection, and the hardware configuration register. The CPLD is in-systemprogrammable (ISP). A single JTAG interface is provided for local programming. Remote programming via the IPMC is also possible.

All reset sources and loads are connected to the CPLD. The board can be remotely reset via the IPMI controller. Software can also assert a board-levelreset.

PLD REGISTER SUMMARY

The PLD registers start at address FC40,000016.Table 7-1 lists the8-bitPLD registers followed by the register bit descriptions.

Table 7-1: PLD Registers

Address

 

 

 

Offset (hex):

Mnemonic:

Register Name:

Register Map:

0x00

PIDR

Product ID

7-1

 

 

 

 

0x04

HVR

Hardware Version

7-2

 

 

 

 

0x08

PVR

PLD Version

7-3

 

 

 

 

0x0C

PLLC

PLL Configuration

7-5

 

 

 

 

0x10

HCR0

Hardware Configuration 0

7-4

 

 

 

 

0x14

Reserved

0x18

JSR

Jumper Settings

7-7

 

 

 

 

0x1C

LEDR

LED Control

7-6

 

 

 

 

0x20

RER

Reset Event

7-12

 

 

 

 

0x24

RCR1

Reset Command 1

7-13

 

 

 

 

0x28

RCR2

Reset Command 2

7-14

 

 

 

 

0x2C

SCR1

Scratch 1

7-11

 

 

 

 

0x30

BDRR

Boot Device Redirection

7-15

 

 

 

 

0x34

MISC

MISC Control

7-10

 

 

 

 

0x38

RGSR

RTM GPIO State

7-8

 

 

 

 

0x3C

RGCR

RTM GPIO Control

7-9

 

 

 

 

0x40

CSC1

Clock Synchronizer Control 1

 

 

 

 

 

0x44

CSC2

Clock Synchronizer Control 2

7-16

 

 

 

 

0x48

CSC3

Clock Synchronizer Control 3

 

 

 

 

 

0x4C

Reserved

0x50

CPS1

Clock Synchronizer Primary Source 1

 

 

 

 

 

0x54

CPS2

Clock Synchronizer Primary Source 2

7-17

 

 

 

 

0x58

CPS3

Clock Synchronizer Primary Source 3

 

 

 

 

 

0x5C

Reserved

 

 

 

 

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KAT4000 User’s Manual

7-1

 

 

 

CPLD:Version and ID Registers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Map:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Offset (hex):

 

 

Mnemonic:

Register Name:

 

(continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x60

 

 

CSS1

Clock Synchronizer Secondary Source 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x64

 

 

CSS2

Clock Synchronizer Secondary Source 2

 

7-18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x68

 

 

CSS3

Clock Synchronizer Secondary Source 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x6C

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x70

 

 

CCR1

Clock Control, AMC1 CLK1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x74

 

 

CCR2

Clock Control, AMC1 CLK2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x78

 

 

CCR3

Clock Control, AMC1 CLK3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x7C

 

 

CCR4

Clock Control, AMC2 CLK1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x80

 

 

CCR5

Clock Control, AMC2 CLK2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x84

 

 

CCR6

Clock Control, AMC2 CLK3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x88

 

 

CCR7

Clock Control, AMC3 CLK1

 

7-19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x8C

 

 

CCR8

Clock Control, AMC3 CLK2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x90

 

 

CCR9

Clock Control, AMC3 CLK3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x94

 

 

CCR10

Clock Control, AMC4 CLK1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x98

 

 

CCR11

Clock Control, AMC4 CLK2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x9C

 

 

CCR12

Clock Control, AMC4 CLK3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0xA0

 

 

CCR13

Clock Control, aTCA CLK3 A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0xA4

 

 

CCR14

Clock Control, aTCA CLK3 B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0xA8

 

 

CSI1

Clock Synchronizer Interrupt 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0xAC

 

 

CSI2

Clock Synchronizer Interrupt 2

 

7-20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0xB0

 

 

CSI3

Clock Synchronizer Interrupt 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VERSION AND ID REGISTERS

Product ID Register (PIDR)

The read-onlyProduct ID register indicates the product name and configuration. The values of these bits are defined by strapping resistors. Default register values are shown in the bottom row of the register table.

Register 7-1: Product ID Register (PIDR) at 0xfc40,0000

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

PID1

PID0

 

reserved

 

ECS

PCIE

 

 

 

 

 

 

 

 

0

0

 

 

 

 

configuration

 

 

 

 

 

 

dependent

 

 

 

 

 

 

 

 

7-2

KAT4000 User’s Manual

10007175-02

 

 

 

CPLD:Version and ID Registers

PID1, PID0: PID Select

00 KAT4000

01 Reserved

10Reserved

11Reserved

R:Reserved

ECS: Ethernet Core Switch

1 Ethernet Core Switch is installed

0 Ethernet Core Switch is not installed

PCIE: PCI Express Switch

1 PCI Express Switch is installed

0 PCI Express Switch is not installed

Hardware Version Register (HVR)

The read-onlyHardware Version register indicates artwork revision and notifies of any other change to the hardware. The values of these bits are defined by strapping resistors.

Register 7-2: Hardware Version Register (HVR) at 0xfc40,0004

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

reserved

 

 

HVR1

HVR0

 

 

 

 

 

 

 

 

R: Reserved

HVR1, HVR0: Hardware Version Register

This is hard-codedin the PLD and changes with every major PCB version. Version starts at

Ox00.

PLD Version Register (PVR)

The read-onlyPLD Version register provides ahard-codedtracking number that changes with each CPLD code release.

Register 7-3: PLD Version Register (PVR) at 0xfc40,0008

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

PCV7

PCV6

PCV5

PCV4

PCV3

PCV2

PCV1

PCV0

 

 

 

 

 

 

 

 

PCV7-0: PLD Code Version

This is hard-codedin the PLD and changes with every major code version. Version starts at

Ox00.

10007175-02

KAT4000 User’s Manual

7-3

 

 

 

CPLD:Configuration Registers

CONFIGURATION REGISTERS

Hardware Configuration Register 0 (HCR0)

The read-onlyHardware Configuration 0 register indicates various settings of the particular product configuration. The values of these bits are defined by strapping resistors. Default register values are configuration dependent.

Register 7-4: Hardware Configuration Register 0 (HCR0) at 0xfc40,0010

 

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

reserved

BDR

reserved

CF1

CF0

DDRF

 

 

 

 

 

 

 

 

 

R: Reserved

 

 

 

 

 

 

 

BDR: BDR Enable

 

 

 

 

 

 

 

1

Enable boot redirect circuitry

 

 

 

 

0

Disable boot redirect circuitry

 

 

 

 

CF1, CF0, DDRF: CCB and Core Frequencies (MHz)

Bits 2:0:

CCB:

 

Core:

000

400

 

800

 

 

 

 

001

533

 

800

 

 

 

 

010

400

 

1000

 

 

 

 

011

533

 

800

 

 

 

 

100

400

 

1200

 

 

 

 

101

533

 

1333

 

 

 

 

110

 

reserved

 

 

 

111

 

reserved

 

 

 

 

PLL Configuration Register (PLLC)

The PLL Configuration register indicates PLL settings for the MPC8548 processor. The initial values of these bits are defined by strapping resistors. The values can be overwritten by software. Default register values are configuration dependent.

Register 7-5: PLL Configuration Register (PLLC) at 0xfc40,000c

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

R

CORE2

CORE1

CORE0

SYS3

SYS2

SYS1

SYS0

 

 

 

 

 

 

 

 

 

R: Reserved

 

 

 

 

 

 

 

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CPLD:Miscellaneous Registers

CORE2-0: Core CCB PLL Ratio 000 Reserved 001 Reserved 010 Reserved 011 3:2

100Reserved

1015:2

1103:1

111Reserved

SYS3-0: System CCB PLL Ratio 0000 16:1 1100 12:1

All others are reserved

MISCELLANEOUS REGISTERS

LED Control Register (LEDR)

The KAT4000 has multiple light-emittingdiodes (LED) for status and software development (see Section “LEDs” for LED location and description). The LED Control register controls the card’s LEDs. Setting (1) the bit enables the LED. By default, the LEDs are not set. Default is 0xd0. Default register values are shown in the bottom row of the register table.

Register 7-6: LED Control Register (LEDR) at 0xfc40,001c

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

CPUR

CPUG

R

LDM

DBG3

DBG2

DBG1

DBG0

 

 

 

 

 

 

 

 

1

1

 

1

0

0

0

0

 

 

 

 

 

 

 

 

CPUR: CPU Red LED

1 On

0 Off

CPUG: CPU Green LED

1 On

0 Off

R:Reserved

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CPLD:Miscellaneous Registers

LDM: LED Debug Mode

Setting (0) puts the four debug LEDs into user mode allowing software to turn them off/on individually. By default, they are in hardware debug mode and are connected to specific internal/external signals.

1 Debug mode probes are enabled (default)

0 Debug mode probes are disabled

DBG3-0: Debug LEDs

1 On

0 Off

Jumper Settings Register (JSR)

The read-onlyJumper Settings register indicates miscellaneous external settings. Default register values are configuration dependent.

Register 7-7: Jumper Settings Register (JSR) at 0xfc40,0018

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

PRB

IROM

BFS

R

TID3

TID2

TID1

TID0

 

 

 

 

 

 

 

 

PRB: Logic Probe Input State

IROM: Ignore SROM

1 SROM ignored

0 SROM not ignored

BFS: Boot From Socket

1 Boot from socketed flash (default)

0 Boot from NOR flash

R:Reserved

TID3-0: Transition Module ID

RTM GPIO State Register (RGSR)

The read-onlyRTM GPIO State register reads the state of the GPIO lines to/from the RTM.

Default register values are configuration dependent.

Register 7-8: RTM GPIO State Register (RGSR) at 0xfc40,0038

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

RIO7

RIO6

RIO5

RIO4

RIO3

RIO2

RIO1

RIO0

 

 

 

 

 

 

 

 

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