Emerson 752I User Manual

User’s Manual from Emerson Network Power Embedded Computing

™

Katana®752i: Intelligent CompactPCI Blade for cPSB

April 2008

The information in this manual has been checked and is believed to be accurate and reliable. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER, EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are subject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Emerson patents or the rights of others.

Emerson. Consider It Solved is a trademark, and Business-Critical Continuity, Emerson Network Power, and the Emerson Network Power logo are trademarks and service marks of Emerson Network Power, Embedded Computing, Inc. © 2008 Emerson Network Power, Embedded Computing, Inc.

Revision Level: Principal Changes: Date:

10006024-00 Original release February 2006 10006024-01 Updates to page 10-4 March 2006 10006024-02 ECR01059: Added MTBF and RoHS cable info January 2007 10006024-03 Updated block diagram and FRU info July 2007 10006024-04 Updated format, Emerson contact and

regulatory info, and monitor section; changed 750GX to 750GL

April 2008

Regulatory Agency Warnings & Notices

The Emerson Katana752i meets the requirements set forth by the Federal Communications Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information is provided as required by this agency.

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

FCC RULES AND REGULATIONS — PART 15

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.

Caution: Making changes or modifications to the Katana752i hardware without the explicit consent

of Emerson Network Power could invalidate the user’s authority to operate this equipment.

EMC COMPLIANCE

The electromagnetic compatibility (EMC) tests used a Katana752i model that includes a front panel assembly from Emerson Network Power.

Caution: For applications where the Katana752i is provided without a front panel, or where the front

panel has been removed, your system chassis/enclosure must provide the required electromagnetic interference (EMI) shielding to maintain EMC compliance.

10006024-04 Katana®752i User’s Manual

(continued)

EC Declaration of Conformity

According to EN 45014:1998

Manufacturer’s Name: Emerson Network Power

Embedded Computing

Manufacturer’s Address: 8310 Excelsior Drive

Madison, Wisconsin 53717

Declares that the following product, in accordance with the requirements of 2004/108/EEC, EMC Directive and 1999/5/EC, RTTE Directive and their amending directives,

Product: Real-Time Processing Blade

Model Name/Number: Katana752i/10006008-xx

has been designed and manufactured to the following specifications:

EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and methods of measurement

EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods of measurement

EN300386 V.1.3.2:2003-05 Electromagnetic compatibility and radio spectrum matters (ERM); Telecommunication network equipment; EMC requirements

As manufacturer we hereby declare that the product named above has been designed to comply with the relevant sections of the above referenced specifications. This product complies with the essential health and safety requirements of the EMC Directive and RTTE Directive. We have an internal production control system that ensures compliance between the manufactured products and the technical documentation.

Issue date: April 21, 2008

Bill Fleury Compliance Engineer

Katana®752i User’s Manual 10006024-04

1Overview

Components and Features . . . . . . . . . . . 1-1

Functional Overview . . . . . . . . . . . . . . . . 1-4

Additional Information . . . . . . . . . . . . . . 1-5

Product Certification . . . . . . . . . . . . .1-5

RoHS Compliance. . . . . . . . . . . . . . . .1-6

Terminology and Notation. . . . . . . .1-6

Technical References. . . . . . . . . . . . .1-6

2Setup

Electrostatic Discharge . . . . . . . . . . . . . . 2-1

Katana®752i Circuit Board. . . . . . . . . . . 2-1

Identification Numbers. . . . . . . . . . . 2-7

Connectors . . . . . . . . . . . . . . . . . . . . .2-7

Fuses. . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8

Katana®752i Setup . . . . . . . . . . . . . . . . . 2-9

Power Requirements. . . . . . . . . . . .2-10

Environmental Requirements . . . .2-10

Troubleshooting. . . . . . . . . . . . . . . . . . . 2-10

Technical Support . . . . . . . . . . . . . .2-11

Product Repair . . . . . . . . . . . . . . . . .2-11

3 Reset Logic

General Overview . . . . . . . . . . . . . . . . . . . 3-1

Reset Sources . . . . . . . . . . . . . . . . . . . . . . 3-3

CompactPCI Reset Enable . . . . . . . . 3-3

Power Monitor . . . . . . . . . . . . . . . . . . 3-3

750GL Processor Reset . . . . . . . . . . . 3-3

Exception Processing. . . . . . . . . . . . . . . . .4-9

Cache Memory . . . . . . . . . . . . . . . . . . . . 4-11

L1 Cache . . . . . . . . . . . . . . . . . . . . . . 4-11

L2 Cache . . . . . . . . . . . . . . . . . . . . . . 4-11

JTAG/COP Headers. . . . . . . . . . . . . . . . . 4-13

5System Controller

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

CPU Interface . . . . . . . . . . . . . . . . . . . . . . .5-2

SDRAM Controller . . . . . . . . . . . . . . . . . . .5-3

Device Controller Interface. . . . . . . . . . . .5-3

Internal (IDMA) Controller . . . . . . . . . . . .5-4

Timer/Counters . . . . . . . . . . . . . . . . . . . . .5-4

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . .5-4

PCI Configuration Space. . . . . . . . . . 5-4

PCI Identification . . . . . . . . . . . . . . . . 5-5

PCI Read/Write. . . . . . . . . . . . . . . . . . 5-5

PCI Interface Registers . . . . . . . . . . . 5-5

Doorbell Registers . . . . . . . . . . . . . . . . . . .5-6

Outbound Doorbells . . . . . . . . . . . . . 5-6

Inbound Doorbells. . . . . . . . . . . . . . . 5-6

Watchdog Timer . . . . . . . . . . . . . . . . . . . .5-6

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6

On-Card Memory . . . . . . . . . . . . . . . . . . . .5-7

User Flash . . . . . . . . . . . . . . . . . . . . . . 5-7

SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . 5-7

EEPROMs. . . . . . . . . . . . . . . . . . . . . . . 5-8

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . .5-8

GPIO Signal Definitions . . . . . . . . . . . . . 5-10

Console Serial Port . . . . . . . . . . . . . . . . . 5-11

4Processor

Processor Overview . . . . . . . . . . . . . . . . . 4-1

Features . . . . . . . . . . . . . . . . . . . . . . . .4-1

Physical Memory Map . . . . . . . . . . . . 4-2

Processor Reset. . . . . . . . . . . . . . . . . . . . . 4-4

Processor Initialization. . . . . . . . . . . . . . . 4-4

Hardware Implementation Dependent

0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Hardware Implementation Dependent

1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Hardware Implementation Dependent

2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Exception Handling . . . . . . . . . . . . . . . . . 4-8

10006024-04 Katana®752i User’s Manual

6 Device Bus PLD

Reset Registers . . . . . . . . . . . . . . . . . . . . . .6-1

Interrupt Registers. . . . . . . . . . . . . . . . . . .6-2

Product Identification . . . . . . . . . . . . . . . .6-3

PCI Enumeration. . . . . . . . . . . . . . . . . . . . .6-3

Revision Registers . . . . . . . . . . . . . . . . . . .6-4

Board Configuration Registers. . . . . . . . .6-4

Other Registers. . . . . . . . . . . . . . . . . . . . . .6-6

7 Real-Time Clock

Block Diagram. . . . . . . . . . . . . . . . . . . . . . .7-1

Operation . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

Clock Operation . . . . . . . . . . . . . . . . . . . . .7-2

iii

8Local PCI Bus

PCI Enumeration. . . . . . . . . . . . . . . . . . . . .8-1

PCI ID Select and Interrupts . . . . . . . . . . .8-1

Geographical Addressing . . . . . . . . . . . . .8-2

PCI Bus Control Signals . . . . . . . . . . . . . . .8-2

9 PTMC Interface

PTMC Installation . . . . . . . . . . . . . . . . . . . .9-1

PTMC Connector Pinouts . . . . . . . . . . . . .9-3

10Ethernet Interfaces

Ethernet Address . . . . . . . . . . . . . . . . . . 10-1

Ethernet Ports . . . . . . . . . . . . . . . . . . . . . 10-2

Front Panel Ethernet Connector Pinouts . . .

10-2

Optional RMII PHY Devices. . . . . . . . . . 10-3

11IPMI Controller

SMB/IPMI Overview . . . . . . . . . . . . . . . . 11-1

I/O Interface . . . . . . . . . . . . . . . . . . . . . . 11-4

I2C Interfaces . . . . . . . . . . . . . . . . . . . . . 11-5

IPMI Message Protocol . . . . . . . . . . . . . 11-6

IPMI Network Function Codes . . . .11-8

IPMI Completion Codes . . . . . . . . .11-9

Zircon PM IPMI Commands . . . . .11-10

Get Sensor Reading (Sensor/Event) . . .

11-11

Master Write-Read I2C (Application) . .

11-14

Write Setting (OEM) . . . . . . . . . . .11-15

Read Setting (OEM) . . . . . . . . . . . .11-16

Set Heartbeat (OEM) . . . . . . . . . . .11-17

Get Heartbeat (OEM). . . . . . . . . . .11-18

IPMI FRU Information . . . . . . . . . .11-19

IPMI Device SDR Repository . . . . .11-20

IPMI Event Messages . . . . . . . . . . .11-20

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12Hot Swap

Hot Swap Logic (HSL) PLD. . . . . . . . . . . 12-1

cPCI Functionality. . . . . . . . . . . . . . . . . . 12-2

Hot Swap LED and Ejector Switch Control . .

12-2

cPCI Hot Swap. . . . . . . . . . . . . . . . . .12-2

Non-cPCI Hot Swap . . . . . . . . . . . . . 12-4

Timing Considerations . . . . . . . . . . . . . 12-5

HEALTHY* Signal . . . . . . . . . . . . . . . . . . 12-6

13CT Bus Interface

PICMG 2.15 Configuration 2 . . . . . . . . 13-1

Katana®752i CT Bus Options. . . . . . . . 13-2

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

Signal Control . . . . . . . . . . . . . . . . . . . . . 13-3

CT Bus Routing Without the T8110 (option

1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

CT Bus Routing With the T8110 Installed

(option 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

Local CT Bus Operation. . . . . . . . . . 13-7

H.110 CT Bus Operation. . . . . . . . . 13-8

14Backplane Signals

Overview . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

15Monitor

Command-Line Features. . . . . . . . . . . . 15-1

Basic Operation . . . . . . . . . . . . . . . . . . . 15-3

Power-Up/Reset Sequence . . . . . . 15-3

Power-Up Timing. . . . . . . . . . . . . . . 15-5

POST Diagnostic Results . . . . . . . . 15-6

Monitor SDRAM Usage. . . . . . . . . . 15-6

Monitor Recovery and Updates . . . . . . 15-7

Recovering the Monitor . . . . . . . . . 15-7

Updating the Monitor via TFTP . . . 15-7 Resetting Environment Variables . 15-8

Monitor Command Reference . . . . . . . 15-8

Command Syntax . . . . . . . . . . . . . . 15-8

Command Help . . . . . . . . . . . . . . . . 15-9

Typographic Conventions . . . . . . . 15-9

Boot Commands . . . . . . . . . . . . . . . . . . 15-9

bootbus. . . . . . . . . . . . . . . . . . . . . . . 15-9

bootcrc . . . . . . . . . . . . . . . . . . . . . . 15-10

bootd . . . . . . . . . . . . . . . . . . . . . . . .15-10

bootelf. . . . . . . . . . . . . . . . . . . . . . .15-10

bootm . . . . . . . . . . . . . . . . . . . . . . .15-10

bootp . . . . . . . . . . . . . . . . . . . . . . . .15-10

bootv . . . . . . . . . . . . . . . . . . . . . . . .15-11

bootvx . . . . . . . . . . . . . . . . . . . . . . . 15-11

rarpboot . . . . . . . . . . . . . . . . . . . . . 15-11

tftpboot. . . . . . . . . . . . . . . . . . . . . . 15-11

Katana®752i User’s Manual 10006024-04

Contents (continued)

JFFS2 File Systems. . . . . . . . . . . . . . . . . 15-12

ls . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-12

fsinfo. . . . . . . . . . . . . . . . . . . . . . . . .15-12

fsload . . . . . . . . . . . . . . . . . . . . . . . .15-12

chpart. . . . . . . . . . . . . . . . . . . . . . . .15-12

Memory Commands . . . . . . . . . . . . . . 15-12

cmp. . . . . . . . . . . . . . . . . . . . . . . . . .15-13

cp . . . . . . . . . . . . . . . . . . . . . . . . . . .15-13

find . . . . . . . . . . . . . . . . . . . . . . . . . .15-13

md. . . . . . . . . . . . . . . . . . . . . . . . . . .15-13

mm . . . . . . . . . . . . . . . . . . . . . . . . . .15-14

nm. . . . . . . . . . . . . . . . . . . . . . . . . . .15-14

mw . . . . . . . . . . . . . . . . . . . . . . . . . .15-14

Flash Commands . . . . . . . . . . . . . . . . . 15-15

cp . . . . . . . . . . . . . . . . . . . . . . . . . . .15-15

erase. . . . . . . . . . . . . . . . . . . . . . . . .15-15

flinfo . . . . . . . . . . . . . . . . . . . . . . . . .15-15

protect . . . . . . . . . . . . . . . . . . . . . . .15-16

EEPROM / I2C Commands. . . . . . . . . . 15-16

eeprom . . . . . . . . . . . . . . . . . . . . . .15-16

icrc32 . . . . . . . . . . . . . . . . . . . . . . . .15-17

iloop . . . . . . . . . . . . . . . . . . . . . . . . .15-17

imd . . . . . . . . . . . . . . . . . . . . . . . . . .15-17

ipmifirmload . . . . . . . . . . . . . . . . . .15-17

imm . . . . . . . . . . . . . . . . . . . . . . . . .15-17

imw. . . . . . . . . . . . . . . . . . . . . . . . . .15-17

inm . . . . . . . . . . . . . . . . . . . . . . . . . .15-17

iprobe. . . . . . . . . . . . . . . . . . . . . . . .15-18

Ethernet Controller EEPROM Commands . .

15-18

initeth4rom. . . . . . . . . . . . . . . . . . .15-18

filleth4rom . . . . . . . . . . . . . . . . . . .15-18

showeth4rom . . . . . . . . . . . . . . . . .15-18

Environment Parameter Commands 15-18

envinit . . . . . . . . . . . . . . . . . . . . . . .15-19

printenv . . . . . . . . . . . . . . . . . . . . . .15-19

saveenv . . . . . . . . . . . . . . . . . . . . . .15-19

setenv. . . . . . . . . . . . . . . . . . . . . . . .15-19

Test Commands . . . . . . . . . . . . . . . . . . 15-20

diags . . . . . . . . . . . . . . . . . . . . . . . . .15-20

mtest . . . . . . . . . . . . . . . . . . . . . . . .15-20

um. . . . . . . . . . . . . . . . . . . . . . . . . . .15-20

Other Commands. . . . . . . . . . . . . . . . . 15-20

autoscr . . . . . . . . . . . . . . . . . . . . . . .15-20

base . . . . . . . . . . . . . . . . . . . . . . . . .15-20

bdinfo . . . . . . . . . . . . . . . . . . . . . . .15-20

coninfo . . . . . . . . . . . . . . . . . . . . . . 15-21

crc16 . . . . . . . . . . . . . . . . . . . . . . . . 15-21

crc32 . . . . . . . . . . . . . . . . . . . . . . . . 15-21

echo . . . . . . . . . . . . . . . . . . . . . . . . . 15-21

enumpci . . . . . . . . . . . . . . . . . . . . .15-21

fpledoff . . . . . . . . . . . . . . . . . . . . . . 15-21

fruget. . . . . . . . . . . . . . . . . . . . . . . .15-21

frugetuser . . . . . . . . . . . . . . . . . . . . 15-21

frusetuser . . . . . . . . . . . . . . . . . . . . 15-22

gethvr . . . . . . . . . . . . . . . . . . . . . . .15-22

getmonver . . . . . . . . . . . . . . . . . . . 15-22

getpcimemsize . . . . . . . . . . . . . . . 15-22

getpcimode . . . . . . . . . . . . . . . . . . 15-23

getphysloc . . . . . . . . . . . . . . . . . . .15-23

getspr . . . . . . . . . . . . . . . . . . . . . . . 15-23

go . . . . . . . . . . . . . . . . . . . . . . . . . . .15-23

help . . . . . . . . . . . . . . . . . . . . . . . . .15-23

iminfo . . . . . . . . . . . . . . . . . . . . . . . 15-23

isdram . . . . . . . . . . . . . . . . . . . . . . .15-24

loop . . . . . . . . . . . . . . . . . . . . . . . . . 15-24

memmap . . . . . . . . . . . . . . . . . . . . 15-24

moninit . . . . . . . . . . . . . . . . . . . . . . 15-24

pci. . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24

reset. . . . . . . . . . . . . . . . . . . . . . . . . 15-25

run . . . . . . . . . . . . . . . . . . . . . . . . . .15-25

setpcimemsize. . . . . . . . . . . . . . . . 15-25

setpcimode. . . . . . . . . . . . . . . . . . . 15-25

setspr . . . . . . . . . . . . . . . . . . . . . . . .15-26

script . . . . . . . . . . . . . . . . . . . . . . . . 15-26

showmac. . . . . . . . . . . . . . . . . . . . .15-26

showpci . . . . . . . . . . . . . . . . . . . . . . 15-26

showtemp. . . . . . . . . . . . . . . . . . . . 15-26

sleep. . . . . . . . . . . . . . . . . . . . . . . . . 15-26

vdhcp. . . . . . . . . . . . . . . . . . . . . . . . 15-26

version. . . . . . . . . . . . . . . . . . . . . . . 15-27

Environment Variables . . . . . . . . . . . . 15-27

Troubleshooting. . . . . . . . . . . . . . . . . . 15-30

Download Formats. . . . . . . . . . . . . . . . 15-30

Binary. . . . . . . . . . . . . . . . . . . . . . . .15-30

Motorola S-Record . . . . . . . . . . . . 15-30

16Acronyms

10006024-04 Katana®752i User’s Manual

(blank page)

Katana®752i User’s Manual 10006024-04

Figures

Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Figure 2-1: Katana®752i Front Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Figure 2-2: Component Map, Top (Rev. 03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-3: Component Map, Bottom (Rev. 03). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-4: Jumper, Fuse, and Switch Locations, Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Figure 2-5: Fuse, and LED Locations, Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Figure 3-1: Katana®752i Reset Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Figure 3-2: 750GL Reset Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Figure 4-1: 750GL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Figure 4-2: 750GL Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 5-1: MV64460 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

Figure 5-2: I2C Interface Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Figure 5-3: Standard Console Cable Wiring, #10007665-00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Figure 7-1: M41T00 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

Figure 9-1: PTMC Module Location on Baseboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

Figure 10-1: RMII PHY to Transition Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

Figure 11-1: IPMB Connections Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

Figure 12-1: Hot Swap Controller Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4

Figure 13-1: Typical System Clocking Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

Figure 13-2: CT Signal Routing Diagram —T8110 Not Installed (option 1) . . . . . . . . . . . . . . . . . . . 13-5

Figure 13-3: CT Signal Routing Diagram —T8110 Installed (option 2) . . . . . . . . . . . . . . . . . . . . . . . 13-8

Figure 14-1: cPCI Connector Pin Assignments, J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

Figure 15-1: Example Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

Figure 15-2: Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

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Katana®752i User’s Manual 10006024-04

Tables

Table 1-1: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Table 1-2: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Table 2-2: LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 4-1: Katana®752i CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Table 4-2: Katana®752i Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 4-3: CPU Internal Register Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Table 4-4: 750GL Exception Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Table 4-5: Floating Point Exception Mode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

Table 4-6: 750GL JTAG/COP Interface Pin Assignments, (P3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Table 5-1: PCI Identification Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Table 5-2: NVRAM Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Table 5-3: GPIO Signals Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Table 5-4: Serial Console Port Pin Assignments, (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Table 7-1: RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Table 8-1: ID Select Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Table 8-2: Interrupt Connections for Katana®752i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Table 8-3: Geographical Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

Table 9-1: J1x PTMC Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

Table 9-2: J2x PTMC Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

Table 10-1: GbE Port LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

Table 10-2: 82544EI Ethernet Port Pin Assignments, ETH4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Table 10-3: MV64460 Ethernet Port Pin Assignments, ETH3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Table 10-4: PTMC PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

Table 11-1: Zircon PM General Purpose I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

Table 11-2: Zircon PM Analog-to-Digital Input Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

Table 11-3: IPMB Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

Table 11-4: Format for IPMI Request Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6

Table 11-5: Format for IPMI Response Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

Table 11-6: Network Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

Table 11-7: Completion Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9

Table 11-8: Zircon PM IPMI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10

Table 11-9: Get Sensor Reading Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

Table 11-10: Master Write-Read I2C Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14

Table 11-11: Write Setting Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15

Table 11-12: Read Setting Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16

Table 11-13: Set Heartbeat Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17

Table 11-14: Get Heartbeat Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18

Table 11-15: FRU Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19

Table 11-16: IPMI Event Messages Generating Sensors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20

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Tables (continued)

Table 11-17: Event Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20

Table 11-18: System Firmware Progress OEM Event Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21

Table 12-1: HSL PLD Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

Table 13-1: CT Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

Table 13-2: Local CT Bus Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

Table 14-1: cPCI Connector Pin Assignments, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

Table 14-2: cPCI Connector Pin Assignments, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

Table 14-3: cPSB Connector Pin Assignments, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

Table 14-4: cPSB Connector Pin Assignments, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

Table 15-1: Power-Up Timing for Booting from Soldered Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

Table 15-2: Power-Up Timing for Booting from Socketed Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

Table 15-3: POST Diagnostics Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

Table 15-4: Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27

Table 15-5: Optional Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29

Katana®752i User’s Manual 10006024-04

Registers

Register 4-4: CPU Machine State (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Register 4-5: L2 Cache Control Register (L2CR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Register 6-1: Reset Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Register 6-2: Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Register 6-3: Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Register 6-4: Interrupt Pending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Register 6-5: Product ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Register 6-6: EReady. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Register 6-7: Hardware Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Register 6-8: PLD Version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Register 6-9: Board Configuration 3.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Register 6-10: Board Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Register 6-11: Board Configuration 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Register 6-12: IPMI Port Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Register 6-13: Programmable LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Register 10-1: MAC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

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Katana®752i User’s Manual 10006024-04

Overview

Section 1

The Emerson Katana®752i is an intelligent input/output (I/O) processing blade for use in a CompactPCI backplane. It is compatible with the CompactPCI Packet-Switched Backplane (cPSB) and has two PCI Telecom Mezzanine Card (PTMC) sites that can support two telecommunications interface cards, such as the Emerson PM/3Gv. The Katana®752i draws processing power from its IBM PowerPC to 1GHz. A Marvell system controller serves as a PCI bridge. In the standard configuration, the Katana®752i connects two Gigabit Ethernet ports to the front panel and two Gigabit Ethernet ports to the J3 backplane connector, which (depending upon the configuration) provides access to a rear transition module or cPSB. The Katana®752i supports various memory configurations, user Flash memory, a front-panel serial port, and user I/O from the PTMC sites. Optionally, the Katana®752i supports the H.110 Computer Telephony (CT) bus and various clocking signals.

COMPONENTS AND FEATURES

The following is a brief summary of the Katana®752i hardware components and features:

750GL microprocessor, running at a speed of up

CPU: The Katana®752i features an IBM 750GL central processing unit (CPU), operating at a rate

of up to 1GHz. The CPU is a 32-bit PowerPC RISC microprocessor with 32-kilobyte, Level-1, data and instruction caches, as well as a one-megabyte, four-way, set-associative, Level-2 cache.

System Controller/PCI Bridge:

The Katana®752i employs a system controller/PCI bridge device from Marvell. The Discov-

™

ery bus interface, double-data rate (DDR) SDRAM controller, two 66-MHz PCI interfaces (64 bits for CompactPCI, 32 bits for PTMC sites), three 10/100/1000BaseT Ethernet MAC controllers, two multi-protocol serial controllers (MPSC), an interrupt controller, and 32 general-purpose input/output (I/O) signals. The MV64460 also includes an inter-integrated circuit (I

III MV64460 is a single-chip solution that provides a high-speed (up to 200MHz) 60x

C) interface.

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Overview: Components and Features

SDRAM: The Katana®752i allows for a 72-bit Small-Outline Dual In-Line Memory Module (SO-

DIMM) of up to two gigabytes to support the CPU. (Please contact Emerson for the availability of one- and two-gigabyte SO-DIMMs.) This SDRAM operates at a speed of up to 200 MHz and has Error Checking and Correction (ECC) code.

Flash: The Katana®752i supports up to 128 megabytes soldered user Flash memory for the CPU.

The Flash bank is 32 bits wide, using two or four 16-bit wide devices. The Katana®752i also supports 512 kilobytes of socketed Flash. The Flash memory conforms to the Intel StrataFlash

H.110: The Katana®752i has an optional configuration that supports the H.110 Computer Tele-

phony (CT) bus in accordance with the PICMG 2.5 Computer Telephony Specification and ECTF H.110 Specification, and it complies with Configuration 2 of the PICMG 2.15 PCI Telecom Mezzanine/Carrier Card Specification. The optional Agere Systems T8110 Time Slot Interchanger (TSI) serves as a bridge between the H.110 and local CT bus.

Ethernet Ports: The Katana®752i provides four, 10/100/1000BaseT, Gigabit Media-Independent Interface

(GMII) Ethernet ports (three from the MV64460 system controller, one from the 82544EI Ethernet controller). Two ports route to the front panel RJ45 connectors, and two ports route to the J3 CompactPCI (cPCI) connector for use either by a rear transition module or a cPCI packet-switched backplane (cPSB). Four PHY devices (three Broadcom BCM5461S, one Intel 82544EI) provide the physical interface for these ports. Optionally, the Katana®752i can support two Reduced Media-Independent (RMII) 10/100BaseT Ethernet ports routed from the PTMC sites to connector J5. Two Micrel KS8721CL PHYs support these ports.

™

architecture. The CPU is capable of booting from either Flash memory.

Serial I/O: The MV64460 system controllers provides an asynchronous console serial port, which sup-

ports EIA-232 signal levels. This serial port is accessible via a mini-DB9 connector on the Katana®752i front panel and the backplane connector J5.

CT Bus Clocks: Optionally, the Katana®752i can provide computer telephony (CT) bus clocking. One

option supports only the CT clocks (C8A, C8B, FRAMEA, FRAMEB, NETREF1, and NETFER2) between J4 and the PTMC sites. A second option supports CT bus clocking plus CT data traffic via an Agere Systems T8110 Time Slot Interchanger (TSI). This routes H.110 to the backplane connector J4.

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Katana®752i User’s Manual 10006024-04

Overview: Components and Features

PTMC Sites: The Katana®752i has two standard PCI Telecom Mezzanine Card (PTMC) slots, which allow

for the use of two compatible PTMC boards, such as the Emerson PM/3Gv telecommunications interface card. (Refer to the PM/3Gv User’s Manual for details on the PM/3Gv.) The Katana®752i complies with Configuration 2 of the PCI Telecom Mezzanine/Carrier Card Spec- ification, PICMG 2.15.

IPMI: The Katana®752i supports an Intelligent Platform Management Interface (IPMI) by using a

Zircon PM controller device from QLogic Corporation.

Rear Transition Module:

An optional TmPIM rear transition module (RTM) can host two PCI Mezzanine Card Input/Output Modules (PIMs). This RTM routes input/output signals from the Katana®752i PMC slots to the PIM slots. It can also route two Ethernet ports and an EIA-232 serial port from the J3 backplane connector to its rear panel. The Katana®752i also supports the TM/cSpan-P16 and TM/cSpan-P8E RTMs from Emerson. See the appropriate RTM user manuals more information.

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Overview: Functional Overview

J1 J2

J3 cPSB & I/O

Marvell

D-III

System

Controller

32/64/128

MB Flash

256/512MB

1GB/2GB

DDR SDRAM

512KB

Socketed

Flash

PMC Site #1

32 bit/33/66MHz PCI

64 User I/O

CT Bus per PT2MC

PMC Site #2

32 bit/33/66MHz PCI

64 User I/O

CT Bus per PT2MC

Opt J4 H.110 J5 I/O

RS232

μDB-9

RJ45

1000BaseT

CT Bus Clocks

User I/O

NVRAM

IPMI

CTRL

FRU ROM

Voltage

Monitors

Temp

Sensors

Power Supply

& Monitoring

Switch

BCM

5461S

MAG

RTC

BCM

5461S

MAG

IBM

750GX

BCM

5461S

MAG

RJ45

1000BaseT

MAG

GbE

MAC/PHY

GMII

Clock

Buffer

Opt. TSI

T8110

PCI

Opt.

KS8721CL

Opt.

KS8721CL

J12

J11

J13

J22

J21 J23

J24

J14

RMII

3.3V

2.5V

1.5V

PCI

RS232

1000BaseT

CT Bus

CPCI

Power

PTMC Ethernet

FUNCTIONAL OVERVIEW

The following block diagram provides a functional overview for the Katana®752i.

Figure 1-1: General System Block Diagram

1-4

Katana®752i User’s Manual 10006024-04

Overview: Additional Information

ADDITIONAL INFORMATION

This section lists the Katana®752i hardware’s regulatory certifications and briefly discusses the terminology and notation conventions used in this manual. It also lists general technical references.

Mean time between failures (MTBF) has been calculated at 500,674 hours using Telcordia SR-232, Issue 1, Reliability Prediction for Electronic Equipment at 40

Product Certification

The Katana®752i hardware has been tested to comply with various safety, immunity, and emissions requirements as specified by the Federal Communications Commission (FCC), Underwriters Laboratories (UL), and others. The following table summarizes this compliance.

Table 1-1: Regulatory Agency Compliance

Type: Specification:

Safety IEC60950/EN60950 – Safety of Information Technology

Equipment (Western Europe)

UL60950, CSA C22.2 No. 60950, Third Edition – Safety of Information Technology Equipment, including Electrical Business Equipment (BI-National)

Global IEC – CB Scheme Report IEC 60950, all country deviations

Environmental NEBS: Telecordia GR-63 –

Section 4.1.1 Transportation and Storage Environmental

Criteria;

Section 4.3 Equipment Handling Criteria; Section 4.4.1 Earthquake Environment and Criteria; Section 4.4.3 Office Vibration Environment and Criteria; Section 4.4.4 Transportation Vibration Criteria Section 4.5 Airborne Contaminants

EMC FCC Part 15, Class A – Title 47, Code of Federal Regulations,

Radio Frequency Devices

ICES 003, Class A – Radiated and Conducted Emissions, Canada

NEBS: Telecordia GR-1089 level 3 – Emissions and Immunity (circuit pack level testing only)

ETSI EN300386 – Electromagnetic Compatibility and Radio Spectrum Matters (ERM), Telecommunication Network Equipment, Electromagnetic Compatibility (EMC) Requirements

°C.

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Overview: Additional Information

Emerson maintains test reports that provide specific information regarding the methods and equipment used in compliance testing. Unshielded external I/O cables, loose screws, or a poorly grounded chassis may adversely affect the Katana®752i hardware’s ability to comply with any of the stated specifications.

The UL web site at ul.com has a list of Emerson’s UL certifications. To find the list, search in the online certifications directory using Emerson’s UL file number, E190079. There is a list for products distributed in the United States, as well as a list for products shipped to Canada. To find the Katana®752i, search in the list for 10006008-xx, where xx changes with each revision of the printed circuit board.

RoHS Compliance

The Katana®752i is compliant with the European Union’s RoHS (Restriction of Use of Hazardous Substances) directive, created to limit harm to the environment and human health by restricting the use of harmful substances in electrical and electronic equipment. Effective July 1, 2006, RoHS restricts the use of six substances: cadmium (Cd), mercury (Hg), hexavalent chromium (Cr (VI)), polybrominated biphenyls (PBBs), polybrominated diphenyl ethers (PBDEs), and lead (Pb). Configurations that are RoHS compliant are built with lead-free solder. Configurations that are 5-of-6 are built with tin-lead solder per the lead-insolder RoHS exemption.

To obtain a certificate of conformity (CoC) for the Katana®752i, send an e-mail to sales@artesyncp.com or call 1-800-356-9602. Please have the part number(s) (e.g., C000####-##) for your configuration(s) available when contacting Emerson.

Terminology and Notation

Active low signals: An active low signal is indicated with an asterisk * after the signal name.

Byte, word: Throughout this manual byte refers to 8 bits, word refers to 16 bits, and long word refers to

32 bits, double long word refers to 64 bits.

PLD: This manual uses the acronym, PLD, as a generic term for programmable logic device (also

known as FPGA, CPLD, EPLD, etc.).

Radix 2 and 16: Hexadecimal numbers end with a subscript 16. Binary numbers are shown with a subscript

Technical References

Further information on basic operation and programming of the Katana®752i components can be found in the following documents.

1-6

Katana®752i User’s Manual 10006024-04

Overview: Additional Information

Table 1-2: Technical References

Device/Interface:Type: Document: 1

CompactPCI CompactPCI® Specification

CPU 750GL IBM PowerPC™ 750GX and 750GL RISC Microprocessor User’s

(PCI Industrial Computers Manufacturers Group, PICMG

2.0

R3.0, Oct. 1, 1999)

Hot Swap Specification

(PICMG

System Management Specification

(PICMG

PCI Telecom Mezzanine/Carrier Card Specification

(PICMG

Packet Switching Backplane Specification

(PICMG

2.1 R2.0, Jan. 17, 2001)

2.9 R1.0, Feb. 2, 2000)

2.15 R1.0, Apr. 11, 2001)

2.16 R1.0, Sept. 5, 2001)

http://www.picmg.org

Manual

(IBM Corporation, Version 1.2, March 27, 2006)

IBM PowerPC™ 750GL RISC Microprocessor Revision Level DD1.X Datasheet

(IBM Corporation, Preliminary, Version 1.2, March 13, 2006)

PowerPC™ Microprocessor Family: The Programming Environments for 32-Bit Microprocessors

(IBM Corporation, G522-0290-01)

PowerPC™ Microprocessor Family: The Bus Interface for 32-Bit Microprocessors

(IBM Corporation, G522-0291-00)

http://www.ibm.com

10006024-04 Katana®752i User’s Manual

1-7

Overview: Additional Information

Device/Interface:Type: Document: 1 (continued)

Ethernet BCM5461S BCM5461S 10/100/1000Base-T Gigabit Ethernet Transceiver

82544EI 82544EI Gigabit Ethernet Controller Datasheet and Hardware

KS8721CL KS8721CL 3.3V Single Power Supply 10/100BASE-TX/FX MII

Hot Swap Controller

IPMI/IPMB IPMI — Intelligent Platform Management Interface

IPMI Controller Zircon PM Zircon PM Technical Manual

PCI PCI Local Bus Specification

PMC IEEE Standard for a Common Mezzanine Card (CMC) Family: IEEE

LTC1643L LTC1643L/LTC1643L-1/LTC1643H PCI-Bus Hot Swap Controller

Advance Data Sheet

(Broadcom Corp., 5461S-DS04-R, April 27, 2004)

http://www.broadcom.com

Design Guide; Application Note (AP-422)

(Intel Corp., Doc. No. A44740-005, Rev. 0.80, Dec. 2003)

http://www.intel.com

Physical Layer Transceiver Data Sheet, Rev. 1.2

(Micrel, Inc., M9999-041405, April 2005)

http://www.micrel.com

IEEE Standard for Information Technology: IEEE Std 802.3, 2000 Edition

(IEEE: New York, NY)

http://www.ieee.org

Data Sheet

(Linear Technology Corp., 1998)

http://www.linear.com

Specification v1.5

(Intel Corp., Hewlett-Packard Co., NEC Corp., Dell Computer Corp., Rev. 1.1, Feb. 20, 2002)

IPMI — Intelligent Platform Management Bus Communications Protocol Specification v1.0

(Intel Corp., Hewlett-Packard Co., NEC Corp., Dell Computer Corp., Rev. 1.0, Sept. 16, 1998)

http://www.intel.com/design/servers/ipmi/spec.htm

(QLogic Corp., 36000-510-03, Rev. C, Apr. 2002)

http://www.qlogic.com

(PCI Special Interest Group, Revision 2.3, March 29, 2002)

http://www.pcisig.com

Std 1386-2001

(IEEE: New York, NY)

IEEE Standard for Physical and Environmental Layers for PCI Mezzanine Cards: IEEE Std 1386.1-2001

(IEEE: New York, NY)

http://www.ieee.org

1-8

Katana®752i User’s Manual 10006024-04

Overview: Additional Information

Device/Interface:Type: Document: 1 (continued)

H.110 T8110 Ambassador® T8110 PCI-Based H.100/H.110 Switch and Packet

Serial Interface

System Controller MV64460 MV6446x System Controller for PowerPC Processors

PTMC Module PM/3Gv

Transition Module TmPIM

1. Frequently, the most current information regarding addenda/errata for specific documents may be found on the corresponding web site.

EIA-232-F TIA/EIA-232-F: Interface Between Data Terminal Equipment and

TM/cSpan-P16 TM/cSpan-P8E

Payload Engine

(Agere Systems, April 2001 AY01-021CT1)

http://www.agere.com

H.110 Hardware Compatibility Specification: CT Bus

(ECTF, revision 1.0)

http://www.ectf.org

Data Circuit-Terminating Equipment Employing Serial Binary Data Interchange

(Electronic Industries Association, October 1997)

http://www.eia.com/

(Marvell, MV-S101286-01, Rev. A, June 19, 2003)

http://www.marvell.com

PM/3Gv User’s Manual

(Emerson Network Power, Embedded Computing #10003035-xx)

http://www.emersonembeddedcomputing.com

TmPIM User’s Manual

(Emerson Network Power, Embedded Computing #10005691-xx)

TM/cSpan-P16 User’s Manual

(Emerson Network Power, Embedded Computing #10001320-xx)

TM/cSpan-P8E User’s Manual

(Emerson Network Power, Embedded Computing #10005363-xx)

http://www.emersonembeddedcomputing.com

If you have questions, please call Emerson Technical Support at 1-800-327-1251, visit the web site at http://www.emersonembeddedcomputing.com, or send e-mail to support@artesyncp.com.

10006024-04 Katana®752i User’s Manual

1-9

(blank page)

1-10

Katana®752i User’s Manual 10006024-04

Setup

Section 2

This chapter describes the physical layout of the boards, the setup process, and how to check for proper operation once the boards have been installed. This chapter also includes troubleshooting, service, and warranty information.

ELECTROSTATIC DISCHARGE

Before you begin the setup process, please remember that electrostatic discharge (ESD) can easily damage the components on the Katana especially those with programmable parts, are susceptible to ESD, which can result in operational failure. Unless you ground yourself properly, static charges can accumulate in your body and cause ESD damage when you touch the board.

Caution: Use proper static protection and handle Katana

necessary. Always wear a wriststrap to ground your body before touching a board. Keep your body grounded while handling the board. Hold the board by its edges–do not touch any components or circuits. When the board is not in an enclosure, store it in a staticshielding bag.

To ground yourself, wear a grounding wriststrap. Simply placing the board on top of a static-shielding bag does not provide any protection–place it on a grounded dissipative mat. Do not place the board on metal or other conductive surfaces.

KATANA®752I CIRCUIT BOARD

The Katana®752i circuit board is a 6U CompactPCI card assembly. It uses a 14-layer printed circuit board with the following dimensions.

Table 2-1: Circuit Board Dimensions

Width: Depth: Height:

9.19 in. (233.35 mm) 6.30 in. (160 mm) < 0.8 in. (< 20.32 mm)

The figures on the following pages show the front panel, component maps, and jumper locations for the Katana

752i circuit board.

752i hardware. Electronic devices,

752i boards only when absolutely

10006024-04 Katana®752i User’s Manual

2-1

PMC Site #2

PMC Site #1

EIA-232 Serial Port

Reset Switch

Programmable LEDs 14, Green

Speed LED, ETH4

GbE Port, 82544EI (ETH4)

Fault LED, Red

Activity LED, ETH4

Speed LED, ETH3

Activity LED, ETH3

GbE Port, MV64460 (ETH3)

Hot Swap LED, Blue

Ethernet LED Coding

ACT SP green green 1000BASE-T green yellow 100BASE-T green off 10BASE-T flash green yellow or green activity off off no link

Note: PMC Site #1 is not available for standard 2-GB SO-DIMM configurations. However, it may be available for some custom 2-GB configurations. Please contact Artesyn for details.

Setup: Katana®752i Circuit Board

Figure 2-1: Katana®752i Front Panel

2-2

Katana®752i User’s Manual 10006024-04

Setup: Katana®752i Circuit Board

CR1

U15

C98

C62

C97

C88

C66

C71

C75

U34

C124

C123

C93

C114

C115

C94

C85

C122

C638

C113

C112

C120

C116

C119

C118

C5C4

C43

C42

C52

C50

C14

C99

C61

C58

C91

U23HC

C546

C548

C552

C553

C550

C544

C543

C540

C541

C538

C539

U23H

C32

C59

C41

C20

C49

C19

C24

C13

C110

C109

C111

C90

C101

C107

C102

C103

C100

C104

C106

C121

C688

C689

C691

C690

C692

JP1

JP2

J11

J12

J13

J14

J21

J22

J23

J24

CR7

U27

R288

R831

R2 R3 R4 R5

U5S

SW1

R10

R11

R13

R16

R7R8R9

U17

U18

U36

U52

U54

U19

U26

C86

C87

RN3

RN19 RN20 RN21 RN22 RN23

RN24

RN25

RN26 RN27 RN28 RN29

RN30

RN31 RN32 RN33

RN34 RN35

RN36 RN37 RN38 RN39

R19

R20

U35

U13

RN1

RN10

RN11

RN12

RN13

RN14

RN2

RN4 RN5

RN6

RN7

RN8

RN9

R12

R14

R15

R17

R18

R21

U14U16

R262

R284

U24

U1 U2

U32

U33

CR3

CR4

CR5

CR6

CR2

U21

U22

U20

R263

C105

C108

C11

C117

C18

C21

C23

C25

C29

C31

C36

C38

C39

C40

C44

C45

C48

C51

C53

C60

C63

C64

C65

C68

C69

C70

C73

C74

C76

C77

C82

C89

C92

C95

C96

R873

R886

C717

C722

C733

C734

U75

U76

U6U10

U11 U7

U29

JP3

R904

R911

R914

C735

C736

C72

C78

C772

C779

C800

R920

R921

R928

R929

R936

R937

C770

C775

C776

C781

C798

C803

R932

R933

R941

R919

R930

R935

C774

C777

C802

R918

R931

R934

C768

C769

C773

C778

C782

C783

C796

C797

C801

C762

C763

C764

C765

C766

C767

C784

C785

C786

C787

C788

C789

C790

C791

C792

C793

C794

C795

L26

L27

L28

U77

U78

U79

R924

R940

R923

R926

R939

R943

R942

R945

R944

R946

R950

R951

R947

C804

R952

R948

R949

R925

C805

C806

C807

C808

C809

C810

R953

J1 – cPCI ConnectorJ2 – cPCI ConnectorJ3 – cPSB ConnectorJ4 – cPCI ConnectorJ5 – cPCI Connector

J22 – PMC Site #2

J21 – PMC Site #2

J24 – PMC Site #2

J23 – PMC Site #2

J12 – PMC Site #1

J11 – PMC Site #1

J14 – PMC Site #1

J13 – PMC Site #1

Dual RJ45

Connector with

LEDs

Micro DB9

LP1

U15

SO-DIMM

DDR

SDRAM

U28

MV64460

System Controller

U29

T8110

TSI

U23

IBM 750GX

CPU

U20

82544EI

Ethernet

Controller

Socketed

Flash

Soldered

Flash

U11

Soldered

Flash

Soldered

Flash

U10

Soldered

Flash

JTAG

(750GX)

HotSwap

Device

Bus

PLD

U24 HSL PLD

JTAG

(ISP)

Figure 2-2: Component Map, Top (Rev. 03)

10006024-04 Katana®752i User’s Manual

2-3

Setup: Katana®752i Circuit Board

C171

C347

C641

C627

C626

C657

C193

C182

C400

C386

C414

C472

C439

C441

C456

C454

C420

C432

C708

C709

C710

C707

C661

C132

C127 C126

C125

C508

C587

C640

C662

C637

C639

C669

C656

C458

C150

C216

C412

C403

C422

C455

C470

C655

C660

C649

C672

C673

C666 C665

C675

C648 C647

C654

C659

C670

C528

C169

C188

C523

C174

C594

C388

C133

C592

C562

C131

C306

C424

C343

C288

C304

C361

C312

C303

C338

C331

C380

C302

C362

C370

C308

C381

C339

C372

C259

C341

C313

C333

C348

C344

C334

C309

C391

C374

C394

C392

C256

C335

C342

C360

C585

C371

C314

C332

C260

C281

C379

C287

C395

C340

C373

C286

C305

C336

C559

C301

C393

C337

C396

C228

C199

C241

C206

C527

C231

C248

C328

C289

C290

C190

C130

C263

C283

C645

C365

C194

C200

C327

C187

C202

C663

C411

C650

C224

C262

C221

C214

C233

C246

C226

C222

C244

C250

C234

C184

C355

C377

C522

C236

C243

C220

C185

C208

C227

C201

C242

C223

C270

C319

C320

C274

C275

C325

C277

C326

C317

C318

C292

C235

C225

C212

C186

C431

C273

C299

C324

C278

C269

C215

C384

C413

C357

C457

C298

C257

C276

C300

C268

C272

C430

C442

C418

C211

C402

C421

C210

C267

C459

C378

C297

C323

C322

C293

C271

C183

C463

C469

C632

C475

C440

C307

C294

C406

C295

C321

C296

C364

C363

C426

C452

C471

C399

C385

C490

C465

C351

C410

C461

C460

C526

C429

C383

C229

C382

C427

C531

C207

C608

C642

C329

C604

C437

C425

C481

C474

C417

C230

C613

C615

C614

C618

C617

C619

C407

C398

C350

C511

C451

C534

C480

C436

C168

C644

C512

C521

C453

C204

C213

C556

C195

C664

C674

C643

C646

C167

C616

C438

C477

C505

C504

C428

C409

C476

C676

C671

C572

C558

C588

C609

C180

C177

C176 C175

C179 C178

C713

C731

C719

C718

C714

C720

C730

C712

C711

C723

C715 C716

C634

C462

C356

C354

C376

C375

C464

C515

C261

C621

C500

C519

C502

C501

C448

C574

C560

C579

C625

C568

C569

C181

C567

C566

C630

C611

C564

C467

C598

C173

C578

C602

C631

C525

C584

C479

C582

C597

C554

C575

C561

C596

C629

C589

C191

C600

C601

C620

C555

C633

C366

C310

C192

C129

C128

C172

C510

C576

C449

C565

C444

C583

C577

C599

C532

C591

C533

C492

C494

C498

C491

C495

C497

C486

C484

C487

C489

C483

C485

C482

C488

C153

C155

C493

C496

C547

C549

C551

C542

C135

C134

C136

C139

C138

C141

C140

C137

C143

C142

C144

C147

C146

C149

C148

C145

C154

C152

C158

C156

C157

C151

C164

C166

C162

C160

C367

C651

C607

C368

C433

C389

C359

C557

C580

C503

C590

C349

C316

C408

C346

C161

C163

C165

C159

C265

C315

C285

C390

C405

C311

C240

C612

C610

C330

C628

C369

C434

C447

C445

C450

C435

C239

C264

C266

C249

C423

C258

C291

C509

C397

C624

C443

C570

C573

C446

C468

C282

C245

C401

C658

C218

C668 C653

C652C667

C677

C678

C478

C507

C693

C622

C623

C635

C636

C694

C695

C696

C697

C698

C699

C700

C701

C702

C703

C704

C705

C706

CR11

CR15

CR19

U69

U55

U65

U46

U49

R152

R211

R22

R24

R25

R26

R264

R28

R29

R30R31

R329

R330

R334

R34

R343

R344

R35

R36

R37

R39

R437

R452

R453

R481

R487

R488

R519

R520

R530

R531

R568

R590

R595

R596

R597

R598

R599

R600

R601

R615

R616

R617

R618

R619

R620

R621

R622

R623

R624

R625

R626

R627

R636

R647

R648

R649

R650

R651

R652

R653

R654

R655

R656

R657

R658

R659

R660

R661

R662

R663

R664

R665

R666

R671

R713

R727

R768

R770

R832

R92

R643

R133

R134

R169

R171

R212

R213

R215

R216

R230

R231

R234

R253

R265

R269

R270

R271

R272

R273

R274

R275

R276

R277

R278

R279

R298

R313

R314

R318

R319

R320

R321

R322

R323

R324

R325

R326

R327

R328

R337

R371

R372

R386

R387

R464

R465

R466

R467

R500

R501

R508

R511

R515

R518

R554

R575

R602

R734

R791

R792

R514

R41

R486

R491

R69

R799

R806

R127

R217

R218

R219

R220

R368

R392

R400

R410

R428

R490

R694

R235

R268

R408

R412

R451

R456

R743

R762

R763

R78R79

R793

R797

R798

R801

R802

R764

R781

R338

R154

R170

R182

R198

R199

R200

R201

R202

R222

R233

R236

R242

R374

R405

R473

R489

R509

R51

R510

R529

R539

R552

R553

R559

R562

R574

R634

R675

R679

R683

R686

R690

R697

R700

R702

R722

R724

R725

R744

R746

R753

R754

R757

R758

R769

R787

R800

R807

R808

R809

R810

R811

R104

R107

R108

R109

R123

R145

R147

R153

R164

R167

R173

R174

R176

R177

R178

R184

R188

R197

R205

R246

R282

R283

R290

R306

R308

R341

R354

R355

R360

R384

R391

R393

R396

R40

R402

R414

R416

R420

R424

R426

R427

R43

R435

R436

R438

R439

R441

R454

R455

R459

R460

R461

R462

R463

R47

R471

R48

R483

R485

R49

R492

R497

R498

R499

R503

R513

R567

R578

R58

R580

R581

R585

R588

R589

R60

R638

R682

R684

R693

R698

R703

R704

R705

R706

R73

R739

R741

R750

R751

R760

R761

R785

R789

R790

R794

R795

R796

R80

R81

R82

R83

R84

R85

R86

R93

U60

R105

R117

R118

R125

R155

R156

R157

R158

R159

R160

R166

R168

R175

R317

R340

R357

R359

R376

R411

R418

R425

R512

R544

R606

R607

R637

R670

R70

R709

R710

R717

R726

R737

R738

R740

R748

R752

R755

R756

R759

R782

R786

R87

R88

L11

L13

L14

L18

L19

L20

L23

L24

L25

U58

U61

U63

U66

U67

U68

R179

R180

R221

RN100

RN101

RN113 RN114

RN115RN116

RN117RN118

RN119

RN120RN121RN122RN123

RN124RN125

RN126

RN127

RN139

RN140RN141

RN142

RN143

RN144

RN145RN146RN147RN148

RN149RN150

RN154 RN163

RN164

RN165

RN166

RN168

RN171RN172RN173RN174RN175RN176RN177RN178

RN179

RN182RN185

RN186

RN187

RN188

RN198

RN199

RN201

RN202

RN225RN226RN227

RN251RN252

RN253RN254RN255RN256

RN257

RN258

RN64

RN68

RN72

RN75

RN77

RN80

RN85 RN87

RN92RN93

RN94

RN95RN96RN97RN98

RN99

RN228

RN102RN103

RN104RN105

RN106RN107RN108RN109RN110

RN111RN112

RN128RN129

RN130RN131

RN132RN133RN134RN135RN136

RN137RN138

RN51

RN52

RN53

RN54RN57

RN60

RN61RN65

RN66

RN69

RN70

RN73

RN78

RN81

RN82

RN88

RN89

RN90RN91

RN190

RN191

RN192

RN193

RN194

RN195

RN196

RN197

RN42

RN43

RN44

RN45

RN46

RN47

RN48

RN49

R549

R730

R731

R732

R733

R803

R804R805

R223

R74

U50

U70

R742

CR16

CR24

CR29

CR30

CR36

CR42

CR8

CR9

U71

U74

RN151

RN152

RN153

RN160

RN161RN162

RN205

RN206

RN207

RN208

RN209

RN210

RN40RN41RN50

RN155

RN156

RN157

RN158

RN159

RN167

RN169

RN170

RN180

RN181

RN200

RN203

RN204

RN211

RN213

RN214

RN215

RN216

RN217RN218

RN219RN220

RN221

RN222

RN223

RN224

RN55RN58

RN62

RN63

RN67

RN71

RN74

RN76

RN79

RN83

RN84

RN86

U64

U38

U40

U51

U53

R101

R119

R124

R128

R135

R136

R137

R141

R146

R150

R151

R161

R162

R189

R190

R191

R192

R193

R195

R204

R206

R207

R208

R209

R210

R214

R227

R228

R229

R23

R239

R243

R244

R245

R261

R267

R280

R285

R286

R287

R289

R291

R307

R309

R310

R311

R315

R316

R331

R332

R333

R335R336

R342

R345R346

R347

R348

R349

R350

R351

R352R353

R356

R358

R361

R362R363

R364

R367

R370

R373

R378R379

R385

R389R390

R395

R397R398

R399

R403

R404

R407

R409

R413

R417

R419

R421

R433

R434

R44

R440

R442R443

R444

R445

R447

R448

R449

R45

R450

R457R458

R46

R472

R479

R480

R493

R494

R502

R504

R505

R506

R516

R52

R526

R527

R528

R53

R545

R546

R547

R548

R55

R555R556

R56

R569

R57

R570

R576

R582R583

R586

R587

R59

R592R593

R609

R61

R610

R62

R63

R632R633

R64

R640

R641

R642

R65

R66

R67

R673

R680

R681

R691

R692

R711

R712

R714

R718

R719

R721

R728

R747

R76

R77

R784

R788

R96

R97

R98

R99

R736

R771

R773

R774

R745

R203

R50

R75

R89R90

R91

R94

R339

R394

R468

R72

R830

R834

U37

U73

R312

R644

R126

R27

R32

R33

R38

R423

R475

R478

R71

R674

R676

R677

R685

R687

R688

R699

R701

R707

R708

R715

R716

RN212

RN229

RN230 RN231 RN232 RN233 RN234

RN235 RN236

RN237 RN238 RN239 RN240

RN241 RN242 RN243 RN244

RN245 RN246 RN247 RN248 RN249 RN250

RN59

R100

R120

R121

R132

R139

R172

R183

R194

R232

R238

R248

R249

R250

R251

R252

R254

R255

R256

R257

R258

R259

R260

R292

R293

R294

R295

R296

R297

R299

R300

R301

R302

R303

R304

R305

R365

R375

R377

R380

R388

R406

R42

R422

R474

R476

R477

R538

R550

R551

R560

R561

R579

R603

R68

R695

R783

U42

U45

U57

U59

CR10

CR20

CR21

CR22

CR23

CR32

CR33

CR34

CR35

CR31

U39

U47

U72

L15

L16

L17

R735

R765

R767

R772

R776

R778

R780

R369

R591

R604

R605

R635

R669

R672

R696

R766

R775

R777

R779

U48

R142

R163

R196

R237

R247

R281

R534

R543

R608

U56

U62

C189

C196

C203

C217

C247

C251

C252C253

C254

C255

C345

C352

C353

C416

C419

C518

C520

C586

C593

C603

C605

C606

L10

L12

L21

L22

R861

R860

R879R878

R871

R862

R863

R864

R865

R877

R876

R875

R874

R845

R846

R841

R836

R844

R835

R837

R838

R840

R849

R847

R851

R853

R839

R854

R856

R859

R843

R848

R857

R850

CR45

CR44

CR46

CR43

C721

C732

R870

R884

R885

R852

R855

R858

R872

R887

R842

C724

C725

C726

C727

C728 C729

R866

R867

R868

R869

R880

R881

R882

R883

RN259

RN260

R888

R889

R890

R891

R893

R894

R895

R896

C750

C751

R106

RN183

R720

R103

R110

R122

R898

RN261

RN262

R899

C752

R900

R901

R902

R903

C753

C754

C755

C756

C757

C758

C759

C760

C761

R446

R470

R484

R908

R909

R910

R912

R913

R915

R905

R906

R907

R916

R917

C83

C499

C506

C513

C514

C516

C537

C563

C571

C581

C595

C679

C680

C681

R678

R689

R723

R729

C771

C780

C799

R897

U43 IPMI

Controller

U44 – IPMI

EEPROM

(0xA2)

U41 – IPMI

EEPROM

(0xA0)

CR17

R165

CR28

R401

R149

Figure 2-3: Component Map, Bottom (Rev. 03)

2-4

Katana®752i User’s Manual 10006024-04

Setup: Katana®752i Circuit Board

10006008-00 REV A

J3J4J5

J22

J21

J24

J23

J12

J11

J1J2

J14

J13

CR1

JP2

JP1

SW1

SW1  Reset Switch

F4  Fuse

for 5-Volt Supply to RTM, 2.5A

F3  Fuse

for 3.3-Volt Supply to RTM, 2.5A

F2  Fuse

for 12-Volt Supply to RTM, 1A

F1  Fuse

for +12-Volt Supply to RTM, 1A

JP1  Signal Enable Jumpers

(pins 109 are spares) Jumper on pins 8 & 7, cPCI enabled Jumper on pins 6 & 5, PCIXCAP enabled Jumper on pins 4 & 3, CT_EN enabled Jumper on pins 2 & 1, cPCI_RST enable

Note: To enable cPCI functionality, use a jumper on pins 8-7 and on pins 2-1.

JP2  Configuration Jumpers

Jumpers off pins 107, MV64460 is Monarch Jumper on pins 10 & 9, PPMC #2 is Monarch Jumper on pins 8 & 7, PPMC #1 is Monarch Jumper on pins 6 & 5, enable cPCI_PRST out Jumper on pins 4 & 3, disable SROM load Jumper on pins 2 & 1, boot from socket

910

Figure 2-4: Jumper, Fuse, and Switch Locations, Top

10006024-04 Katana®752i User’s Manual

2-5

Setup: Katana®752i Circuit Board

C171

C347

C641

C627

C626

C657

C193

C182

C400

C386

C414

C472

C439

C441

C456

C454

C420

C432

C708

C709

C710

C707

C661

C132

C127 C126

C125

C508

C587

C640

C662

C637

C639

C669

C656

C458

C150

C216

C412

C403

C422

C455

C470

C655

C660

C649

C672

C673

C666 C665

C675

C648 C647

C654

C659

C670

C528

C169

C188

C523

C174

C594

C388

C133

C592

C562

C131

C306

C424

C343

C288

C304

C361

C312

C303

C338

C331

C380

C302

C362

C370

C308

C381

C339

C372

C259

C341

C313

C333

C348

C344

C334

C309

C391

C374

C394

C392

C256

C335

C342

C360

C585

C371

C314

C332

C260

C281

C379

C287

C395

C340

C373

C286

C305

C336

C559

C301

C393

C337

C396

C228

C199

C241

C206

C527

C231

C248

C328

C289

C290

C190

C130

C263

C283

C645

C365

C194

C200

C327

C187

C202

C663

C411

C650

C224

C262

C221

C214

C233

C246

C226

C222

C244

C250

C234

C184

C355

C377

C522

C236

C243

C220

C185

C208

C227

C201

C242

C223

C270

C319

C320

C274

C275

C325

C277

C326

C317

C318

C292

C235

C225

C212

C186

C431

C273

C299

C324

C278

C269

C215

C384

C413

C357

C457

C298

C257

C276

C300

C268

C272

C430

C442

C418

C211

C402

C421

C210

C267

C459

C378

C297

C323

C322

C293

C271

C183

C463

C469

C632

C475

C440

C307

C294

C406

C295

C321

C296

C364

C363

C426

C452

C471

C399

C385

C490

C465

C351

C410

C461

C460

C526

C429

C383

C229

C382

C427

C531

C207

C608

C642

C329

C604

C437

C425

C481

C474

C417

C230

C613

C615

C614

C618

C617

C619

C407

C398

C350

C511

C451

C534

C480

C436

C168

C644

C512

C521

C453

C204

C213

C556

C195

C664

C674

C643

C646

C167

C616

C438

C477

C505

C504

C428

C409

C476

C676

C671

C572

C558

C588

C609

C180

C177

C176 C175

C179 C178

C713

C731

C719

C718

C714

C720

C730

C712

C711

C723

C715 C716

C634

C462

C356

C354

C376

C375

C464

C515

C261

C621

C500

C519

C502

C501

C448

C574

C560

C579

C625

C568

C569

C181

C567

C566

C630

C611

C564

C467

C598

C173

C578

C602

C631

C525

C584

C479

C582

C597

C554

C575

C561

C596

C629

C589

C191

C600

C601

C620

C555

C633

C366

C310

C192

C129

C128

C172

C510

C576

C449

C565

C444

C583

C577

C599

C532

C591

C533

C492

C494

C498

C491

C495

C497

C486

C484

C487

C489

C483

C485

C482

C488

C153

C155

C493

C496

C547

C549

C551

C542

C135

C134

C136

C139

C138

C141

C140

C137

C143

C142

C144

C147

C146

C149

C148

C145

C154

C152

C158

C156

C157

C151

C164

C166

C162

C160

C367

C651

C607

C368

C433

C389

C359

C557

C580

C503

C590

C349

C316

C408

C346

C161

C163

C165

C159

C265

C315

C285

C390

C405

C311

C240

C612

C610

C330

C628

C369

C434

C447

C445

C450

C435

C239

C264

C266

C249

C423

C258

C291

C509

C397

C624

C443

C570

C573

C446

C468

C282

C245

C401

C658

C218

C668 C653

C652C667

C677

C678

C478

C507

C693

C622

C623

C635

C636

C694

C695

C696

C697

C698

C699

C700

C701

C702

C703

C704

C705

C706

CR11

CR15

CR19

U69

U55

U65

U46

U49

R152

R211

R22

R24

R25

R26

R264

R28

R29

R30R31

R329

R330

R334

R34

R343

R344

R35

R36

R37

R39

R437

R452

R453

R481

R487

R488

R519

R520

R530

R531

R568

R590

R595

R596

R597

R598

R599

R600

R601

R615

R616

R617

R618

R619

R620

R621

R622

R623

R624

R625

R626

R627

R636

R647

R648

R649

R650

R651

R652

R653

R654

R655

R656

R657

R658

R659

R660

R661

R662

R663

R664

R665

R666

R671

R713

R727

R768

R770

R832

R92

R643

R133

R134

R169

R171

R212

R213

R215

R216

R230

R231

R234

R253

R265

R269

R270

R271

R272

R273

R274

R275

R276

R277

R278

R279

R298

R313

R314

R318

R319

R320

R321

R322

R323

R324

R325

R326

R327

R328

R337

R371

R372

R386

R387

R464

R465

R466

R467

R500

R501

R508

R511

R515

R518

R554

R575

R602

R734

R791

R792

R514

R41

R486

R491

R69

R799

R806

R127

R217

R218

R219

R220

R368

R392

R400

R410

R428

R490

R694

R235

R268

R408

R412

R451

R456

R743

R762

R763

R78R79

R793

R797

R798

R801

R802

R764

R781

R338

R154

R170

R182

R198

R199

R200

R201

R202

R222

R233

R236

R242

R374

R405

R473

R489

R509

R51

R510

R529

R539

R552

R553

R559

R562

R574

R634

R675

R679

R683

R686

R690

R697

R700

R702

R722

R724

R725

R744

R746

R753

R754

R757

R758

R769

R787

R800

R807

R808

R809

R810

R811

R104

R107

R108

R109

R123

R145

R147

R153

R164

R167

R173

R174

R176

R177

R178

R184

R188

R197

R205

R246

R282

R283

R290

R306

R308

R341

R354

R355

R360

R384

R391

R393

R396

R40

R402

R414

R416

R420

R424

R426

R427

R43

R435

R436

R438

R439

R441

R454

R455

R459

R460

R461

R462

R463

R47

R471

R48

R483

R485

R49

R492

R497

R498

R499

R503

R513

R567

R578

R58

R580

R581

R585

R588

R589

R60

R638

R682

R684

R693

R698

R703

R704

R705

R706

R73

R739

R741

R750

R751

R760

R761

R785

R789

R790

R794

R795

R796

R80

R81

R82

R83

R84

R85

R86

R93

U60

R105

R117

R118

R125

R155

R156

R157

R158

R159

R160

R166

R168

R175

R317

R340

R357

R359

R376

R411

R418

R425

R512

R544

R606

R607

R637

R670

R70

R709

R710

R717

R726

R737

R738

R740

R748

R752

R755

R756

R759

R782

R786

R87

R88

L11

L13

L14

L18

L19

L20

L23

L24

L25

U58

U61

U63

U66

U67

U68

R179

R180

R221

RN100

RN101

RN113 RN114

RN115RN116

RN117RN118

RN119

RN120RN121RN122RN123

RN124RN125

RN126

RN127

RN139

RN140RN141

RN142

RN143

RN144

RN145RN146RN147RN148

RN149RN150

RN154 RN163

RN164

RN165

RN166

RN168

RN171RN172RN173RN174RN175RN176RN177RN178

RN179

RN182RN185

RN186

RN187

RN188

RN198

RN199

RN201

RN202

RN225RN226RN227

RN251RN252

RN253RN254RN255RN256

RN257

RN258

RN64

RN68

RN72

RN75

RN77

RN80

RN85 RN87

RN92RN93

RN94

RN95RN96RN97RN98

RN99

RN228

RN102RN103

RN104RN105

RN106RN107RN108RN109RN110

RN111RN112

RN128RN129

RN130RN131

RN132RN133RN134RN135RN136

RN137RN138

RN51

RN52

RN53

RN54RN57

RN60

RN61RN65

RN66

RN69

RN70

RN73

RN78

RN81

RN82

RN88

RN89

RN90RN91

RN190

RN191

RN192

RN193

RN194

RN195

RN196

RN197

RN42

RN43

RN44

RN45

RN46

RN47

RN48

RN49

R549

R730

R731

R732

R733

R803

R804R805

R223

R74

U50

U70

R742

CR16

CR24

CR29

CR30

CR36

CR42

CR8

CR9

U71

U74

RN151

RN152

RN153

RN160

RN161RN162

RN205

RN206

RN207

RN208

RN209

RN210

RN40RN41RN50

RN155

RN156

RN157

RN158

RN159

RN167

RN169

RN170

RN180

RN181

RN200

RN203

RN204

RN211

RN213

RN214

RN215

RN216

RN217RN218

RN219RN220

RN221

RN222

RN223

RN224

RN55RN58

RN62

RN63

RN67

RN71

RN74

RN76

RN79

RN83

RN84

RN86

U64

U38

U40

U51

U53

R101

R119

R124

R128

R135

R136

R137

R141

R146

R150

R151

R161

R162

R189

R190

R191

R192

R193

R195

R204

R206

R207

R208

R209

R210

R214

R227

R228

R229

R23

R239

R243

R244

R245

R261

R267

R280

R285

R286

R287

R289

R291

R307

R309

R310

R311

R315

R316

R331

R332

R333

R335R336

R342

R345R346

R347

R348

R349

R350

R351

R352R353

R356

R358

R361

R362R363

R364

R367

R370

R373

R378R379

R385

R389R390

R395

R397R398

R399

R403

R404

R407

R409

R413

R417

R419

R421

R433

R434

R44

R440

R442R443

R444

R445

R447

R448

R449

R45

R450

R457R458

R46

R472

R479

R480

R493

R494

R502

R504

R505

R506

R516

R52

R526

R527

R528

R53

R545

R546

R547

R548

R55

R555R556

R56

R569

R57

R570

R576

R582R583

R586

R587

R59

R592R593

R609

R61

R610

R62

R63

R632R633

R64

R640

R641

R642

R65

R66

R67

R673

R680

R681

R691

R692

R711

R712

R714

R718

R719

R721

R728

R747

R76

R77

R784

R788

R96

R97

R98

R99

R736

R771

R773

R774

R745

R203

R50

R75

R89R90

R91

R94

R339

R394

R468

R72

R830

R834

U37

U73

R312

R644

R126

R27

R32

R33

R38

R423

R475

R478

R71

R674

R676

R677

R685

R687

R688

R699

R701

R707

R708

R715

R716

RN212

RN229

RN230 RN231 RN232 RN233 RN234

RN235 RN236

RN237 RN238 RN239 RN240

RN241 RN242 RN243 RN244

RN245 RN246 RN247 RN248 RN249 RN250

RN59

R100

R120

R121

R132

R139

R172

R183

R194

R232

R238

R248

R249

R250

R251

R252

R254

R255

R256

R257

R258

R259

R260

R292

R293

R294

R295

R296

R297

R299

R300

R301

R302

R303

R304

R305

R365

R375

R377

R380

R388

R406

R42

R422

R474

R476

R477

R538

R550

R551

R560

R561

R579

R603

R68

R695

R783

U42

U45

U57

U59

CR10

CR20

CR21

CR22

CR23

CR32

CR33

CR34

CR35

CR31

U39

U47

U72

L15

L16

L17

R735

R765

R767

R772

R776

R778

R780

R369

R591

R604

R605

R635

R669

R672

R696

R766

R775

R777

R779

U48

R142

R163

R196

R237

R247

R281

R534

R543

R608

U56

U62

C189

C196

C203

C217

C247

C251

C252C253

C254

C255

C345

C352

C353

C416

C419

C518

C520

C586

C593

C603

C605

C606

L10

L12

L21

L22

R861

R860

R879R878

R871

R862

R863

R864

R865

R877

R876

R875

R874

R845

R846

R841

R836

R844

R835

R837

R838

R840

R849

R847

R851

R853

R839

R854

R856

R859

R843

R848

R857

R850

CR45

CR44

CR46

CR43

C721

C732

R870

R884

R885

R852

R855

R858

R872

R887

R842

C724

C725

C726

C727

C728 C729

R866

R867

R868

R869

R880

R881

R882

R883

RN259

RN260

R888

R889

R890

R891

R893

R894

R895

R896

C750

C751

R106

RN183

R720

R103

R110

R122

R898

RN261

RN262

R899

C752

R900

R901

R902

R903

C753

C754

C755

C756

C757

C758

C759

C760

C761

R446

R470

R484

R908

R909

R910

R912

R913

R915

R905

R906

R907

R916

R917

C83

C499

C506

C513

C514

C516

C537

C563

C571

C581

C595

C679

C680

C681

R678

R689

R723

R729

C771

C780

C799

R897

CR17

R165

CR28

R401

R149

U43

U41

U44

PMC Slot 2 Ethernet LEDs

CR45 – PMC2 Act CR46 – PMC2 Link

GbE Port 2 LEDs

CR23 – Link1, CR22 – Link2 CR21 – Link, CR20 – Act

GbE Port 1 LEDs

CR35 – Link1, CR34 – Act CR33 – Link2, CR32 – Link

Ethernet LED Coding

Link1 Link2 on on 1000BASE-T on off 100BASE-T off on 10BASE-T off off no link

F7 – Fuse

for 2.5V JTAG (P3), 0.75A

F6 – Fuse

for 3.3V JTAG (P3), 0.75A

F5 – Fuse

for 3.3V JTAG (J7), 0.75A

CR31 – LED

750GX Checkstop Indicator

PMC Slot 1 Ethernet LEDs

CR43 – PMC1 Act CR44 – PMC1 Link

CR10 – LED

IPMI Status Out Indicator

2-6

Katana®752i User’s Manual 10006024-04

Figure 2-5: Fuse, and LED Locations, Bottom

Setup: Katana®752i Circuit Board

Identification Numbers

Before you install the Katana®752i circuit board in a system, you should record the following information:

❐ The board serial number:____________________________________________ .

The board serial number appears on a bar code sticker located on the back of the board.

❐ The board product identification: _____________________________________ .

This sticker is located near the board serial number.

❐ The monitor version: _______________________________________________ .

The version number of the monitor is on the monitor start-up display.

❐ The operating system version and part number: _________________________ .

This information is labeled on the master media supplied by Emerson or another vendor.

❐ Any custom or user ROM installed, including version and serial number:

________________________________________________________________ .

It is useful to have these numbers available if you need to contact Technical Support at Emerson Network Power, Embedded Computing.

Connectors

The Katana®752i circuit board has various connectors, summarized as follows:

P1: P1 is a dual-RJ45 connector that provides front panel access to two 10/100/1000BaseT

Ethernet ports (see routes to the 82544EI Ethernet controller on the local PCI bus. The connector also has integrated link, speed, and activity LEDs for each port. See Chapter for pinouts.

P2: P2 is a 9-pin Micro D connector on the front panel that provides EIA-232 console port access

for the 750GL processor. See

P3: P3 is a 16-pin header on the circuit board for the 750GL COP/JTAG interface. See

for pinouts.

J1: J1 is a 110-pin connector that routes power supply signals, various CompactPCI (cPCI) util-

ity signals and Intelligent Platform Management Interface (IPMI) control signals to and from the CompactPCI backplane. See Chapter for pinouts.

J2: J2 is a 110-pin connector that routes Geographical Address (GA) signals and power supply

signals from the CompactPCI backplane. See Chapter for pinouts.

J3: J3 is a 95-pin connector that routes the gigabit Ethernet signals to and from the Compact-

PCI packet-switched backplane (cPSB) or rear transition module. It also routes user input/output signals directly from the J14 connector at PTMC expansion site #1. See Chapter for pinouts.

Fig. 2-1). One port routes to the MV64460 system controller. The other

Table 5-4 for pinouts.

Table 4-6

10006024-04 Katana®752i User’s Manual

2-7

Setup: Katana®752i Circuit Board

J4 : J4 is a 90-pin connector that routes computer telephony (CT) bus signals to the Compact-

PCI backplane. See Chapter for pinouts.

J5: J5 is a 110-pin connector that routes user input/output signals directly from the J24 connec-

tor at PTMC expansion site #2. It also routes optional RMII signals from both PTMC sites. See Chapter for pinouts.

J6: J6 is a 3-pin header on the circuit board for the ejector switch (for factory use only).

J7: J7 is a 10-pin header on the circuit board that provides an in-system programmable (ISP)

JTAG interface to the programmable logic (PLD) devices (factory use only).

J11—J14: J11, J12, J13, and J14 are 64-pin connectors that support PTMC expansion site #1. See

Table 9-1 for pinouts.

J21—J24: J21, J22, J23, and J24 are 64-pin connectors that support PTMC expansion site #2. See

Table 9-2 for pinouts.

Fuses

There are seven fuses on the Katana®752i circuit board.

Note: The part numbers for these fuses are subject to change. Please check with Emerson before ordering replace-

ment fuses.

F1—F2: These 1-amp fuses (see Fig. 2-4) protect the ±12-volt power supplies. They are Emerson part

number 02739005-00.

F3—F4: These surface-mounted, socketed, 2.5-amp fuses (see

volt power supplies. They are Emerson part number 02959021-00.

F5—F7: These 0.75 amp fuses (see

(P3) and PLD header (J7). They are Emerson part number 02959012-00.

LEDs

The Katana®752i has various light-emitting diodes (LEDs), as described in the following table. Please refer to

Table 2-2: LEDs

LED: Color: Signal Name: Comments:

CR1 Blue HOTSWAP_LED* front panel Hot Swap status CR2 Red PWRLED_OUT front panel Fault LED CR31 750GL_CHKSTP_OUT* CPU checkstop indicator

2-8

Katana®752i User’s Manual 10006024-04

Fig. 2-4) protect the 3.3-volt and 5-

Fig. 2-5) protect the power supplies for the COP/JTAG interface

Fig. 2-1 and Fig. 2-5 to locate these LEDs.

Setup: Katana®752i Setup

LED: Color: Signal Name: Comments:

CR3 Green 750GL_LED4 programmable LED on front CR4 750GL_LED3 CR5 750GL_LED2 CR6 750GL_LED1 CR10 IPMI_STATUSOUT IPMI controller status CR32 GIG0_LINK_LED* Port 1 Gigabit Ethernet CR33 GIG0_LINK2* CR34 GIG0_ACT_LED* CR35 GIG0_LINK1* CR20 GIG1_ACT_LED* Port 2 Gigabit Ethernet CR21 GIG1_LINK_LED* CR22 GIG1_LINK2* CR23 GIG1_LINK1* CR39 PMC0_ACTLED PMC1 RMII CR41 PMC0_LINKLED_R CR38 PMC1_ACTLED PMC2 RMII CR40 PMC1_LINKLED_R – Green/Ye

llow

–FP1_LED2_1

–FP2_LED1_1

–FP2_LED2_1

FP1_LED1_1 FP1_LED1_2

FP1_LED2_2

FP2_LED1_2

FP2_LED2_2

panel (via light pipe LP1)

front panel SP LED for ETH4 (integrated with connector P1)

front panel ACT LED for ETH4 (integrated with connector P1)

front panel SP LED for ETH3 (integrated with connector P1)

front panel ACT LED for ETH3 (integrated with connector P1)

KATANA®752I SETUP

You need the following items to set up and check the operation of the Emerson

Katana

❐ Emerson Katana

❐ Card cage and power supply

❐ Serial interface cable (EIA-232)

❐ Terminal

Save the antistatic bag and box for future shipping or storage.

752i.

752i board

10006024-04 Katana®752i User’s Manual

2-9

Setup: Troubleshooting

Power Requirements

The Emerson Katana®752i circuit board typically requires about 35 watts of power when performing a simple memory test with no PMC/PTMC modules installed. The exact power requirements for the Katana the board, including the CPU frequency, amount of memory installed on the board, and PTMC configuration. Please contact Emerson Technical Support at 1-800-327-1251 if you have specific questions regarding the board’s power requirements.

Note: The power value is an approximate–not measured–value.

Environmental Requirements

The Emerson Katana®752i circuit board is specified to operate in an ambient air temperature range of 0° to +55° Centigrade. This range meets the NEBS Telecordia GR-63 specification. The entire chassis should be cooled with forced air. The recommended minimum air flow rate is 11 cubic feet/minute. The exact air flow requirement depends upon the chassis configuration and the ambient air temperature. The Katana and storage temperature ranges fully comply with NEBS Telecordia GR-63 specification.

752i circuit board depend upon the specific configuration of

752i board’s relative humidity

TROUBLESHOOTING

In case of difficulty, use this checklist:

❐ Be sure the Katana

❐ Be sure the system is not overheating.

❐ Check the cables and connectors to be certain they are secure.

❐ If you are using the Katana

results. Chapter describes the power-up diagnostics.

❐ Check your power supply for proper DC voltages. If possible, use an oscilloscope to look

for excessive power supply ripple or noise (over 50 mV

❐ Check that your terminal is connected to a console port.

The Katana configure and set the baud rates for its console port. The lack of a prompt might be caused by incorrect terminal settings, and incorrect configuration of the NVRAM, or a malfunctioning NVRAM.

To force the board to boot using the default settings, first configure the terminal parameters to: 9600 baud, no parity, 8 data bits, and 1 stop bit. Then, reset the board while holding down the ‘s’ key. After the board boots to the prompt, you can initialize the configuration settings to their factory defaults with the following command:

752i circuit board is seated firmly in the card cage.

752i monitor, run the power-up diagnostics and check the

below 10 MHz).

752i monitor uses values stored in on-card NVRAM (I2C EEPROM) to

2-10

Katana®752i User’s Manual 10006024-04

Setup: Troubleshooting

moninit <four-digit board serial number> noburn

Executing the above command will set all environment variables to default values and erase any user-added environment variables. Please see “Environment Parameter Commands” on page 15-18, for additional information.

Technical Support

If you need help resolving a problem with your Katana®752i, visit http://www.emersonembeddedcomputing.com on the Internet or send e-mail to support@artesyncp.com. Please have the following information handy:

• Katana

• baseboard model number and BIOS revision level (if applicable)

• version and part number of the operating system (if applicable)

• whether your board has been customized for options such as a higher processor speed

752i serial number and product identification from the stickers on the board

or additional memory

• license agreements (if applicable)

If you do not have Internet access, please call Emerson for further assistance:

(800) 327-1251 or (608) 826-8006 (US)

44-131-475-7070 (UK)

Product Repair

If you plan to return the board to Emerson Network Power for service, visit http://www.emersonembeddedcomputing.com on the internet or send e-mail to serviceinfo@artesyncp.com to obtain a Return Merchandise Authorization (RMA) number. We will ask you to list which items you are returning and the board serial number, plus your purchase order number and billing information if your Katana752i hardware is out of warranty. Contact our Test and Repair Services Department for any warranty questions. If you return the board, be sure to enclose it in an antistatic bag, such as the one in which it was originally shipped. Send it prepaid to:

Emerson Network Power, Embedded Computing Test and Repair Services Department 8310 Excelsior Drive Madison, WI 53717

RMA #____________

10006024-04 Katana®752i User’s Manual

2-11

Setup: Troubleshooting

Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA number.

2-12

Katana®752i User’s Manual 10006024-04

Reset Logic

Section 3

This chapter provides a system-level overview of the reset logic for the Katana®752i. It also describes the various reset sources.

GENERAL OVERVIEW

The Katana®752i uses discrete logic on a programmable logic device (PLD) to implement the reset circuitry. logic.

Fig. 3-1 on the following page shows an overview of the reset signals and

10006024-04 Katana®752i User’s Manual

3-1

Reset Logic: General Overview

F r

o n t P a n e l

P u s

h B u

to n

2 .

5 V

P M I P o w e r

O S C _ E N

E n a b le

BCM5221

KS8721CL

BCM5221

BCM5461

T8110 TSI

Soldered

Flash

R P

PMC Site 1

PMC Site 2

750GL

Complex

m c

F L

R P

ip m i_ r

B c

m 5

P c

i1 _

Notes:

1. All discrete logic located inside PLD

2. PLD powered from early power

3. Zircon PM powered from IPMI power

Oscillators

O S C _

Voltage

Monitor

Voltage

Monitor

Zircon PM

to u

LTC1728

Voltage

Monitor

P C I

_ R S T _ O U

3 .

3 V

1 .

8 V

5 V

3 .

2 .

5 V

o r

P M C

3 .

3 V

cPCI_RST

Default:

Jumper Out =

cPCI reset is disabled

82544

MAC

Figure 3-1: Katana®752i Reset Diagram

3-2

Katana®752i User’s Manual 10006024-04

Reset Logic: Reset Sources

RESET SOURCES

The Katana®752i circuit board can be reset from the following sources:

• Power-On Reset (POR) circuitry

•CompactPCI Reset

• Power Monitor Reset

• 750GL Processor Reset (JTAG header)

• Remote IPMI Reset

•Front Panel Reset

• Watchdog Timer Reset

CompactPCI Reset Enable

The Katana®752i has an optional configuration jumper at JP2 (see Fig. 2-4). When installed (default condition), this jumper enables the board to send a reset signal (when the front panel reset switch is pressed) to the cPCI system controller via the cPCI_PRST pin. Upon receiving this signal, the cPCI system controller generates a cPCI reset. When the jumper is not installed, the Katana when the reset switch is pressed.

752i does not send the reset signal to the cPCI system controller

Another optional configuration jumper at JP1 (see tion), enables the cPCI reset signal to drive a local PCI reset to the 750GL reset logic (see

Fig. 3-2). When the jumper is not installed, the Katana

Fig. 2-4), when installed (default condi-

752i ignores the cPCI reset signal.

Power Monitor

The Katana®752i has a power monitor circuit that detects low voltage conditions on any of the power supply sources. The circuit will hold the oscillators off and drive the power-on reset (POR) for as long as the low voltage condition exists.

750GL Processor Reset

The Device Bus PLD (see Chapter ) on the Katana®752i implements the 750GL processor reset logic.

Note: The Device Bus PLD is also known as the MVC PLD.

Fig. 3-2 shows how the reset signals connect to the related devices.

10006024-04 Katana®752i User’s Manual

3-3

Reset Logic: Reset Sources

Soldered

Flash

flash_wp

MV64460

sysrst

pci0_rst

pci1_rst

gt_wde

COP/JTAG

hreset

sreset

trst

Device

Bus

PLD

cop_hreset

cop_sreset

cop_trst

pmc_rst

gt_wde

gt_pci0

gt_pci1

start_lrst

cpu_hreset

cpu_sreset

cpu_trst

fl_rp

gt_sysrst

750GX

hreset

sreset

trst

start_rst (switch_rst)

PMC Sites

HSL PLD

por_rst

ipmi_rst

cpci_rst

IPMI

Power

cPCI

pwr_good

por_rst

rst

KS8721CL

PHY

reset

KS8721CL

reset

KS8721CL

PHY

reset

KS8721CL

PHY

reset

5461S

reset

ks8721_rst

eth_rst

Figure 3-2: 750GL Reset Logic

3-4

Katana®752i User’s Manual 10006024-04

Processor

Section 4

The Katana®752i processor complex consists of a processor and a system controller/PCI bridge device (see Chapter ) with associated memory and input/output interfaces. The processor complex supports soldered and socketed user Flash memory, DDR SDRAM, an EIA232 serial console port, and three 10/100/1000BaseT Ethernet ports.

PROCESSOR OVERVIEW

This chapter provides an overview of the processor logic on the Katana®752i. It includes information on the CPU, exception handling, and cache memory. The Katana the IBM PowerPC

™

750GL microprocessor. For more detailed information, please refer to the following IBM document: PowerPC Microprocessors.

Features

The following table outlines some of the key features for the 750GL CPU.

Table 4-1: Katana®752i CPU Features

Category: 750GL Key Features:

Instruction Set 32-bit CPU Speed (internal) Up to 1GHz Data Bus 64-bit Address Bus 32-bit Four stage pipeline control Fetch, dispatch/decode, execute,

Cache (L1) 32KB Instruction, 32KB Data, 8-way set

Cache (L2) 1MB, 4-way set associative, ECC checking Execution Units Branch Processing, Dispatch, Decode,

Dual issue superscalar control

Voltages Internal, 1.5V; input/output, 2.5V

™

Microprocessor Family: The Bus Interface for 32-Bit

complete/write back

associative

Load/Store, Fixed-point, Floating-point, System

Maximum of two instructions completed plus one branch folded per cycle

752i utilizes

The following block diagram provides an overview of the IBM 750GL architecture.

10006024-04 Katana®752i User’s Manual

4-1

Processor: Processor Overview

Completion

System

Unit

Dispatch BHT/BTIC

Instruction Fetch

Branch Unit

Control Unit

32KB I-Cache

with Parity

LSU

FPRs

Rename

Buffers

FPU

GPRs

Rename

Buffers

FXU2FXU1

32KB D-Cache

with Parity

L2 Tags

with Parity

1MB

L2 Cache

w/ECC

Enhanced 60x

BIU

Figure 4-1: 750GL Block Diagram

4-2

Physical Memory Map

The Katana®752i monitor (see Chapter ) initializes the devices required to configure the memory map for the 750GL bus. The following figure shows the 750GL physical memory map.

Katana®752i User’s Manual 10006024-04

Processor: Processor Overview

Device Bus PLD Registers

E800,0000

Flash Socket

F820,0000

FLASH

(up to 128MB)

F810,0000

MV64460 Registers

F800,0000

Reserved

C000,0000

E000,0000

F808,0000

Reserved

F811,0000

cPCI

Memory Space

cPCI

I/O Space

FF80,0000

Boot Mirror

FFFF,FFFF

32-Bit

Hex Address:

Reserved

SRAM

F834,0000

F830,0000

HSL PLD Registers

F821,0000

B400,0000

B000,0000

8000,0000

0000,0000

SDRAM

(up to 2GB)

PMC

PCI Memory Space

PMC

PCI I/O Space

Reserved

Figure 4-2: 750GL Memory Map

10006024-04 Katana®752i User’s Manual

4-3

Processor: Processor Reset

This table summarizes the physical addresses for the 750GL on the Katana®752i board and provides a reference to more detailed information.

Table 4-2: Katana®752i Address Summary

Hex Address (32-bit):

FF80,0000 R Boot Mirror F834,0000 F830,0000 R/W MV64460 SRAM page 5-1 F821,0000 R/W HSL PLD Registers page 4-1,

F820,0000 R/W Device Bus PLD Registers page 6-1 F811,0000 F810,0000 R/W MV64460 Registers page 5-1 F808,0000 F800,0000 R/W Flash socket page 5-7 E800,0000 R/W Flash (up to 128MB) page 5-7 E000,0000 R/W cPCI I/O Space page 5-4 C000,0000 R/W cPCI Memory Space page 5-4 B400,0000 B000,0000 R/W PMC PCI I/O Space page 5-4 8000,0000 R/W PMC PCI Memory Space page 5-4 0000,0000 R/W SO-DIMM SDRAM (up to 2GB) page 5-7

Access Mode: Description: See Page:

— Reserved –

page 13-1

— Reserved –

PROCESSOR RESET

Circuitry on the Katana®752i resets the processor and the board. Please refer to Chapter for details.

PROCESSOR INITIALIZATION

Initially, the Katana®752i powers up with specific values stored in the CPU registers. The initial power-up state of the Hardware Implementation Dependent registers (HID0) and the Machine State register (MSR) are given in

Table 4-3: CPU Internal Register Initialization

HID0 8000,0000 (icache and dcache off) Hardware Implementation Dependent

8000,C000 (icache and dcache on)

MSR 0000,B032 Machine State register.

4-4

Katana®752i User’s Manual 10006024-04

Table 4-3.

(See Section )

Processor: Processor Initialization

Hardware Implementation Dependent 0 Register

The Hardware Implementation Dependent 0 Register (HID0) contains bits for CPU-specific features. Most of these bits are cleared on initial power-up of the Katana to the IBM PowerPC documentation for more detailed descriptions of the HIDx registers. The following register map summarizes HID0 for the 750GL CPU:

0 1 2 34 67 8 9 10 11 121314 15

EMCP DBP EBA EBD Reserved PAR DOZE NAP

SLEEP

DPM RISEG

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ICE DCE

ILOCK

DLOCK

ICFI DCFI

SPD IFEM

SGE DCFA BTIC

Res

EMCP: Enable Machine Check Pin. Initially enabled on the Katana®752i.

DBP: Disable 60x Bus address and data Parity generation (in conjunction with EBA/EBD).

EBA: Enable 60x Bus Address parity checking.

EBD: Enable 60x Bus Data parity checking.

752i. Please refer

Res.

ABE BHT

MUM NHR

Res

NOOPTI

PAR: Disable Precharge of ARTRY* and shared signals.

DOZE: Select low-power doze.

NAP: Select low-power nap.

SLEEP: Select low-power sleep.

DPM: Enable Dynamic Power Management.

RISEG: Read Instruction Segment Register (test only).

NHR: Not Hard Reset (software use only).

MUM: Miss-Under-Miss Enable.

ICE/DCE: Instruction and Data Cache Enables.

I/DLOCK: Instruction and Data Cache Lock bits.

ICFI/DCFI: Instruction and Data Cache Flash Invalidate bits.

SPD: DCache and ICache Speculative access disable.

IFEM: Enable M bit on bus for Instruction Fetches.

SGE: Store Gathering Enable.

DCFA: Data Cache Flush Assist.

Force data cache to ignore invalid sets on miss replacement selection.

10006024-04 Katana®752i User’s Manual

4-5

Processor: Processor Initialization

BTIC: Branch Target Instruction Cache enable.

ABE: Address Broadcast Enable (for cache ops, eieio, sync).

BHT: Branch History Table enable.

NOOPTI: No-op the dcbt/dcbst instructions.

Hardware Implementation Dependent 1 Register

The 750GL includes two phase-lock loops (PLL0 and PLL1), which allow the processor clock frequency to be changed to one of the PLL frequencies via software control. The HID1 register contains:

• Fields that specify the frequency range of each PLL

• The clock multiplier of each PLL

• External or internal control of PLL0

• A bit to choose which PLL is selected (source of the processor clock at any given time):

0456789131415

PCE PRE PSTAT1 ECLK Reserved PI0 PS

16 20 21 22 23 24 28 29 30 31

PC0 PR0 Res. PC1 PR1 Res.

PCE: PLL External Configuration bits (read only).

PRE: PLL External Range bits (read only).

PSTAT1: PLL Status (not supported in DD1.x).

0 = PLL0 is the processor clock source 1 = PLL1 is the processor clock source

ECLK: Enable the CLKOUT pin (set to 1).

PI0: PLL 0 Internal configuration select.

0 = Select external configuration and range bits to control PLL0 1 = Select internal fields in HID1 to control PLL0

PS: PLL Select.

0 = Select PLL0 as source for processor clock 1 = Select PLL1 as source for processor clock

PC0: PLL0 Configuration bits.

4-6

Katana®752i User’s Manual 10006024-04

Processor: Processor Initialization

PR0: PLL0 Range select bits.

PC1: PLL1 Configuration bits.

PRI: PLL1 Range bits.

Hardware Implementation Dependent 2 Register

Parity is implemented for the following arrays: I-Cache, I-Tag, D-Cache, D-Tag, and L2 Tag. Status bits are set when a parity error is detected and cleared when the HID2 register is written.

0234 15

Reserved

STMUMD

Reserved

1 6

Reserved FICBP

STMUMD: Disable store miss-under-miss processing.

FICBP: Force I-Cache bad parity.

FITBP: Force I-Tag bad parity.

FDCBP: Force D-Cache bad parity.

FDTBP: Force D-Tag bad parity.

FL2TBP: Force L2-Tag bad parity.

DCPS: L1 D-Cache/D-Tag Parity Error Status/Mask.

DCPE: L1 D-Cache/D-Tag Parity checking Enable.

1 9 20 21 22 23 24 25262728293031

FITBP FDCBP FDTBP

FL2TBP

ICPS

DCPS

L2PS Res. ICPE

DCPE L2PE

ICPS: L1 I-Cache/I-Tag Parity Error Status/Mask.

L2PS: L2 Tag Parity Error Status/Mask.

ICPE: L1 I-Cache/I-Tag Parity checking Enable.

L2PE: L2 Tag Parity checking Enable.

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4-7

Processor: Exception Handling

EXCEPTION HANDLING

Each CPU exception type transfers control to a different address in the vector table. The vector table normally occupies the first 2000 bytes of RAM (with a base address of 0000,0000 may be used to point to an error routine or for code or data storage. exceptions recognized by the processor from the lowest to highest priority.

Table 4-4: 750GL Exception Priorities

Exception:

Trace 00D00 Lowest priority. Due to MSR[SE]=1 or MSR[BE]=1 for

Data Storage (DSI) 00300 DABR address match.

Alignment 00600 Any alignment exception condition. Program (PI) 00700 Due to a floating-point enabled exception.

Floating Point Unavailable (FPA) 00800 Any floating-point unavailable exception. System call (SC) 00C00 Execution of system call (sc) instruction. Instruction Address Breakpoint

(IABR) Instruction Storage (ISI) 00400 Instruction fetch exceptions. Thermal Management (TMI) 01700 Junction temperature exceeds the threshold

Decrementer (DEC) 00900 Decrementer passed through zero. Performance Monitor (PFM) 00F00 Programmer-specified. External (EI) 00500 INT* (Refer to Section for description of interrupt

System Management (SMI) 01400 MSR[EE]=1 and SMI* is asserted. Machine check 00200 Assertion of TEA*, 60x Address Parity Error, 60x Data

System reset 00100 Soft reset (SRESET*).

) or ROM (with a base address of F800,000016). An unassigned vector position

Vector Address Hex Offset: Notes:

01300 Any IABR exception condition.

Table 4-4 lists the

branches.

TLB page protection violation. Any access except cache operations to T=1 (bit 5 of

DSISR) or T=0->T=1 crossing. BAT page protection violation. Due to eciwx, ecowx with EAR(E)=0 (bit 11 of

DSIDSR).

Due to an illegal instruction, a privileged instruction, or a trap.

specified in THRM1 or THRM2, and MSR[EE]=1.

sources and interrupt handling.)

Parity Error, L2 ECC Double Bit Error, MCP*, L2-Tag Parity Error, D-Tag Parity Error, I-Tag Parity Error, ICache Parity Error, D-Cache Parity Error, or locked L2 snoop hit.

Highest priority. Hard reset (HRESET* and POR).

4-8

Katana®752i User’s Manual 10006024-04

Processor: Exception Processing

Vector Address

Exception:

– 00000 Reserved.

EXCEPTION PROCESSING

When an exception occurs, the address saved in Machine Status Save/Restore register 0 (SRR0) helps determine where instruction processing should resume when the exception handler returns control to the interrupted process. Machine Status Save/Restore register 1 (SRR1) is used to save machine status on exceptions and to restore those values when an rfi instruction is executed.

When an exception is taken, the 750GL controller uses SRR0 and SRR1 to save the contents of the Machine State register (MSR) for the current context and to identify where instruction execution resumes after the exception is handled.

Hex Offset: Notes: (continued)

The Machine State register (MSR) configures the state of the 750GL CPU. On initial powerup of the Katana

752i, most of the MSR bits are cleared. Please refer to the IBM PowerPC

documentation for more detailed descriptions of the individual bit fields.

01 12 13 14 15

Reserved POW Res. ILE

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

EE PR FP ME FE0 SE BE FE1 Res. IP IR DR Res. PM RI LE

POW: Power Management enable. Setting this bit enables the programmable power manage-

ment modes: nap, doze, or sleep. These modes are selected in the HID0 register. This bit has no effect on dynamic power management. 0= Power management disabled (normal operation mode) 1= Power management enabled (reduced power mode)

ILE: Exception Little-Endian mode.

EE: External interrupt Enable. This bit allows the processor to take an external interrupt, system

management interrupt, or decrementer interrupt. 0= External interrupts and decrementer exception conditions delayed. 1= External interrupt or decrementer exception enabled.

PR: Privilege level.

0= User- and supervisor-level instructions are executed 1= Only user-level instructions are executed

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4-9

Processor: Exception Processing

FP: Floating-Point available. This bit is set on initial power-up.

0= Prevents floating-point instructions dispatch (loads, stores, moves). 1= Executes floating-point instructions.

ME: Machine check Enable.

0= Machine check exceptions disabled. 1= Machine check exceptions enabled.

FE0/FE1: These bits define the Floating-point Exception mode.

Table 4-5: Floating Point Exception Mode Bits

FE0: FE1: FP Exception Mode:

00Disabled 0 1 Imprecise nonrecoverable 1 0 Imprecise recoverable 11Precise

SE: Single-step trace Enable.

0= Executes instructions normally. 1= Single-step trace exception generated.

4-10

BE: Branch trace Enable.

0= Executes instructions normally. 1= Branch type trace exception generated.

IP: Exception Prefix. Initially, this bit is cleared so that the exception vector table is placed at

the base of RAM (0000,0000 ROM (FFF0,0000

). When this bit is set, the vector table is placed at the base of

IR/DR: Instruction and Data address translation enables.

0= Address translation disabled. 1= Address translation enabled.

PM: Marks a process for the Performance Monitor.

0= Process is not marked. 1= Process is marked.

RI: Recoverable exception enable for system reset and machine check. This feature is enabled

on initial power-up. 0= Exception is not recoverable. 1= Exception is recoverable.

LE: Little-endian mode enable.

0= Big-endian mode (default). 1= Little-endian mode.

Katana®752i User’s Manual 10006024-04

Processor: Cache Memory

CACHE MEMORY

The 750GL processor provides both level 1 (L1) and level 2 (L2) cache memory. This section describes this memory.

L1 Cache

The 750GL processor has separate, on-chip, 32-kilobyte, Level 1 (L1) instruction and data caches with eight-way, set-associative translation lookaside buffers (TLBs). The CPU supports the modified/exclusive/invalid (MEI) cache coherency protocol. The data bus width for bus interface unit (BIU) accesses of the L1 data cache array is 256 bits. This enables cache line data burst to be read from or written to the cache array in a single cycle, reducing cache contention between the BIU and the load-store unit. The 750GL also employs pseudo-least recently used (PLRU) replacement algorithms for enhanced performance.

L2 Cache

The internal L2 cache is four-way set associative. Each way contains 4096 blocks, and each block consists of two 32-byte sectors. It can be configured with any combination of individual ways locked. It can lock half or all of the ways, or it can unlock them all. When unlocked, the L2 cache is four-way set associative. Each way contains 262144 blocks, and each block consists of two 32-byte sectors.

The L2 cache can be configured to contain instructions or data only. Array read and write operations execute in one processor cycle—writes are 64 bits wide and reads are 256 bits wide. The L2 has a 1MB SRAM which includes an 8-bit ECC for every 64-bit word in memory that can be used to correct most single bit errors and detect multiple bit errors.

The L2 cache control register (L2CR) configures and enables the L2 cache. The L2CR is read/write and contents are cleared during power-on reset.

0 1 2 8 9 1011 12 13 1415

L2E L2CE Reserved L2DO L2I Res. L2WT L2TS Reserved

Reserved

9202122232425262728293031

L0CK LO

LOCK HI

SHEE

SHERR

LOCK0

LOCK1L2LOCK2L2LOCK3

L2IO Reserved L2IP

L2E: L2 Enable.

Enables and disables the operation of the L2 cache, starting with the next transaction.

L2CE: L2 double bit error Checkstop Enable.

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4-11

Processor: Cache Memory

L2DO: L2 Data-Only.

Setting this bit inhibits the caching of instructions in the L2 cache. All accesses from the L2 instruction cache are treated as cache-inhibited by the L2 cache.

L2I: L2 global Invalidate.

Setting this bit invalidates the L2 cache globally by clearing the L2 status bits.

L2WT: L2 Write-Through.

Setting this bit selects write-through mode (rather than default copy-back mode) so all writes to the L2 cache also write through to the 60x bus.

L2TS: L2 Test Support.

Setting this bit causes cache block pushes from the L1 data cache that result from dcbf and dcbst instructions to be written only into the L2 cache and marked valid. Also causes singlebeat store operations that miss in the L2 cache to be discarded.

L2L0CKLO: L2 cache locking: lock ways 0 and 1.

L2LOCKHI: L2 cache locking: lock ways 2 and 3.

SHEE: Snoop Hit in locked line Error Enable.

SHERR: Snoop Hit in locked line Error.

L2LOCK0: Lock way 0 if either bit 20 or bit 24 is set to one.

L2LOCK1: Lock way 1 if either bit 20 or bit 25 is set to one.

L2LOCK2: Lock way 2 if either bit 21 or bit 26 is set to one.

L2LOCK3: Lock way 3 if either bit 21 or bit 27 is set to one.

L2IO: L2 Instruction-Only.

Setting this bit inhibits data caching in the L2 cache.

L2IP: L2 global Invalidate in Progress.

This read only bit indicates whether an L2 global invalidate is occurring.

The L2 cache is disabled following a power-on or hard reset. Before enabling the L2 cache, configuration parameters must be set in the L2CR and the L2 tags must be globally invalidated. Initialize the L2 cache during system start-up per the following sequence:

1 Power-on reset (automatically performed by the assertion of HRESET* signal).

2 Disable interrupts and dynamic power management (DPM).

3 Disable L2 cache by clearing L2CR[L2E].

4 Perform an L2 global invalidate.

5 Enable the L2 cache for normal operation by setting the L2CR[L2E] bit to 1.

4-12

Katana®752i User’s Manual 10006024-04

Processor: JTAG/COP Headers

JTAG/COP HEADERS

The 750GL CPU provides a dedicated user-accessible test access port (TAP) that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. The internal common-on-chip (COP) debug processor allows access to internal scan chains for debugging purposes, and can also be used as a serial connection to the core for emulator support.

Table 4-6: 750GL JTAG/COP Interface Pin Assignments, (P3)

Pin: Signal: I/O: Description:

1 TDO Output The Test Data Out is a standard JTAG signal. This is the scan

2 — — Not connected 3 TDI Input The Test Data In is a standard JTAG signal, and is the input

4 TRST* Input Test Reset is a standard JTAG signal. When this signal is active

5 — — Not connected 6 +3.3V Output This is the power supply for the 750GL which indicates to the

7 TCK Input The Test Clock is a standard JTAG signal, and is the clock for

8 — — Not connected 9 TMS Input The Test Mode Select is a standard JTAG signal. This signal,

10 — — Not connected 11 SRESET* Input The Soft Reset is required to enable the debug station to

12 GND — Ground 13 HRESET* Input The Hard Reset is required to enable the debug station to

14 Key — Pin 14 is not installed.

path output, driven by the falling edge of the TCK signal and sampled on the rising edge of TCK.

data for the scan path. TDI is driven by the JTAG controller on the falling edge of TCK, and sampled on the rising edge of TCK by the JTAG slave.

(low), the JTAG logic is reset and inactive, allowing normal operation of the 750GL.

debug station the voltage at which the target processor is powered. (For the through a resettable PTC fuse.)

the JTAG machine. JTAG signals are driven according to the TCK falling edge and sampled over its rising edge.

along with TCK, controls the TAP controller state machine allowing movement between its different states. When high, it causes a change in the TAP controller state on the rising edge of TMS. When low, the TAP controller state machine remains in its current state.

either generate a Soft Reset sequence, or observe the 750GL taking a Soft Reset sequence.

either generate a Hard Reset sequence, or observe the 750GL taking a Hard Reset sequence.

Katana®752i, this signal is tied to 2.5V

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4-13

Processor: JTAG/COP Headers

Pin: Signal: I/O: Description: (continued)

15 CHKSTPO* Output Checkstop (halted) indication (see also Checkstop LED

16 GND — Ground

indicator, CR31, in Fig. 2-5)

4-14

Katana®752i User’s Manual 10006024-04

System Controller

The Katana®752i processor complex consists of a processor (see Chapter ) and a system controller/PCI bridge device with associated memory and input/output interfaces. This chapter describes the Marvell MV64460 system controller/PCI bridge device implementation.

OVERVIEW

The Discovery™ III PowerPC® System Controller (MV64460) from Marvell is an integrated system controller with a PCI interface and communication ports for high performance control applications. The MV64460 has a five bus architecture:

• A 64-bit interface to the CPU bus

• A 64-bit interface to DDR SDRAM

• A 32-bit interface to devices

• Two PCI interfaces: The Katana

local PCI bus (PCI1) and a 32/64-bit interface for the CompactPCI bus (PCI0).

752i implementation uses a 32-bit interface for the

Section 5

The five buses function independently which enables simultaneous operation of the CPU bus, PCI device, and access to memory.

The MV64460 communications unit includes the following:

• Three Gigabit Ethernet ports

• Two multi-protocol serial controllers (MPSC)

• Ten serial DMAs (SDMA)

• Two baud rate generators (BRG)

•I

C interface

The crossbar fabric, or central routing unit, controls the data path routing. It contains programmable arbitration mechanisms to optimize device performance.

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5-1

System Controller: CPU Interface

CPU at up to 200 MHz

10/100/1000

72-bit at up to

200 MHz

SCC, TWSI

64-bit at 33/66 MHz

CPU Interface + 2 Mb SRAM

4 DMA

2 XOR

GPIO, SCC,

TWSI, Int,

Timers

PCI

DDR

PCI

Device

32-bit at

66 MHz

64-bit at 33/66 MHz

3 Ports Gb Ethernet +

FIFO Interface

Figure 5-1: MV64460 Block Diagram

CPU INTERFACE

CPU interface features include:

• 32-bit address and 64-bit data buses

• Support for Symmetrical Multi-Processing (SMP) in both 60x and MPX bus modes

• Support for up to four slave devices on the same 60x bus

• Up to 200 MHz CPU bus frequency

• CPU address remapping to PCI

• Support for access, write, and cache protection to a configurable address range

• Support for up to 16 pipelined address transactions

Note: Proprietary information on the Marvell MV64460 device is not available in this user’s manual. Please refer to

the Marvell web site at http://www.marvell.com for available documentation.

The Katana®752i monitor configures the MV64460 controller so that it provides these 32bit registers to the PowerPC processor in the correct byte order (assuming the access width is 32 bits). The CPU setting of the CPU Configuration register affects the MV64460 behavior on subsequent CPU accesses. This register activates with transactions pipeline disabled. In order to gain the maximum CPU interface performance, change this default by following these steps:

5-2

Katana®752i User’s Manual 10006024-04

System Controller: SDRAM Controller

1 Read the CPU Configuration register. This guarantees that all previous transactions in the

CPU interface pipe are flushed.

2 Program the register to its new value.

3 Read polling of the register until the new data is being read.

Caution: Setting the CPU Configuration register must be done only once. For example, if the CPU

interface is configured to support Out of Order (OOO) read completion, changing the register to not support OOO read completion is fatal.

SDRAM CONTROLLER

The MV64460 supports double data rate (DDR) synchronous dynamic random access memory (SDRAM). The SDRAM controller supports up to four banks of SDRAMs. It has a 16bit address bus (M_DA[13:0] and M_BA[1:0]) and a 72-bit data bus (M_DQ[63:0] and M_CB7[7:0]). The SDRAM controller supports both registered and unbuffered SDRAM devices. Other features include:

• 64-bit wide (+ 8-bit ECC) SDRAM interface

• Up to 200-MHz SDRAM frequency

• Support for 64-megabit to one-gigabit DDR SDRAM devices

• Supports both physical and virtual bank interleaving

The MV64460 has a number of SDRAM registers. Refer to the Marvell web site for available documentation.

DEVICE CONTROLLER INTERFACE

The device controller supports up to five banks of devices. Each bank’s supported memory space can be programmed separately in one megabyte quantities up to 512 megabytes of address space with a total device space of 2.5 gigabytes. Other features include:

• Dedicated 32-bit multiplexed address/data bus (separate from the SDRAM bus)

• 66 MHz bus frequency

• Five chip selects, each with programmable timing

• Use as a high bandwidth interface to user specific logic

• Supports many types of standard memory and I/O devices

Each bank has its own parameter register and can be programmed to 8, 16, or 32-bits wide. The device interface consists of 128 bytes of write buffer and 128 bytes of read buffer.

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5-3

System Controller: Internal (IDMA) Controller

INTERNAL (IDMA) CONTROLLER

Each of the four DMA engines can move data between any source and any destination, such as the SDRAM, device, PCI_0, or CPU bus. These engines optimize system performance by moving large amounts of data without significant CPU intervention. Read and write are handled independently and concurrently.

TIMER/COUNTERS

Each of the four 32-bit wide timer/counters can be selected to operate as a timer or a counter. Each timer/counter increments with every Tclk rising edge. In counter mode, the counter counts down to terminal count, stops, and issues an interrupt. In timer mode, the timer counts down, issues an interrupt on terminal count, reloads itself to the programmed value, and continues to count. Reads from the counter or timer are completed directly from the counter, and writes are to the timer/counter register.

PCI INTERFACE

The MV64460 supports two 64-bit PCI interfaces, which comply with the PCI Local Bus Specification revision 2.3. Other features include:

• Supports P2P memory, I/O, and configuration transactions

• PCI bus speed up to 66 MHz with zero wait states

• Operates either synchronous or asynchronous to CPU clock; at slower, equal, or faster

clock frequency

• 32/64-bit PCI master and target operations

For the Katana PCI_0 is a 32/64-bit, 33/66MHz cPCI bus interface.

752i, PCI1 is a 32-bit, 33/66MHz local PCI bus interface.

PCI Configuration Space

The PCI slave supports Type 00 configuration space header as defined in the PCI specification. The MV64460 is a multi-function device and the header is implemented in all eight functions. The PCI interface implements the configuration header and this space is accessible from the CPU or PCI bus.

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Katana®752i User’s Manual 10006024-04

System Controller: PCI Interface

PCI Identification

The Katana®752i has been assigned the following PCI identification numbers.

Table 5-1: PCI Identification Values

Field: Value: Description:

Vendor ID 0x11AB Marvell Device ID 0x6480 MV64460 System Controller Subsystem Vendor ID 0x1223 Emerson Network Power Subsystem Device ID 0x0048 Katana

PCI Read/Write

The MV64460 becomes a PCI bus master when the CPU, IDMA, or MPSC SDMAs initiate a bus cycle to a PCI device. Conventional PCI mode allows unlimited DMA bursts between PCI and memory. It supports all PCI commands including 64-bit addressing using dual access cycles (DAC).

The MV64460 acts as a target when a PCI device initiates a memory access (or an I/O access in the case of internal registers, or a P2P transaction). It responds to all memory read and write accesses, including DAC, and to all configuration and I/O cycles in the case of internal registers. Its internal buffers allow unlimited burst reads and writes, and they support up to four pending delayed reads in conventional PCI mode.

752i

PCI Interface Registers

PCI0 and PCI1 contain the same set of internal registers, but are located at different offsets. A CPU access to the MV64460 PCIx Configuration register is performed via the PCIx Configuration Address and Data registers.

All PCI configuration registers are located at their standard offset in the configuration header, as defined in the PCI specification, when accessed from their corresponding PCI bus. For example, if a master on PCI1 performs a PCI configuration cycle on PCI’s Status and Command register, the register is located at 0x004.

A host access from the PCI interface to this register allows the target PCI device to acknowledge the interrupt by turning off the INTA* interrupt. Although the interrupts are active low, the register values are active high. For example, a value of one in the INTA field indicates that an interrupt is pending on INTA*. Also, writing a one to this location asserts the INTA* interrupt.

The Katana interrupt-generating registers or address ranges within their PCI bridges. The board will respond to interrupts caused by another PCI device when it accesses a programmable range of local memory, as provided by the MV64460 memory controller. In addition, it may

752i may generate interrupts to other PCI devices by accessing doorbell-type

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5-5

System Controller: Doorbell Registers

monitor the state of the PCI bus INTA*—INTD* signals (PCI1 only). The MV64460 contains registers that control the masking, unmasking, and priority of the PMC interrupts as inputs to the processor.

DOORBELL REGISTERS

The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts on both the PCI and CPU buses. There are two types of doorbell registers:

Outbound: These are set by the MV64460’s local CPU to request an interrupt service on the PCI bus.

Inbound: These are set by an external PCI agent to request interrupt service from the local CPU.

Outbound Doorbells

The local CPU generates an interrupt request to the PCI bus by setting bits in the Outbound Doorbell register (ODR). The interrupt may be masked in the Outbound Interrupt Mask register (OIMR), but that does not prevent the bit from being set in the ODR. The ODR is located at PCI_0 offset 0x1C2C.

Note: The CPU or the PCI interface can set the ODR bits. This allows for passing interrupt requests between CPU and

PCI interfaces.

Inbound Doorbells

The PCI bus generates an interrupt request to the local CPU by setting bits in the Inbound Doorbell register (IDR). The interrupt may be masked in the Inbound Interrupt Mask register (IIMR), but masking the interrupt does not prevent the bit from being set in the IDR. The IDR is located at PCI_0 offset 0x1C20.

Note: The interrupt request triggered from the PCI bus can be targeted to the CPU or to the PCI interface, depending

on the software setting of the interrupt mask registers.

WATCHDOG TIMER

The 32-bit count down watchdog timer generates a nonmaskable interrupt or resets the system in the event of unpredictable software behavior. After the watchdog is enabled, it is a free-running counter that requires periodic servicing to prevent its expiration. After reset, the watchdog is disabled.

RESET

Circuitry on the Katana®752i resets the entire board if the voltages fall out of tolerance or if the optional on-board reset switch is activated. Please refer to Chapter for additional information.

5-6

Katana®752i User’s Manual 10006024-04

System Controller: On-Card Memory

ON-CARD MEMORY

The Katana®752i has various types of on-card memory to support the MV64460 system controller and the 750GL processor. It has user Flash, SDRAM for data storage, and several serial EEPROMs for non-volatile memory storage. The following subsections describe these memory devices.

User Flash

The Katana®752i user Flash memory interface supports soldered devices of 32, 64, or 128 megabytes for the processor complex. The 32-megabyte configuration uses one bank of two 128 Mbit devices. The 64-megabyte configuration uses two banks of two 128 Mbit devices or one bank of 256 Mbit devices. The 128-megabyte configuration uses two banks of two 256 megabit devices. The soldered Flash banks provide a maximum of 128 megabytes of contiguous true Flash file system (TFFS) memory. The MV64460 controls this memory, located at E800,0000 sor boots from the soldered Flash (see Jumper JP2 location on page 2-5).

In addition to the soldered Flash memory, the Katana memory device of up to 512 kilobytes for the 750GL processor complex. This memory device is socketed and located at F800,0000 cessor can write to and boot from this memory.

on the processor 60x bus. By default, the 750GL proces-

752i also supports a single Flash

on the processor 60x bus. The 750GL pro-

SDRAM

The Katana®752i supports up to two gigabytes of 72-bit wide synchronous dynamic random access memory (SDRAM) for the 750GL processor complex. The SDRAM interface implements eight additional bits to allow for error correcting code (ECC).

Note: If a standard two-gigabyte SO-DIMM is installed, PMC Site #1 becomes inaccessible due to the dimensions of

the SO-DIMM. Also, the CPU and local bus frequencies are slightly different for this configuration. Using a two-gigabyte SO-DIMM will slightly increase the Katana

The SDRAM is in the form of a small-outline, dual in-line memory module (SO-DIMM) device. A serial EEPROM on the SO-DIMM provides configuration information, accessible via

the I

C interface at address AE16. The SDRAM occupies physical addresses from

0000,0000

to 7FFF,FFFF16 on the processor 60x bus. The MV64460 controls the SDRAM

and supports a double data rate (DDR) interface that allows for transfer speeds of up to 400 MHz (clock rates of up to 200 MHz).

10006024-04 Katana®752i User’s Manual

752i’s airflow requirements.

5-7

System Controller: I2C Interface

EEPROMs

The MV64460 uses an 8-kilobyte serial EEPROM at hex location 53 configuration data. Also, the MV64460 provides a second 8-kilobyte serial EEPROM at hex location A6 monitor, and operating system configurations. All Emerson-specific data is stored in the upper 2 kilobytes of the device. The SROM data organization is allocated as follows.

Table 5-2: NVRAM Allocation

Address Offset: Name: Window Size:

0x1E00-0x1FFF Reserved 0x0200 (512) bytes 0x1DDC-0x1DFF BootVerify parameters 0x0024 (36) bytes 0x1DD8-0x1DDB Power-on self-test (POST) diagnostic results 0x0004 (4) bytes 0x1800-0x1DD7 Monitor configuration parameters 0x05D8 (1496) bytes 0x1600-0x17FF Operating system 0x0200 (512) bytes 0x0000-0x15FF User Defined 0x1600 (5632) bytes

I2C INTERFACE

on the I2C bus to provide additional non-volatile information such as board,

on the I2C bus to store

The MV64460 has a built-in inter-integrated circuit (I2C) interface that supports master and

slave I

C devices. The following devices connect to the I2C bus:

• SO-DIMM SDRAM

• two 64-kilobit serial EEPROMs

• real-time clock (RTC) device

• Zircon PM IPMI controller and associated devices

The multiplexer shown in

Fig. 5-2 actually consists of two switches. One switch allows the

750GL processor to access the IPMI serial ROMs only while the IPMI controller is held in reset. The second switch allows the 750GL processor to access I end power is up–otherwise this connection is isolated. (Please refer to the Katana

C Port #1 only while back-

752i

schematics for details.)

5-8

Katana®752i User’s Manual 10006024-04

System Controller: I2C Interface

Figure 5-2: I2C Interface Diagram

MV64460 initialization

ROM

0xA4

NVRAM

0xA6

MUX

IPMI Bootcode

ROM

0xA2

and FRU ROM

Bootloader

0xA0

IPMI

MV64460

Bridge

software

through

control

PVT_SDA/SCL

Marvell

Configurable

address

MV1_SDA/SCL

SODIMM

ROM

0xAE

Real-time

0xD0

clock

mv1_port_sel

ipmi_rst*

Temperature

sensor

0x90

Temperature

sensor

0x92

IPMI_SDA/SCL

I2C #1

Configurable

Backplane IPMB

I2C #0

I2C #2

software

through

address

control

Devices on IPMI power

ipmi_rst*

ZirconPM IPMI

Controller

Qlogic

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5-9

System Controller: GPIO Signal Definitions

GPIO SIGNAL DEFINITIONS

The MV64460 system controller on the Katana®752i has 32 general-purpose input output (GPIO) pins that are used for various purposes. The following table describes the GPIO pin assignments.

Table 5-3: GPIO Signals Definitions

Pin: Direction: Description:

0 output console port transmit data 1 input console port receive data 2output PTMC site #1 PCI grant 3 input PTMC site #1 PCI request 4output PTMC site #2 PCI grant 5 input PTMC site #2 PCI request 6 output Ethernet MAC PCI grant 7 input Ethernet MAC PCI request 8 input PCI1 INTA 9 input PCI1 INTB 10 input PCI1 INTC 11 output INIT_ACT, driven to indicate the bridge is loading from serial ROM 12 input input from CPLD, used as synchronous versions of PERR and SERR 13 output driven low to turn off front panel fault LED once processor section is up

14 input PCI1 INTD 15 – unused 16 output watchdog NMI 17 output watchdog expired 18 output I2C_HOLDOFF signal (Zircon PM) 19 output output enable for PTMC RMII clocks 20 input baud rate input clock for serial port 21—22 – unused 23 input IPMI Timerout, driven by IPMI microcontroller when there is a time-

24 output POST indicator 25 output driven high to put the IPMI microcontroller in reset 26 input Watchdog Maskable Interrupt (in) 27 input GIG0_INT interrupt signal from gigabit PHY (unused on rev. 0—1

28 input GIG1_INT interrupt signal from gigabit PHY (unused on rev. 0—1

29 input GIG2_INT interrupt signal from gigabit PHY (unused on rev. 0—1

and running

out condition

boards)

5-10

Katana®752i User’s Manual 10006024-04

System Controller: Console Serial Port

Twisted Pairs

DB9 Connector Mini DB9 Connector

GND (Green)

CONSOLE Rx (Red)

CONSOLE Tx (Black)

CONSOLE Rx (Red)

CONSOLE Tx (Black)

Shield (Braid to shell 360 connection)

SHELL SHELL

9 8 7 6 5 4 3 2 1

Pin: Direction: Description: (continued)

30 – unused 31 input MVL_PCI0_HS signal, ejector handle status; 1=latch closed, 0=latch

CONSOLE SERIAL PORT

The processor complex on the Katana®752i has an asynchronous console serial port on the front panel. This port operates at EIA-232 signal levels, but does not provide any handshaking functionality. The connector for the front panel console port is a mini-DB9 connector, with the following pin assignments.

Table 5-4: Serial Console Port Pin Assignments, (P2)

Pin: Signal: Pin: Signal:

1 no connection 6 no connection 2 RXD (Data Out) 7 no connection 3 TXD (Data In) 8 no connection 4 no connection 9 no connection 5 ground 10-11 CHS_GND

open (For rev. 0 boards, software must debounce switch input.)

The standard Emerson console cable (#10007665-00) is cross-pinned, as shown in the figure below. A straight-through connector (#10007664-00) also is available.

Figure 5-3: Standard Console Cable Wiring, #10007665-00

Note: Cable part numbers are subject to change. Please check with Emerson before ordering replacement cables.

The Katana®752i also provides serial console port access via the J5 CompactPCI connector at pins E15 and D15 (refer to page 14-3 for pinouts).

10006024-04 Katana®752i User’s Manual

5-11

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5-12

Katana®752i User’s Manual 10006024-04

Device Bus PLD

The processor complex on the Katana®752i has a programmable logic device (PLD) that provides control logic for the 750GL device bus. This PLD implements various registers relating to reset control, interrupt handling, product identification, PCI enumeration, and board configuration. This chapter describes the registers in the device bus PLD, which is also known as the MVC PLD.

RESET REGISTERS

The device bus PLD routes and distributes the reset signals. Two registers support this functionality. The read-only Reset Event register at hex location F820,0000 son for the last reset as follows.

76543210

InitAct Reserved WD COPS COPH PMCR CPCI FP

indicates the rea-

Section 6

InitAct: Initialization Active:

Set to 1 when the MV64460 InitAct pin does not go inactive after reset

WD: Watchdog:

Set to 1 when a reset was caused by the expiration of the MV64460 watchdog timer

COPS: Soft Reset:

Set to 1 when a COP header soft reset (SRESET) has occurred

COPH: Hard Reset:

Set to 1 when a COP header hard reset (HRESET) has occurred

PMCR: PMC Reset:

Set to 1 when a PPMC issues a PMC Reset Out

CPCI: CPCI:

Set to 1 when a cPCI reset (RST* signal) has occurred

FP: Front Panel:

Set to 1 when the front panel switch caused a reset

The Reset Command register at hex location F820,1000 resets, as shown below. After a reset sequence is initiated by writing a one to a valid bit, the bit is automatically cleared.

Note: When writing to this register, only set one bit at a time.

forces one of several types of

10006024-04 Katana®752i User’s Manual

6-1

Device Bus PLD: Interrupt Registers

76543210

SCL SDA PCI0

SCL: Direct control for I2C clock signal:

1=Tri-states the PLD 0=Drives logic low

SDA: Direct control for I

C data signal: 1=Tri-states the PLD 0=Drives logic low

PCI0 : PCI0 reset status, as set by JP1, pins 7-8;

software should not overwrite this value: 1=cPCI functionality is disabled

(MV64460 PCI0 interface held in reset)

0=cPCI functionality is enabled

(MV64460 PCI0 interface reset deasserted)

Reserved

FR Reserved HR

FR: Flash Reset command:

1=Causes Flash to be reset, clears automatically 0=No Flash reset (default)

HR: Hard Reset command:

1=Causes a hard reset on board, clears automatically 0=No hard reset (default)

INTERRUPT REGISTERS

The system error and parity error interrupts from the PCI bus route to the device bus PLD. Sampling for these signals occurs on the rising edge of the PCI clock, according to the PCI specification. The software should hold these signals low for a clock cycle, otherwise they will be ignored. PERR and SERR have two loads, which are combined in the PLD to a single interrupt and route to the MPP12 pin on the MV64460.

The Interrupt Enable register at hex location F820,2000 lows.

76543210

contains two enable bits, as fol-

Reserved SREN PREN

6-2

Katana®752i User’s Manual 10006024-04

Device Bus PLD: Product Identification

SREN: PCI SERR Enable interrupt routed from PCI SERR to MV64460:

1=Enabled to generate an interrupt 0=Disabled (default)

PREN: PCI PERR Enable interrupt routed from PCI PERR to MV64460:

1=Enabled to generate an interrupt 0=Disabled (default)

The Interrupt Pending register at hex location F820,3000 which source has caused an interrupt, as follows.

76543210

SERR: PCI SERR Enable

1=SERR has occurred and is enabled (IER SR1EN=1) 0=No SERR (default).

PERR: PCI PERR Enable

1=PERR has occurred and is enabled (IER PR1EN=1) 0=No PERR (default).

PRODUCT IDENTIFICATION

The read-only Product ID register at hex location F820,400016 identifies the Katana®752i.

76543210

PIR: Product Identification register:

=Katana®752i

allows software to determine

Reserved SERR PERR

PIR

PCI ENUMERATION

The Katana®752i provides a register for status and control of enumeration. In a Monarch system, the EReady register at hex location F820,5000 boards in the system are ready for enumeration. In a non-Monarch system, the register is writeable to indicate the Katana

752i is ready for enumeration.

10006024-04 Katana®752i User’s Manual

is readable to indicate that other

6-3

Device Bus PLD: Revision Registers

76543210

Reserved ERdy

ERdy: Monarch (read):

1=PCI devices are ready to be enumerated 0=PCI devices not ready to be enumerated

Non-Monarch (write): 1=PMC is ready to be enumerated 0=PMC is not ready to be enumerated

REVISION REGISTERS

The Katana®752i device bus PLD provides two read only registers to track hardware and PLD revisions. The Hardware Version register at hex location F820,7000 coded tracking number for the hardware.

provides a hard-

76543210

HVR: Hardware version number:

This is hard coded in the PLD and changed with every major PCB version. Version starts at 00

The PLD Version register at hex location F820,8000 ber for the PLD code.

76543210

PVR: Code version number:

This is hard coded in the PLD and changed with every major code change. Version starts at 00

BOARD CONFIGURATION REGISTERS

Three byte-wide, read-only Board Configuration registers allow the monitor software to easily determine specific hardware configurations. The Board Configuration 3 register at hex location F820,C000

HVR

provides a hard-coded tracking num-

PVR

indicates if the Katana®752i is a Monarch.

6-4

Katana®752i User’s Manual 10006024-04

Device Bus PLD: Board Configuration Registers

Note: Board Configuration 2 register is not implemented in the Katana®752i.

76543210

Reserved cPCI Mon Reserved

cPCI: cPCI bus status indication:

1=cPCI bus is disabled (held in reset) (default) 0=cPCI bus is enabled

Mon: Monarch indication:

1=Katana

752i is Monarch

0=PMC is Monarch

The Board Configuration 1 register at hex location F820,A000 tion about the Flash memory, as follows.

76543210

Reserved Boot

Socket

Boot Socket: Boot from socketed Flash or from soldered Flash:

1=Boot from socketed Flash 0=Boot from soldered Flash

The Board Configuration 0 register at hex location F820,9000 speed and the H.110 option status, as follows.

76543210

SysCLK H110 Reserved

SysCLK: System clock speed:

11=133MHz 10=166MHz 01=100MHz 00=200MHz

provides status informa-

Reserved

indicates the system clock

H110: H.110 option installed:

1=yes 0=no (default)

10006024-04 Katana®752i User’s Manual

6-5

Device Bus PLD: Other Registers

OTHER REGISTERS

The IPMI Port Select register at hex location F820,E00016 allows access to the IPMI interface, as follows.

7 6543210

PORT_SEL Reserved

PORT_SEL: IPMI Port Selection:

Allow processor access to the IPMI controller and temperature sensors 1=Disabled (default) 0=Enabled

The LED register at hex location F820,D000 LEDs (on the Katana

76543210

Reserved LED4 LED3 LED2 LED1

LED1—LED4: Programmable LEDs:

Illuminate the corresponding LED 1=on 0=off (default)

752i front panel), as follows.

allows software to access the programmable

6-6

Katana®752i User’s Manual 10006024-04

Real-Time Clock

Seconds

Minutes

Century/Hours

Day

Date

Month

Year

Control

1Hz

OSC1

OSC0

FT/OUT

SCL

SDA

BAT

Address Register

Control

Logic

Divider

Oscillator

32.768 KHz

Voltage

Sense and

Switch

Circuitry

Serial

Bus

Interface

The processor complex on the Katana®752i has a standard real-time clock (RTC), consisting of an M41T00 device from STMicroelectronics. The M41T00 has an integrated year-2000compatible RTC, power sense circuitry, and uses eight bytes of non-volatile RAM for the clock/calendar function. It is powered from the +3.3 volt rail during normal operation. The M41T00 device connects to an I page 5-8). The M41T00 device is backed up by power from a single, super capacitor, which will hold a charge for at least two hours.

BLOCK DIAGRAM

The following block diagram shows the basic structure of the M41T00 device.

Figure 7-1: M41T00 Real-Time Clock Block Diagram

C bus (see

Section 7

OPERATION

The M41T00 clock operates as a slave device on the serial bus. To obtain access, the RTC implements a start condition followed by the correct slave address (D0 bytes in the following order:

10006024-04 Katana®752i User’s Manual

). Access the eight

7-1

Real-Time Clock: Clock Operation

1 Seconds register

2 Minutes register

3 Century/Hours register

4 Day register

5 Date register

6 Month register

7 Years register

8 Control register

The M41T00 clock continually monitors the supply voltage (Vcc) for an out of tolerance condition. If Vcc falls below switch-over voltage (Vso), the M41T00:

• Terminates an access in progress

• Resets the device address counter

• Does not recognize inputs (prevents erroneous data from being written)

At power-up, the M41T00 uses Vcc at Vso and recognizes inputs.

CLOCK OPERATION

Read the seven Clock registers one byte at a time or in a sequential block. Access the Control register (address location 7) independently. An update to the Clock registers is delayed for 250 ms to allow the read to be completed before the update occurs. This delay does not alter the actual clock time. The eight byte clock register sets the clock and reads the date and time from the clock, as summarized in

Table 7-1: RTC Register Map

Address: Data: Function/Range:

D7 D6 D5 D4 D3 D2 D1 D0 BCD Format:

00 ST 10 Seconds Seconds Seconds 00—59 01 X 10 Minutes Minutes Minutes 00—59 02 CEB CB 10 Hours Hours Century/Hours 0-1/00-23 03 X XXX XDay Day 01—07 04 X X 10 Date Date Date 01—31

10 M

05 X X X 06 10 Years Years Years 00—99 07 OUT FT S Calibration Control —

Month Month 01—12

Table 7-1.

7-2

Katana®752i User’s Manual 10006024-04

Real-Time Clock: Clock Operation

ST: Stop bit

1=Stops the oscillator 0=Restarts the oscillator within one second

CEB: Century Enable Bit

1=Causes CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century 0=CB will not toggle

CB: Century Bit

Day: Day of the week

Date: Day of the month

OUT: Output level

1=Default at initial power-up 0=FT/OUT (pin 7) driven low when FT is also zero

FT: Frequency Test bit

1=When oscillator is running at 32,768 Hz, the FT/OUT pin will toggle at 512 Hz 0=The FT/OUT pin is an output driver (default at initial power-up)

S: Sign bit

1=Positive calibration 0=Negative calibration

Calibration: Calibration bits

The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends on this five-bit byte. Adding counts accelerates the clock, and subtracting counts slows the clock down.

X: Don’t care bit.

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7-3

(blank page)

7-4

Katana®752i User’s Manual 10006024-04

Local PCI Bus

The Katana®752i utilizes the Peripheral Component Interconnect (PCI) bus as the interface between the 750GL processor complex, PCI Telecom Mezzanine Card (PTMC) sites, optional T8110 time slot interchanger (TSI), and 82544 Ethernet media access controller (MAC). The Katana PMC mechanical interface standard. The Marvell MV64460 device functions as the PCI bridge and always performs local PCI bus arbitration.

The following devices are on the PCI bus:

• IBM 750GL processor complex (host controller by default)

• Two PCI expansion sites (Monarch or non-Monarch)

• Optional Ambassador T8110 TSI (PCI target only)

• Intel 82544 Ethernet MAC

Note: When the optional T8110 time slot interchanger is installed, the PCI bus speed is limited to 33MHz.

752i complies with the PCI bus interface standard and the associated

Section 8

PCI ENUMERATION

By default, the 750GL processor complex functions as a Monarch. In this mode, the MV64460 serves as a PCI system controller. It provides PCI arbitration and PCI bus enumeration. The Katana either PTMC site as the Monarch.

The PCI standard allows for environments where the number and types of devices on the PCI bus varies. Therefore, the Katana system controller dynamically defines the memory map using a process called enumeration. In this process, the PCI system controller probes the PCI bus to discover what devices are installed and how much memory space each device is requesting. The system controller then allocates the available PCI memory, defines the base address of each device, and configures the PCI base address registers for each device accordingly.

PCI device software should assign physical addresses dynamically, in the format of “base address + offset”. The enumeration routine can retrieve the base address. The offset is device-dependent and fixed. The monitor software performs enumeration routines at power-up and PCI reset. The operating system also performs enumeration upon booting. The monitor and operating system both have built-in hooks for retrieving the base addresses.

752i also has configuration jumpers at JP2 (see Fig. 2-4) which can set

752i does not support a fixed memory map. The PCI

PCI ID SELECT AND INTERRUPTS

The Katana®752i follows the typical PCI convention for assigning ID Select signals, as shown in the following table.

10006024-04 Katana®752i User’s Manual

8-1

Local PCI Bus: Geographical Addressing

Table 8-1: ID Select Connections

Katana®752i PCI Device IDSEL Address

PTMC Site 1 (at J12) AD20 PTMC Site 2 (at J22) AD21 T8110 Time Slot Interchanger (TSI) AD22 MV64460 System Controller AD23 82544 Ethernet MAC AD24

The T8110 TSI connects to INTD. The MV64460 system controller connects to INTA. The Ethernet MAC connects to INTD. The PCI devices on the PTMC module(s) use the following connections.

Table 8-2: Interrupt Connections for Katana®752i

MV64460: PTMC #1: PTMC #2: 82544EI: T8110:

INTA INTD INTC – – INTB INTA INTD – – INTC INTB INTA – – INTD INTC INTB INT INT

GEOGRAPHICAL ADDRESSING

The Katana®752i has three read-only registers that allow the software to read Geographical Addresses from the CompactPCI backplane connectors. The following table describes these registers.

Table 8-3: Geographical Address Registers

J4SGA F821,0000 Read the Shelf Enumeration Bus pins from cPCI J4 connector. J4GA F821,0001 Read the Geographical Address from cPCI J4 connector. J2GA F821,0002 Read the Geographical Address from the cPCI J2 connector.

PCI BUS CONTROL SIGNALS

This section lists signals for the PCI interface which are available on PMC connectors J11, J12, J21, and J22 (see also pinout tables beginning on page 9-3). Please refer to the PCI specification for details on using these signals. All signals are bi-directional unless otherwise stated.

Note: A sustained three-state line is driven high for one clock cycle before float.

8-2

Katana®752i User’s Manual 10006024-04

Local PCI Bus: PCI Bus Control Signals

ACK64*, REQ64*: These sustained three-state output signals tell a 64-bit PCI device whether to use the 64-bit

or the 32-bit data width. Since the Katana

752i is a 32-bit board, these signals are tied off

to indicate the 32-bit data width.

AD00-AD31: ADDRESS and DATA bus (bits 0-31). These three-state lines are used for both address and

data handling. A bus transaction consists of an address phase followed by one or more data phases.

C/BE0*-C/BE3*: BUS COMMAND and BYTE ENABLES. These three-state lines have different functions

depending on the phase of a transaction. During the address phase of a transaction these lines define the bus command. During a data phase the lines are used as byte enables.

CLK: CLOCK. This is an input signal that provides timing for PCI transactions. (This is unused,

since the Katana

752i generates its own PCI clock signal.)

DEVSEL*: DEVICE SELECT. This sustained three-state signal indicates when a device on the bus has

been selected as the target of the current access.

EREADY: READY. This signal is an input for Monarch devices and an output for non-Monarch devices.

It indicates that all modules are initialized and the PCI bus is ready to be enumerated.

FRAME*: CYCLE FRAME. This sustained three-state line is driven by the current master to indicate the

beginning of an access, and continues to be asserted until transaction reaches its final data phase.

GNT*: GRANT. This input signal indicates that access to the bus has been granted to a particular

master. Each master has its own GNT*.

IDSEL: INITIALIZATION DEVICE SELECT. This input signal acts as a chip select during configuration

read and write transactions.

INTA*, INTB*, INTC*, INTD*:

PMC INTERRUPTS A, B, C, D. These interrupt lines are used by PCI devices to interrupt the host processor.

IRDY*: INITIATOR READY. This sustained three-state signal indicates that the bus master is ready

to complete the data phase of the transaction.

M66EN: ENABLE 66 MHZ. When grounded, this signal prevents 66 MHz operation of the PCI bus.

MONARCH*: MONARCH. When this signal is grounded, it indicates that the Katana

Monarch and must provide PCI bus enumeration and interrupt handling.

LOCK*: LOCK. This sustained three-state signal indicates that an automatic operation may require

multiple transactions to complete. (The Katana

752i baseboard is a

752i does not support this signal.)

10006024-04 Katana®752i User’s Manual

8-3

Local PCI Bus: PCI Bus Control Signals

PAR: PARITY. This is even parity across AD00-AD31 and C/BE0-C/BE3*. Parity generation is

required by all PCI agents. This three-state signal is stable and valid one clock after the address phase, and one clock after the bus master indicates that it is ready to complete the data phase (either IRDY* or TRDY* is asserted). Once PAR is asserted, it remains valid until one clock after the completion of the current data phase.

PERR*: PARITY ERROR. This sustained three-state line is used to report parity errors during all PCI

transactions.

PME*: POWER MANAGEMENT EVENT. This optional open-drain signal (pull-up resistor required)

allows a device to request a change in the power state. Devices must be enabled by software before asserting this signal. (The Katana

752i does not support this signal.)

PRESENT*: PRESENT. When grounded, this signal indicates to a carrier that a PMC module is installed.

(The Katana

752i does not support this signal.)

RESET_OUT*: RESET OUTPUT. This optional output signal may be used to support another source. To

avoid reset loops, do not use RST* to generate RESET_OUT*.

REQ*: REQUEST. This output pin indicates to the arbiter that a particular master wants to use the

bus.

RST*: RESET. The assertion of this input line brings PCI registers, sequencers, and signals to a con-

sistent state.

SERR*: SYSTEMS ERROR. This open-collector output signal is used to report any system error with

catastrophic results.

STOP*: STOP. This is a sustained three-state signal used by the current target to request that the

bus master stop the current transaction.

TRDY*: TARGET READY. This is a sustained three-state signal that indicates the target’s ability to

complete the current data phase of the transaction.

8-4

Katana®752i User’s Manual 10006024-04

PTMC Interface

J3J4J5

J22

J21

J24

J23

J12

J11

J1J2

J14

J13

PTMC Module

(bottom side)

PTMC2

PTMC Module

(bottom side)

PTMC1

J12

J11

J14

J13

J21

J22J24

J23

J24J22

J23J21

The Katana®752i Peripheral Component Interconnect (PCI) interface supports two PCI Telecom Mezzanine Card (PTMC) expansion sites. This chapter describes how to install PTMC modules and provides additional information about the PTMC signals. Each PTMC site can connect to two optional KS8721CL RMII PHY devices that route to the CompactPCI backplane connector J5 (see page 10-3). The Katana the PCI Telecom Mezzanine/Carrier Card Specification, PICMG 2.15 (see also “Timing Considerations” on page 12-5).

PTMC INSTALLATION

The Katana®752i baseboard has two sets of four connectors (J11—J14 and J21—J24), as defined by the PMC specification. Katana tion.)

Figure 9-1: PTMC Module Location on Baseboard

752i complies with Configuration 2 of

Fig. 9-1 shows the location of these connectors on the

752i. (Connectors J13 and J23 are only present in the optional CT bus configura-

Section 9

10006024-04 Katana®752i User’s Manual

9-1

PTMC Interface: PTMC Installation

Tighten these two screws first.

PTMC1

PTMC2

P11

P12

J11

J12

J14

J13

PTMC Module

P13

P14

J21

J22

J23

J24

The following procedure describes how to attach a PTMC module to the Katana®752i baseboard:

1 Remove the screws from the standoffs on the PTMC module.

2 Hold the module at an angle and gently slide the faceplate into the opening on the

baseboard.

3 Align the P11, P12, P13, and P14 connectors and gently press the module into place until

firmly mated.

Caution: To avoid damaging the module and/or baseboard, do not force the module onto the

baseboard.

4 Using four M2.5x6mm flathead screws, secure the PTMC module from the bottom of the

baseboard. First, insert and tighten the screws closest to the P11, P12, P13, and P14 connectors. Next, insert and tighten the screws nearest to the front panel.

9-2

Katana®752i User’s Manual 10006024-04

PTMC Interface: PTMC Connector Pinouts

PTMC CONNECTOR PINOUTS

PCI expansion site #1 has four 64-pin connectors, J11—J14 (see Fig. 2-2 on page 2-3 for connector locations).

Table 9-1: J1x PTMC Connector Pin Assignments

Pin J11 J12 J13 J14

1 TCK POS_12V MDIO J3_E13 2 NEG_12V 3GND 4INTA* 5INTB* 6INTC* GND SRX J3_E12 7 PRESENT* GND RXER J3_D12 8 +5V 9INTD* 10 11 GND PUP0 GND J3_E11 12 +3.3V +3.3V TXD1 J3_D11 13 PCICLK RST* REFCLK J3_C11 14 GND PDN0 GND J3_B11 15 GND +3.3V GND J3_A11 16 GNT* PDN1 RXD0 J3_E10 17 REQ* PME* CT_FA J3_D10 18 +5V GND RXD1 J3_C10 19 +3.3V AD30 CT_FB J3_B10 20 AD31 AD29 GND J3_A10 21 AD28 GND PTID0 J3_E9 22 AD27 AD26 TXEN J3_D9 23 AD25 AD24 GND J3_C9 24 GND +3.3V CAS_DV J3_B9 25 GND IDSEL CT_C8A J3_A9 26 CBE3* AD23 GND J3_E8 27 AD22 +3.3V GND J3_D8 28 AD21 AD20 CT_D19 J3_C8 29 AD19 AD18 CT_D18 J3_B8 30 +5V GND CT_D17 J3_A8 31 +3.3V AD16 CT_D16 J3_E7 32 AD17 CBE2* GND J3_D7 33 FRAME* GND GND J3_C7 34 GND IDSELB NETREF2 J3_B7

Table 9-1 shows the pin assignments.

PMC1_TRST* PMC1_TMS PMC1_TDO PMC1

_TDI MDC J3_A13

no connection no connection

GND J3_D13 GND J3_C13 STX J3_B13

GND J3_C12 PTID2 J3_B12 TXD0 J3_A12

10006024-04 Katana®752i User’s Manual

9-3

PTMC Interface: PTMC Connector Pinouts

Pin J11 J12 J13 J14

35 GND TRDY* CT_D14 J3_A7 36 IRDY* +3.3V 37 DEVSEL* GND CT_D12 J3_D6 38 +5V STOP* GND J3_C6 39 GND PERR* PTENB* J3_B6 40 LOCK* GND 41 SDONE* +3.3V GND J3_E5 42 SBO* SERR* NETREF1 J3_D5 43 PAR CBE1* CT_C8B J3_C5 44 GND GND GND J3_B5 45 +3.3V AD14 GND J3_A5 46 AD15 AD13 CT_D15 J3_E4 47 AD12 M66EN CT_D10 J3_D4 48 AD11 AD10 CT_D13 J3_C4 49 AD9 AD8 CT_D8 J3_B4 50 +5V +3.3V CT_D11 J3_A4 51 GND AD7 GND J3_E3 52 CBE0* REQB* CT_D9 J3_D3 53 AD6 +3.3V CT_D6 J3_C3 54 AD5 GNTB* CT_D7 J3_B3 55 AD4 56 GND GND GND J3_E2 57 +3.3V 58 AD3 EREADY CT_D5 J3_C2 59 AD2 GND CT_D2 J3_B2 60 AD1 61 AD0 ACK64* CT_D0 J3_E1 62 +5V +3.3V GND J3_D1 63 GND GND GND J3_C1 64 REQ64*

no connection

RESETOUT*

MONARCH*

no connection

CT_D4 J3_A3

PTID1 J3_D2

CT_D3 J3_A2

CT_D1 J3_B1

J3_E6

J3_A6

9-4

Katana®752i User’s Manual 10006024-04

PTMC Interface: PTMC Connector Pinouts

PCI expansion site #2 has four 64-pin connectors, J21—J24 (see Fig. 2-2 on page 2-3 for connector locations).

Table 9-2: J2x PTMC Connector Pin Assignments

Pin J21 J22 J23 J24

1 TCK POS_12V MDIO J5_E13 2 NEG_12V 3GND 4INTA* 5INTB* 6INTC* GND SRX J5_E12 7 PRESENT* GND RXER J5_D12 8 +5V 9INTD* 10 11 GND PUP0 GND J5_E11 12 +3.3V +3.3V TXD1 J5_D11 13 PCICLK RST* RE 14 GND PDN0 GND J5_B11 15 GND +3.3V GND J5_A11 16 GNT* PDN1 RXD0 J5_E10 17 REQ* PME* CT_FA J5_D10 18 +5V GND RXD1 J5_C10 19 +3.3V AD30 CT_FB J5_B10 20 AD31 AD29 GND J5_A10 21 AD28 GND PTID0 J5_E9 22 AD27 AD26 TXEN J5_D9 23 AD25 AD24 GND J5_C9 24 GND +3.3V CAS_DV J5_B9 25 GND AD21 CT_C8A J5_A9 26 CBE3* AD23 GND J5_E8 27 AD22 +3.3V GND J5_D8 28 AD21 AD20 CT_D19 J5_C8 29 AD19 AD18 CT_D18 J5_B8 30 +5V GND CT_D17 J5_A8 31 +3.3V AD16 CT_D16 J5_E7 32 AD17 CBE2* GND J5_D7 33 FRAME* GND GND J5_C7 34 GND IDSELB NETREF2 J5_B7 35 GND TRDY* CT_D14 J5_A7 36 IRDY* +3.3V

Table 9-2 shows the pin assignments.

PMC2_TRST* PMC2_TMS PMC2_TDO PMC2_

TDI MDC J5_A13

no connection no connection

GND J5_D13 GND J5_C13 STX J5_B13

GND J5_C12 PTID2 J5_B12 TXD0 J5_A12

no connection

FCLK

J5_C11

J5_E6

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9-5

PTMC Interface: PTMC Connector Pinouts

Pin J21 J22 J23 J24

37 DEVSEL* GND CT_D12 J5_D6 38 +5V STOP* GND J5_C6 39 GND PERR* PTENB* J5_B6 40 LOCK* GND 41 SDONE* +3.3V GND J5_E5 42 SBO* SERR* NETREF1 J5_D5 43 PAR CBE1* CT_C8B J5_C5 44 GND GND GND J5_B5 45 +3.3V AD14 GND J5_A5 46 AD15 AD13 CT_D15 J5_E4 47 AD12 M66EN CT_D10 J5_D4 48 AD11 AD10 CT_D13 J5_C4 49 AD9 AD8 CT_D8 J5_B4 50 +5V +3.3V CT_D11 J5_A4 51 GND AD7 GND J5_E3 52 CBE0* REQB* CT_D9 J5_D3 53 AD6 +3.3V CT_D6 J5_C3 54 AD5 GNTB* CT_D7 J5_B3 55 AD4 56 GND GND GND J5_E2 57 +3.3V 58 AD3 EREADY CT_D5 J5_C2 59 AD2 GND CT_D2 J5_B2 60 AD1 61 AD0 ACK64* CT_D0 J5_E1 62 +5V +3.3V GND J5_D1 63 GND GND GND J5_C1 64 REQ64*

no connection

RESETOUT*

MONARCH*

no connection

CT_D4 J5_A3

PTID1 J5_D2

CT_D3 J5_A2

CT_D1 J5_B1

J5_A6

9-6

Katana®752i User’s Manual 10006024-04

Ethernet Interfaces

The Katana®752i supports four 10/100/1000BaseT Ethernet ports. The MV64460 system controller provides three Ethernet Media Access Control (MAC) units, and an Intel 82544EI Ethernet controller device provides direct access from the local PCI bus. Three Broadcom BCM5461S transceivers and an integrated PHY in the 82544EI provide interfaces for the 10/100/1000BaseT Ethernet ports. Two of these ports route to the Katana panel, and two route to the J3 CompactPCI packet-switched backplane (cPSB) connector. The Katana two RMII PHY devices that route to the J5 CompactPCI (cPCI) backplane connector.

ETHERNET ADDRESS

The Ethernet address for your board is a unique identifier on a network and must not be altered. The address consists of 48 bits (Medium Access Control—MAC[47:0]) divided into two equal parts. The upper 24 bits define a unique identifier that has been assigned to Emerson Network Power, Embedded Computing by IEEE. The lower 24 bits are defined by Emerson for identification of each of our products.

The Ethernet address for the Katana digits separated into pairs, with each pair representing eight bits. The address assigned to the Katana

752i also provides optional Ethernet connectivity for each PTMC site, using

752i has the following form:

Section 10

752i front

752i is a binary number referenced as 12 hexadecimal

00 80 F9 6x yy zz

00 80 F9 is Emerson’s identifier. The last three bytes of the Ethernet address comprise the data for the Ethernet addresses in non-volatile memory. 6 is defined by Emerson and is specific to the Katana

752i. x, yy, and zz are calculated.

For the purpose of this calculation, the entire MAC address can be thought of as a 48-bit register, as shown in Register Map 10-1.

MAC[47:0]

00 80 F9 6x yy zz

0000 0000 1000 0000 1111 1001 0110 110x yyyy yyyy zzzz zzzz

47:24

Fixed

23:17

Fixed

16:3

Calculated

To determine the last 17 bits of the MAC address (x, yy, and zz):

1 Subtract 1000 from the decimal serial number, convert it to hex, and place the 14-bit result

in MAC[16:3].

2 Set the remaining three bits, MAC[2:0], according to the following list:

000 = CPSB_1 (MAC address #1)

10006024-04 Katana®752i User’s Manual

2:0 List

10-1

Ethernet Interfaces: Ethernet Ports

001 = CPSB_1 (MAC address #2) 010 = CPSB_2 011 = FRNT_1 (ETH3) 100 = FRNT_2 (ETH4) 101 = reserved 110 = reserved 111 = reserved

So for example, if the Katana 00:80:F9:6C:07:52.

ETHERNET PORTS

752i serial number is 1234, the CPSB_2 MAC address is:

The MV64460 system controller (see Chapter ) provides three 10/100/1000BaseT gigabit Ethernet (GbE) ports. Also, the Katana from the local PCI bus via an Intel 82544EI Ethernet controller device. Two ports connect to the front panel (see Section for pinouts), and two connect to the J3 cPSB connector (see

Table 14-3 for pinouts).

• If the Katana

J3 allow for cPSB functionality. If the Katana support a cPSB backplane, the J3 ports can be routed via a rear transition module to provide two GbE input/output ports.

Four Broadcom BCM5461S transceivers provide the physical interface for these ports. There are eight LEDs associated with the GbE ports (see the component map on page 2-6 for LED locations).

Table 10-1: GbE Port LEDs

GbE Port 1 GbE Port 2

CR34=ACT CR20=ACT CR32=LINK CR21=LINK CR33=LINK2 CR22=LINK2 CR35=LINK1 CR23=LINK1

FRONT PANEL ETHERNET CONNECTOR PINOUTS

The Katana®752i has a dual-RJ45 connector, P1, for the two front panel Ethernet ports. (Refer to the front panel drawing on page 2-2.) The ETH4 port connects to the 82544EI Ethernet controller. The ETH3 port connects to the MV64460 system controller. The dualRJ45 connector has integrated speed (SP) and activity (ACT) LEDs to show the status of each port. The pin assignments are as follows.

752i provides direct access to a fourth GbE port

752i is installed in a system that supports a cPSB backplane, the two ports at

752i is installed in a system that does not

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Katana®752i User’s Manual 10006024-04

Ethernet Interfaces: Optional RMII PHY Devices

Table 10-2: 82544EI Ethernet Port Pin Assignments, ETH4

Pin Signal Pin Signal

1TRD0+ 5TRD2+ 2TRD0— 6TRD2— 3TRD1+ 7TRD3+ 4TRD1— 8TRD3—

Table 10-3: MV64460 Ethernet Port Pin Assignments, ETH3

Pin Signal Pin Signal

1TRD0+ 5TRD2+ 2TRD0— 6TRD2— 3TRD1+ 7TRD3+ 4TRD1— 8TRD3—

OPTIONAL RMII PHY DEVICES

In addition to the four GbE ports, the Katana®752i supports an option for two RMII PHY devices on the Katana plane connector, J5. Each PTMC site has its own PHY address and LEDs, as shown in

and Fig. 10-1. See Fig. 2-3 for LED locations.

Table 10-4: PTMC PHY Address

752i (one for each PTMC site). These route to the CompactPCI back-

Table 10-

PTMC Site: PHY Address: LEDs:

1 0x5 CR43=ACT

2 0x6 CR45=ACT

Note: The Katana

MV64460 MPP port enables this functionality. However, before setting the bit, ensure that the RMII PHYs are installed and the PT2MC card supports an RMII interface. By default, REFCLK is enabled (bit is high). Clearing this bit causes the Katana

752i may drive the RMII REFCLK to the PTMC connectors and the PHYs. Setting bit 19 at the

752i to stop driving REFCLK so that a PTMC module can drive it instead.

CR44=LINK

CR46=LINK

Caution: To ensure proper signal integrity, the RTM magnetics must have a +2.5-volt offset on the

center taps for both the TX and RX differential pairs.

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10-3

Ethernet Interfaces: Optional RMII PHY Devices

PTMC

Site 1

PTMC

Site 2

P13 P23

Katana752i

Optional Rear Transition Module

(i.e. TM/cSPAN-P8E)

Magnetics

PHY

0x5

PHY

0x6

RMII

CR43 CR44

CR45 CR46

+2.5V

Backplane

RJ45RJ45

Figure 10-1: RMII PHY to Transition Module

10-4

Katana®752i User’s Manual 10006024-04

IPMI Controller

The Katana®752i implements a System Management Bus (SMB), as defined in the CompactPCI System Management Specification (see Platform Management Interface (IPMI) Version 1.5 and Intelligent Platform Management Bus (IPMB) Version 1.0 specifications. At the core of SMB/IPMI interface is a Zircon PM device from QLogic Corporation. This device is a microprocessor-based Intelligent Platform Management Controller that implements all the standard IPMI commands and provides hardware interfaces for other system management features.

SMB/IPMI OVERVIEW

The basic features for the Katana®752i SMB/IPMI implementation include:

• conformance to IPMI version 1.5 and IPMB version 1.0

• geographical addressing according to PICMG 2.9

• ability to read and write Field Replaceable Unit (FRU) data

Section 11

Table 1-2). It also supports the Intelligent

• ability to reset from SMB or local processor

• ability to read two airflow temperature sensors

• ability to read six board voltage sensors

• ability to read a watchdog sensor for the 750GL processor

• ability to send event messages to a specified receiver

• all sensors generate assertion and/or de-assertion event messages

• ability to control GPIO to assert resets to various sections of the board

• ability to broadcast a heartbeat message to a specified receiver

• support for field updates of firmware via SMB or local processor

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11-1

IPMI Controller: SMB/IPMI Overview

The Katana®752i system management interface uses the Zircon PM device’s general-purpose input/output (GPIO) pins for the following functions:

• watchdog sensor input (from 750GL processor)

• GPIO (to 750GL processor)

• reset outputs (to 750GL processor)

• IPMI reset control

• cPCI Geographical Addressing inputs

The Zircon PM controller also has input pins to sense all on-board voltage supplies.

Fig. 11-1

on the following page shows a block diagram of the Intelligent Platform Management Bus (IPMB) connections for the Katana

The Katana

752i system management features include two inter-integrated circuit (I2C)

752i.

interfaces, as follows:

• master/slave interface for 750GL communications

• master-only interface for accessing the temperature sensor readings and the two IPMI

read-only memory (ROM) devices

11-2

Katana®752i User’s Manual 10006024-04

IPMI Controller: SMB/IPMI Overview

IPMB (SCL, SDA, PWR)

Katana752i

MV64460

IPMI Microcontroller

IPMI

Bootcode

ROM

IPMI

Bootloader

and FRU

ROM

Voltage

Monitor

Reset

A-to-D 1

A-to-D 2

A-to-D 3

A-to-D 4

A-to-D 5

A-to-D 6

5 V

3.3 V

2.5 V

1.8 V (optional) CPU Core

GPIO[0:23]

1.25V

Timer Out

IPMI_OUT

IPMI Power

I2C #2

Temp

Sensor

Temp

Sensor

I2C #1

MV1_port_sel

Figure 11-1: IPMB Connections Block Diagram

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11-3

IPMI Controller: I/O Interface

I/O INTERFACE

The Zircon PM provides 24 user-definable input/output (I/O) pins. The following table shows how the Katana

Table 11-1: Zircon PM General Purpose I/O Pin Functions

752i implements these pins.

Zircon PM Pin: Signal Name: Function:

GPIO0 TEMP1_OS unused GPIO1 TEMP2_OS unused GPIO[2:3] – unused GPIO4 750GL1_IPMI_RST_R* active low IPMI reset input from 750GL

GPIO5 – unused GPIO6 IPMI_TIMEROUT_D unused GPIO7 – unused GPIO8 POST_FAULT active high input that signals a system

GPIO9 – unused GPIO10 I2C_holdoff active high input that signals Zircon PM off

GPIO11 750GL1_WD_LATCH active high input that signals a watchdog

GPIO12 – unused GPIO13 HS_FAULT_R* active low output that shuts power down

GPIO14 – unused GPIO[15:19] GA[4:0] Geographical Address inputs from J2

GPIO20 – unused GPIO[21:23] 750GL_TEMP_INT* unused

processor

firmware error

C bus

the #1 I

expiration event on 750GL processor

to the board via the Hot Swap controller

connector

11-4

Katana®752i User’s Manual 10006024-04

IPMI Controller: I2C Interfaces

In addition to the General Purpose I/O, there are six analog-to-digital (A2D) input pins that are used for sensing the various power supplies on the board. The following table describes the Katana

Table 11-2: Zircon PM Analog-to-Digital Input Pin Functions

752i implementation of these pins.

Zircon PM Pin: Signal Name:

A2D1 MON_PMC_3_3V 2.0V connects to the 3.3V PTMC power supply A2D2 MON_CPU_CORE 1.5V connects directly to the 750GL core power

A2D3 1_8V 1.8V connects directly to the 1.8V power supply A2D4 MON_2_5V 1.95V connects to the 2.5V power supply via a

A2D5 MON_3_3V 2.0 connects to the 3.3V power supply via a

A2D6 MON_5V 1.88V connects to the 5V power supply via a

1. The A2D inputs on the Zircon PM have a maximum input voltage rating of 2.5V, which is the A2D power supply voltage. Therefore, any sensed voltage that has a value greater than 2.5V must be divided down.

Nominal Voltage: Function:

supply

resistor divider network

I2C INTERFACES

The Zircon PM controller supports three I2C interfaces. Port 0 is a master/slave interface which connects to the public IPMB. Port 1 is a master/slave interface which connects to the

C bus for the MV64460. Port 2 is a master-only interface for accessing the inlet/outlet

temperature sensors and the two IPMI bootloader and boot code ROM devices.

Note: The Zircon PM device must be held in reset when the I2C Port 2 master-only interface is being used by the

750GL processor to access the serial EEPROM devices.

The MV64460 system controller can master Port 2 while the Zircon PM is in reset. This allows for access to the IPMI serial EEPROMs, which is useful for programming the Zircon PM application code. An alternate method for accessing the IPMI serial EEPROMs from the MV64460 is to use IPMI commands on I2C Port 1.

The MV64460 can master Port 1 to send IPMI requests and receive responses from the Zircon PM. All IPMI commands supported on the public IPMB are also supported on the private IPMB.

According to the IPMB specification, IPMI devices must use I IPMB. All IPMI messages overlay the I

C Master Write data, including the I2C command

C Master Write cycles on the

byte. Using this format, the first byte of an IPMI message transmitted on the bus is also the

C command byte.

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11-5

IPMI Controller: IPMI Message Protocol

The PICMG 2.9 specification defines addressing on the public and private IPMBs. It defines the slave addresses assigned to the chassis, power supplies, and peripheral boards based on geographical addressing. on its geographical address.

Table 11-3: IPMB Slave Addresses

Table 11-3 lists the slave address of each peripheral board, based

Geographical Address [0:4]

0 disabled 16 D0 1 B017D2 2 B218D4 3 B419D6 4 B620D8 5 B821DA 6BA22DC 7BC23DE 8BE24E0 9C025E2 10 C4 26 E4 11 C6 27 E6 12 C8 28 E8 13 CA 28 EA 14 CC 30 EC 15 CE 31 disabled

IPMB Address (Hex)

IPMI MESSAGE PROTOCOL

The IPMI message protocol is designed to be robust and support many different physical interfaces. The Zircon PM supports IPMI messages over the IPMB interface. Messages are defined as either a request or a response, as indicated by the least significant bit in the Network Function Code of the message. sage.

Table 11-4: Format for IPMI Request Message

Geographical Address [0:4]

Table 11-4 shows the format of an IPMI request mes-

IPMB Address (Hex)

11-6

Byte: Bits:

7: 6: 5: 4: 3: 2: 1: 0: 1 2

netFn rsLUN

3 4 5

Katana®752i User’s Manual 10006024-04

rqSeq rqLUN

rsSA

Checksum

rqSA

IPMI Controller: IPMI Message Protocol

Byte: Bits:

7: 6: 5: 4: 3: 2: 1: 0: 6 7:N N+1

The first byte contains the responder’s Slave Address, rsSA. The second byte contains the Network Function Code, netFn, and the responder’s Logical Unit Number, rsLUN. The third byte contains the two’s-complement checksum for the first two bytes. The fourth byte contains the requester’s Slave Address, rqSA. The fifth byte contains the requester’s Sequence Number, rqSeq, and requester’s Logical Unit Number, rqLUN. The Sequence number may be used to associate a specific response to a specific request. The sixth byte contains the Command Number. The seventh byte and beyond contain parameters for specific commands (if required). The final byte is the two’s-complement checksum of all of the message data after the first checksum.

Command

Data

Checksum

An IPMI response message (see difference is that the seventh byte contains the Completion Code, and the eighth byte and beyond hold data received from the controller (rather than data to send to the controller). Also, the Slave Address and Logical Unit Number for the requester and responder are swapped.

Table 11-5: Format for IPMI Response Message

Byte: Bits:

7: 6: 5: 4: 3: 2: 1: 0: 1 2 3 4 5 6 7 8:N N+1

Table 11-5) is similar to a IPMI request message. The main

rqSA

netFn rqLUN

Checksum

rsSA

rsSeq rsLUN

Command

Completion Code

Data

Checksum

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11-7

IPMI Controller: IPMI Message Protocol

IPMI Network Function Codes

All IPMI messages contain a Network Function Code field, which defines the category for a particular command. Each category has two codes assigned to it–one for requests and one for responses. The code for a request has the least significant bit of the field set to zero, while the code for a response has the least significant bit of the field set to one. lists the network function codes (as defined in the IPMI specification) used by the Zircon PM.

Table 11-6: Network Function Codes

Hex Code Value(s): Name: Type: Description:

00, 01 Chassis chassis device

02, 03 Bridge bridge

04, 05 Sensor/

Event

06, 07 App application

08, 09 Firmware firmware transfer

0A, 0B Storage non-volatile storage

0C-2F Reserved – reserved: 36 network functions (18 pairs) 30-3F OEM – vendor specific: 16 network functions (8

requests/responses

sensor and event requests/responses

requests/responses

Table 11-6

00 = command/request, 01 = response: common chassis control and status functions

02 = request, 03 = response: message contains data for bridging to the next bus. Typically, the data is another message, which also may be a bridging message. This function is only present on bridge nodes.

04 = command/request, 05 = response: for configuration and transmission of Event Messages and system Sensors. This function may be present on any node.

06 = command/request, 07 = response: message is implementation-specific for a particular device, as defined by the IPMI specification

firmware transfer messages match the format of application messages, as determined by the particular device

may be present on any node that provides nonvolatile storage and retrieval services

pairs). The vendor defines functional semantics for cmd and data fields. The cmd field must hold the same value in requests and responses for a given operation to support IPMI message handling and transport mechanisms. The controller’s Manufacturer ID value identifies the vendor or group.

11-8

Katana®752i User’s Manual 10006024-04

IPMI Controller: IPMI Message Protocol

IPMI Completion Codes

All IPMI response messages contain a hexadecimal Completion Code field that indicates the status of the operation. cation) used by the Zircon PM.

Table 11-7: Completion Codes

Code: Description:

Generic Completion Codes 00, C0-FF 00 Command completed normally C0 Node busy–command could not be processed because command-processing

C1 Invalid command–indicates an unrecognized or unsupported command C2 Command invalid for given LUN C3 Time-out while processing command, response unavailable C4 Out of space–command could not be completed because of a lack of storage

C5 Reservation canceled or invalid Reservation ID C6 Request data truncated C7 Request data length invalid C8 Request data field length limit exceeded C9 Parameter out of range–one or more parameters in the data field of the Request

CA Cannot return number of requested data bytes CB Requested sensor, data, or record not present CC Invalid data field in Request CD Command illegal for specified sensor or record type CE Command response could not be provided CF Cannot execute duplicated request–for devices that cannot return the response

D0 Command response could not be provided, SDR Repository in update mode D1 Command response could not be provided, device in firmware update mode D2 Command response could not be provided, BMC initialization or initialization

D3 Destination unavailable–cannot deliver request to selected destination. (This

D4 Cannot execute command, insufficient privilege level D5 Cannot execute command, parameter(s) not supported in present state FF Unspecified error

Table 11-7 lists the Completion Codes (as defined in the IPMI specifi-

resources are temporarily unavailable

space required to execute the given command operation

are out of range. This is different from Invalid data field code (CC) because it indicates that the erroneous field(s) has a contiguous range of possible values.

returned for the original instance of the request. These devices should provide separate commands that allow the completion status of the original request to be determined. An Event Receiver does not use this completion code, but returns the 00 completion code in the response to (valid) duplicated requests.

agent in progress

code can be returned if a request message is targeted to SMS, but receive message queue reception is disabled for the particular channel.)

10006024-04 Katana®752i User’s Manual

11-9

IPMI Controller: IPMI Message Protocol

Code: Description: (continued)

Device-Specific (OEM) Codes 01-7E 01-7E Device specific (OEM) completion codes–command-specific codes (also specific

Command-Specific Codes 80-BE 80-BE Standard command-specific codes–reserved for command-specific completion

Zircon PM IPMI Commands

The Zircon PM peripheral management controller supports IPMI commands to query board information and to control the behavior of the board. These commands provide a means to:

• identify the controller

• reset the controller

• return the controller’s self-test results

for a particular device and version). Interpretation of these codes requires prior knowledge of the device command set.

codes (described in this chapter)

• read and write the controller’s SROMs

• read the temperature, voltage, and watchdog sensors

• get specific information, such as thresholds, for each sensor

• read and write the Field Replaceable Unit (FRU) data

• reserve and read the Sensor Data Record (SDR) repository

• configure event broadcasts

• bridge an IPMI request to the public IPMB and return the response

• read and write the controller’s general-purpose I/O (GPIO)

• configure heartbeat broadcasts

Table 11-8 lists the IPMI commands supported by the Zircon PM along with the hexadecimal

values for each command’s Network Function Code (netFn), Logical Unit Number (LUN), and Command Code (Cmd).

Table 11-8: Zircon PM IPMI Commands

Command: netFn: LUN: Cmd:

Set Event Receiver Sensor/Event 04, 05 00 00 Get Event Receiver Sensor/Event 04, 05 00 01 Platform Event (Transmit Only) Sensor/Event 04, 05 00 02 Get Device SDR Information Sensor/Event 04, 05 00 20

11-10

Katana®752i User’s Manual 10006024-04

Emerson 752I User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Regulatory Agency Warnings & Notices

Contents

Figures

Tables

Registers

Overview

COMPONENTS AND FEATURES

FUNCTIONAL OVERVIEW

ADDITIONAL INFORMATION

Product Certification

RoHS Compliance

Terminology and Notation

Technical References

Setup

ELECTROSTATIC DISCHARGE

KATANA®752I CIRCUIT BOARD

Identification Numbers

Connectors

Fuses

LEDs

KATANA®752I SETUP

Power Requirements

Environmental Requirements

TROUBLESHOOTING

Technical Support

Product Repair

Reset Logic

GENERAL OVERVIEW

RESET SOURCES

CompactPCI Reset Enable

Power Monitor

750GL Processor Reset

Processor

PROCESSOR OVERVIEW

Features

Physical Memory Map

PROCESSOR RESET

PROCESSOR INITIALIZATION

Hardware Implementation Dependent 0 Register

Hardware Implementation Dependent 1 Register

Hardware Implementation Dependent 2 Register

EXCEPTION HANDLING

EXCEPTION PROCESSING

CACHE MEMORY

L1 Cache

L2 Cache

JTAG/COP HEADERS

System Controller

OVERVIEW

CPU INTERFACE

SDRAM CONTROLLER

DEVICE CONTROLLER INTERFACE

INTERNAL (IDMA) CONTROLLER

TIMER/COUNTERS

PCI INTERFACE

PCI Configuration Space

PCI Identification

PCI Read/Write

PCI Interface Registers

DOORBELL REGISTERS

Outbound Doorbells

Inbound Doorbells

WATCHDOG TIMER

RESET

ON-CARD MEMORY

User Flash

SDRAM

EEPROMs

I2C INTERFACE

GPIO SIGNAL DEFINITIONS

CONSOLE SERIAL PORT

Device Bus PLD

RESET REGISTERS

INTERRUPT REGISTERS

PRODUCT IDENTIFICATION

PCI ENUMERATION