Datasheet UPC1935GR Datasheet (NEC)

BiCMOS

DA T A SHEET

INTEGRATED CIRCUIT

PC1935

µ

µ

µ µ

DC-DC CONVERTER CONTROL IC

DESCRIPTION

The µ PC1935 is a low-voltage input DC-DC converter control IC that can configure a three-output (step-up × 2, inverted

output × 1) DC-DC converter at an input voltage of 3, 3.3, or 5 V.

Because of its wide operating voltage range, this IC can also be used to control DC-DC converters using an AC adapter

for input.

FEATUR ES

Low supply voltage: 2.5 V (MIN.)

•

Operating voltage range: 2.5 to 20 V (breakdown voltage: 30 V)

•

Can control three output channels.

•

Timer latch circuit for short-circuit protection.

•

Ceramic capacitor with low capacitance (0.1

•

Dead times of channels 2 (step-up) and 3 (inverted output) can be set from external resistors. Dead time of channel 1

•

(step-up) is internally fixed to 85 %.

Soft start of each channel can be set independently.

•

Each channel can be turned ON/OFF independently.

•

ORDERING INFORMATION

Part Number Package

PC1935GR 16-pin plastic TSSOP (5.72 mm (225))

µ

F) can be used for short-circuit protection.

µ

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. G13418EJ3V0DS00 (3rd edition)
Date Published March 2000 NS CP (K)
Printed in Japan

The mark ★ shows major revised points.

1998

PC

BLOCK DIAGRAM

µ

µ

µ µ

1935

DTC3I

Channel 3: for inversion

l3

FB

3

OUT

DTC

3

2

Channel 2: for step-up

I

l2

FB

2

OUT

16 15 14 13 12 11 10 9

–
+

Internal
fixed
voltage

–
–+
+

–
+

Internal
fixed
voltage

+
–

Internal
fixed
voltage

+
–
+

Reference

voltage
section

Oscillation
section

Soft start select switch

Timer latch for
short-circuit
protection section

–
+

Internal
fixed
voltage

12 345 6 7 8

V

CC

V

REF

R

T

DLYGND I

I1

FB

1

2

OUT

1

Channel 1: for step-up

2

Data Sheet G13418EJ3V0DS00

PC

PIN CONFIGURATION (Top view)

16-pin plastic TSSOP (5.72 mm (225))

PC1935GR

••••

µµµµ

GND

OUT

V

V

REF

R

DLY

FB

µ

µ

µ µ

DTC

I

I3

FB

OUT

DTC

I

I2

FB

OUT

3

3

3

2

2

2

CC

T

I1

I

1

1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1935

PIN FUNCTIONS

Pin No. Symbol Function Pin No. Symbol Function

1VCCPower supply 9 OUT
2V

REF

Reference voltage output 10 FB
3RTFrequency setting resistor connection 11 I
4 GND Ground 12 DTC
5 DLY Short-circuit protection/channel 1 sof t

13 OUT

start capacitor connection
6II1Channel 1 error amplifier inverted input 14 FB
7FB1Channel 1 error amplifier output 15 I
8OUT1Channel 1 open-drain output 16 DTC

2

Channel 2 open-drain output

2

I2

3

I3

Channel 2 error amplifier output
Channel 2 error amplifier inverted input

2

Channel 2 dead time setting

3

Channel 3 open-drain output

Channel 3 error amplifier output
Channel 3 error amplifier inverted input

3

Channel 3 dead time setting

Data Sheet G13418EJ3V0DS00

3

µ

PC

µ

µ µ

1935

CONTENTS

1. ELECTRICAL SPECIFICATIONS................................................................................................................5

2. CONFIGURATION AND OPERATION OF EACH BLOCK....................................................................11

2.1 Reference V oltage Generator ...........................................................................................................................12

2.2 Oscillator ...........................................................................................................................................................12

2.3 Under Voltage Lock-out Circuit........................................................................................................................12

2.4 Error Amplifiers.................................................................................................................................................12

2.5 PWM Comparators............................................................................................................................................12

2.6 Timer Latch-Method Short Circuit Protection Circuit....................................................................................13

2.7 Output Circuit....................................................................................................................................................13

3. NOTES ON USE........................................................................................................................................14

3.1 Setting the Output Voltage ...............................................................................................................................14

3.2 Setting the Oscillation Frequency...................................................................................................................15

3.3 Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit..................................15

3.4 Connecting Unused Error Amplifiers..............................................................................................................16

3.5 ON/OFF Control.................................................................................................................................................17

3.5.1 Channel 1 (for step-up)............................................................................................................................17

3.5.2 Channel 2 (for step-up)............................................................................................................................18

3.5.3 Channel 3 (for inverted output)................................................................................................................19

3.6 Maximum Duty Limit.........................................................................................................................................20

3.7 Notes on Actual Pattern Wiring........................................................................................................................20

4. APPLICATION EXAMPLE......................................................................................................................... 21

4.1 Application Example.........................................................................................................................................21

4.2 List of External Parts........................................................................................................................................22

5. PACKAGE DRAWING................................................................................................................................23

6. RECOMMENDED SOLDERING CONDITIONS .......................................................................................24

4

Data Sheet G13418EJ3V0DS00

PC

1. ELECTRICAL SPECIFICATIONS

µ

µ

µ µ

1935

Absolute Maximum Ratings (unless otherwise specified, TA

Parameter Symbol Ratings Unit
Supply voltage V
Output voltage V
Output current (open drain output) I
Total power dissipation P
Operating ambient temperature T
Storage temperature T

CC

O

O

T

A

stg

====

25

C)

°°°°

30 V
30 V
21 mA

400 mW

–20 to + 85

–55 to + 150

°

C

°

C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum ratings are not exceeded.

Recommended Operating Conditions

Parameter Symbol MIN. TYP. MAX. Unit

O

OSC

CC

O

A

2.5 20 V
020V

20 mA

−

20

20 800 kHz

+

85

°

C

Supply voltage V
Output voltage V
Output current I
Operating temperature T
Oscillation frequency f

Caution The recommended operating range may be exceeded without causing any problems provided that the

absolute maximum ratings are not exceeded. However, if the device is operated in a way that exceeds
the recommended operating conditions, the margin between the actual conditions of use and the
absolute maximum ratings is small, and therefore thorough evaluation is necessary. The recommended
operating conditions do not imply that the device can be used with all values at their maximum values.

Data Sheet G13418EJ3V0DS00

5

µ

PC

µ

µ µ

1935

Electrical Characteristics (unless otherwise specified, TA = 25

C, VCC

°°°°

3 V, f

====

= 100 kHz)

OSC

Block Parameter Symbol Conditions MIN. TYP. MAX. Unit

Under
voltage

lock-out
section

Reference
voltage
section

section

Duty setting
section

Start-up voltage V
Operation stop voltage V
Hysteresis voltage V
Reset voltage (timer latch) V
Reference voltage V

CC (L-H)

CC (H-L)

H

CCR

REF

Line regulation REG
Load regulation REG
Temperature coefficient

OSC

f

setting accuracy

OSC

f

total stabilit y

Input bias current I
Channel 1 maximum duty D
Channel 1 soft start time t
Low-level threshold voltage V

∆
∆
∆

V
f
f

BD

MAX.

SS

TH (L)

OSC

OSC

IN

L

REF

REF

I

= 0.1 mA 1.57 V

REF

I

= 0.1 mA 1.5 V

REF

I

= 0.1 mA 30 70 mV

REF

I

= 0.1 mA 1.0 V

REF

I

= 1 mA 2.0 2.1 2.2 V

CC

≤

2.5 V≤V

0.1 mA≤I

/∆T−20 °C≤T

RT = 18 k

−

20 °C≤T

2.5 V≤V

20 V 2 12.5 mV

REF

≤

1 mA 1 7.5 mV

A

≤+

Ω−

A

≤+

CC

≤

20 V

85 °C, I

85 °C,

REF

= 0 A 0.5 %

20

−

30

(Channels 2 and 3 only) 1.0

DLY

C

= 0.1 µF50ms

Duty = 0 % (channels 1 and2)

+
+

85 %

1.2 V

Duty = 100 % (channel 3)

High-level threshold voltage V

TH (H)

Duty = 100 % (channel 2)

1.6 V

Duty = 0 % (channel 3)
Error
amplifier
section

Input threshold voltage V
Input bias current I
Open loop gain A
Unity gain f
Maximum output voltage (+)
Maximum output voltage (−)
Maximum sink current I

Output source current I
Output
section

Output ON voltage V

Rise time t

Fall time t
Short-circuit

Input sense voltage V
protection
section

UV sense voltage V

Source current on short-circuiting I

Delay time t
Overall Circuit operation current I

ITH

B

v

unity

OM

V

OM

V

Osink

Osource

OL

r

f

TH1

TH3

V

UV

OUV

DLY

CC

+

−

, V

0.285 0.3 0.315 V

−

100

+

VO = 0.3 V 70 80 dB
VO = 0.3 V 1.5 MHz
IO = −45 µA1.62V
IO = 45 µA 0.02 0.5 V
VFB = 0.5 V 0.8 1.4
VFB = 1.6 V
RL = 150
RL = 150
RL = 150

TH2

Channels 1 and 2 1.75 1.9 2.05 V

Ω
Ω
Ω

−

0.2 0.6 V

−

70

50 ns
50 ns

Channel 3 0.5 0.63 0.75 V

0.8 0.85 V

1.0 1.6 2.7

DLY

C

= 0.1 µF50ms

VCC = 3 V 1.8 3.1 5.1 mA

30 %Oscillation
50 %

µ

100 nA

µ
µ

45

µ

A

A
A

A

Caution Connect a capacitor of 0.01 to 10

PC1935 C

6

F to the V

µ

µ

µ µ

REF

pin.

2

4

Data Sheet G13418EJ3V0DS00

REF

= 0.01 to 10 F

µµ

Timing Charts (sequence operation of power application

1

FB

Channel 1

DLY

OUT

1

Channel 1 starts.

Data Sheet G13418EJ3V0DS00

Channel 2

→ channel 1 → channel 2 → channel 3)

OFF

FB

ON

2

DTC

2

7

OUT

Channel 3

OUT

2

Channel 2 starts.

3

OFF

ON

DTC

3

FB

3

Channel 3 starts.

OFF

ON

µ µ

µ

µ

PC1935

µ

PC

µ

µ µ

1935

Typical Characteristic Curves (unless otherwise specified, VCC = 3 V, f

PT vs T

A

0.5

(W)

0.4

T

312.5 °C/W

0.3

0.2

0.1

Total power dissipation P

0

0 01234525 50 75
Operating ambient temperature T

V

REF

vs T

2.13
I

REF

= 0 A

2.12

(V)

REF

2.11

100 125 150

A

(°C)

A

2.5

2.0

(V)

REF

1.5

1.0

0.5

Reference voltage V

0

1000

(kHz)

OSC

100

= 100 kHz, TA = 25

OSC

V

REF

I

REF

= 0 A

Supply voltage V

OSC

f

vs V

vs R

C) (Nominal)

°°°°

CC

CC

(V)

T

2.10

2.09

2.08

Reference voltage V

2.07

–25 0 25 50 75 100

Operating ambient temperature T

∆f

OSC

vs T

A

8

R

T

(%)

OSC

= 18 kΩ

4

0

–4

–8

Oscillation frequency accuracy ∆f

–25 0 25 50 75 100

Operational ambient temperature T

A

(°C)

A

(°C)

10

Oscillation frequency f

1

1 10 100

Timing resistance R

VOL vs I

T

(kΩ)

O

0.5

0.4

(V)

OL

0.3

0.2

0.1

Output ON voltage V

0

0 4 8 12 16 202 6 10 14 18

Output current I

O

(mA)

8

Data Sheet G13418EJ3V0DS00

µ

PC

µ

µ µ

1935

VOL vs T

0.4

A

D

MAX.

vs R

T

90

IO = 20 mA

(%)

(V)

OL

0.3

0.2

0.1

MAX.

80

70

60

Output ON voltage V

Channel maximum duty D

1.24

(V)

TH (L)

1.22

1.20

50

Timing resistance R

V

RT = 18 kΩ

TH (L)

vs T

T

(kΩ)

A

0

–25 0 25 50 75 100 1 10 100

Operating ambient temperature T

V

TH (H)

vs T

A

A

(°C)

1.64
RT = 18 kΩ

(V)

TH (H)

1.62

1.60

1.58

High-level threshold voltage V

1.56

–25 0 25 50 75 100 –25 0 25 50 75 100

Operating ambient temperature T

t

SS

vs C

DLY

A

(°C)

600

500

(ms)

SS

400

300

200

100

Channel soft start time t

0 0.2 0.4 0.6 0.8 1

DLY pin capacitor capacitance C

DLY

µ

( F)

1.18

Low-level threshold voltage V

1.16
Operating ambient temperature T

t

DLY

vs C

(ms)

600

DLY

DLY

500

400

300

200

100

0

Short-circuit protection circuit delay time t

0.2 0.4 0.6 0.8 1

DLY pin capacitor capacitance C

DLY

A

(°C)

µ

( F)

Data Sheet G13418EJ3V0DS00

9

PC

60

50

µ

µ

µ µ

Av, vs f

t

DLY

vs T

A

100

C

DLY

= 0.1 F

µ

80

φ

180

135

1935

40

(ms)

DLY

30

20

60

(dB)

v

40

Gain A

20

A

φ

v

Delay time t

10

0

–25 0 25 50 75 100 100 1 k 10 k 100 k 1 M 10 M

Operating ambient temperature T

I

CC

vs V

CC

A

(°C)

4

3

(mA)

CC

–20

(mA)

CC

0

Frequency f (Hz)

CC

vs T

A

I

5

4

3

2

2

1

Circuit operation I

0

0 5 10 15 20 25 30

Supply voltage V

CC

(V)

1

Circuit operation I

0

–25 0 25 50 75 100

Operating ambient temperature T

A

(°C)

90

φ

45

0

Phase (deg)

–45

–90

10

Data Sheet G13418EJ3V0DS00

PC

2. CONFIGURATION AND OPERATION OF EACH BLOCK

Figure 2-1 Block Diagram

µ

µ

µ µ

1935

FB

DTC

FB

DTC

FB

V

V

REF

Oscillation
section

7

1

6

I

I1

(common to each channel)

3

T

R

8

OUT

1

Error amplifier

0.3 V

12

2

10

2

11

I

I2

PWM
comparator

Output
section

9

OUT

2

Error amplifier

0.3 V

16

3

14

3

15

I

I3

PWM
comparator

Output
section

13

OUT

3

Error amplifier

0.3 V

2

Under voltage

PWM
comparator

Output
section

lock-out

CC

voltage

1

Reference

section

section

Dead time setting: 85 %

(internally fixed)

DLY

5

C

DLY

Soft start
select switch

SCP
comparator

1.9 V 0.63 V

SQ

Q

Q

1

2

4

GND

Q

Timer latch for
short-circuit
protection section

Data Sheet G13418EJ3V0DS00

11

µ

PC

µ

µ µ

2.1 Reference Voltage Generator

The reference voltage generator is comprised of a band-gap reference circuit, and outputs a temperature-compensated
reference voltage (2.1 V). The reference voltage can be used as the power supply for internal circuits, or as a reference
voltage, and can also be accessed externally via the V

2.2 Oscillator

REF

pin (pin 2).

1935

The oscillator self-oscillates if a timing resistor is attached to the R
inverted input pins (channel 1 and 2) or non-inverted input pin (channel 3) of the three PWM comparators to determine the
oscillation frequency.

2.3 Under Voltage Lock-out Circuit

The under voltage lock-out circuit prevents malfunctioning of the internal circuits when the supply voltage is low, such as
when the supply voltage is first applied, or when the power supply is interrupted. When the voltage is low, the three output
transistors are cut off at the same time.

2.4 Error Amplifiers

The non-inverted input pins of the error amplifiers E/A
threshold voltages are all 0.3 V (TYP.)). The circuits of the error amplifiers E/A
first stage of the error amplifier is a P-channel MOS transistor input.

2.5 PWM Comparators

The output ON duty is controlled according to the outputs of the error amplifiers and the voltage input to the Dead Time
Control pin (fixed internally for channel 1).

A triangular waveform is input to the inverted pin, and the error amplifier output and Dead Time Control pin voltage (fixed

1

, E/A2, and E/A3 are connected internally to 0.3 V (the input

T

pin (pin 3) . This oscilla tor waveform is i nput to the

1

, E/A2, and E/A3 are exactly the same. The

internally for channel 1) are input to the non-inverted pins of the PWM comparators for channel 1 and channel 2.
Therefore, the output transistor ON period is the period when the triangular waveform is lower than the error amplifier
output and Dead Time Control pin voltage (fixed internally for channel 1).

Channel 3 is the logical inverse of channel 1 and channel 2. Consequently, the triangular waveform is input to the non­inverted input pin, and the error amplifier output and Dead Time Control pin voltage are input to the inverted input pins of
the PWM comparator for channel 3. Therefore, the transistor ON period is the period when the triangular waveform is
higher than the error amplifier output and Dead Time Control pin voltage (refer to

12

Data Sheet G13418EJ3V0DS00

Timing Charts

).

µ

PC

µ

µ µ

2.6 Timer Latch-Method Short Circuit Protection Circuit

When the outputs of the converters for each channel drop, the FB outputs of the error amplifiers of those outputs go

1935

high (FB
lower than the timer latch input detection voltage (VTH = 0.63 V)), then the output of the SCP comparator goes low, and Q
goes off.

flip-flop. When the DLY pin voltage reaches the UV detection voltage (V
low, and the output stage of each channel is latched to OFF (refer to

FB output of channels 1 and 2, and SCP comparator input.

short-circuit protection circuit has operated.

2.7 Output Circuit

rating), and an output current of 21 mA (absolute maximum rating).

3

output goes low). If the FB output exceeds the timer latch input detection voltage (VTH = 1.9 V) (FB3 output goes

When Q

The logic of channels 1 and 2 is reverse to that of channel 3. Consequently, an inverter circuit is inserted between the

Make the power supply voltage briefly less than the reset voltage (V

The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum

1

turns OFF, the constant-current supply charges C

DLY

via the DLY pin. The DLY pin is internally connected to a

UV

= 0.8 V (TYP.)), the output Q of the flip-flop goes

Figure 2-1 Block Diagram

CCR

, 1.0 V TYP.) to reset the latch circuit when the

).

1

Data Sheet G13418EJ3V0DS00

13

µ

PC

µ

µ µ

1935

3. NOTES ON USE

3.1 Setting the Output Voltage

Figure 3-1 illustrates the method of setting the output voltage. The output voltage is obtained using the formula shown in
the figure.

The input threshold value of the error amplifier is 0.3 V (TYP.) for all the error amplifiers, E/A
Therefore, select a resistor value that gives this voltage.

Figure 3-1 Setting the Output Voltage

(1) When setting a positive output voltage using error amplifier E/A

1

V

OUT

(positive voltage)

R

1

R

2

V

OUT

6

C

NF

R

NF

7

0.3 V

= 1 +

E/A

1

R

0.3

R

2

1

1

, E/A2, and E/A3.

.

(2) When setting a positive output voltage using error amplifier E/A

R

V

OUT

(positive voltage)

R

1

R

2

V

OUT

= 1 +

11

C

NF

R

NF

E/A

10

0.3 V

1

0.3

R

2

2

.

2

14

Data Sheet G13418EJ3V0DS00

PC

(3) When setting a negative output voltage using error amplifier E/A3.

2

V

REF

R

1

15

C

R

2

V

OUT

(negative voltage)

V

OUT

= 1 +

NF

R

NF

14

R

2

0.3

R

1

0.3 V

R
R

E/A

2
1

3

V

REF

µ

µ

µ µ

1935

3.2 Setting the Oscillation Frequency

Choose R

T

according to the oscillation frequency (f

Characteristics Curves f

OSC

OSC

) vs timing resistor (RT) characteristics (refer to

vs R

T

). The formula below (3-1) gives an approximation of f

OSC

. However, the result of

Typical

formula 3-1 is only an approximation, and the value must be confirmed in actual operation, especially for high-frequency
operation.

OSC

f

[Hz] ≅ 1.856 x 109/RT[Ω] (3-1)

3.3 Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit

The timer latch short-circuit protection circuit operates when the error amplifier outputs of channel 1 or channel 2 (pin 7
and 10) exceed approximately 1.9 V, or when the error amplifier output of channel 3 (pin 14) goes below approximately

0.63 V, and cuts off the output. However, if the rise of the power supply voltage is fast, or if there is noise on the DLY pin
(pin 5), the latch circuit may malfunction and cut the output off.

To prevent this, keep the wiring impedance between the DLY pin and the GND pin (pin 4) low, and avoid applying noise
to the DLY pin.

Data Sheet G13418EJ3V0DS00

15

PC

3.4 Connecting Unused Error Amplifiers

µ

µ

µ µ

1935

When the unused circuit of the three control circuits provided internally is error amplifier E/A
a way as to make sure that the output of the error amplifier is low. When the unused circuit is error amplifier E/A

2

, connect the circuit in such

3

, connect
the circuit in such a way as to make sure that the output of the error amplifier is high. In the case of error amplifier E/A1,
the Dead Time Control pin is fixed internally, so be sure to always use this amplifier.

Figure 3-2 shows examples of how to connect unused error amplifiers.

Figure 3-2 Examples of Connecting Unused Error Amplifiers

(1) Error amplifier E/A

2

V

REF

11

E/A

10

0.3 V

12

DTC

2

2

2

(2) Error amplifier E/A

2

V

REF

15

E/A

3

14

0.3 V

16

DTC

3

3

16

Data Sheet G13418EJ3V0DS00

PC

3.5 ON/OFF Control

3.5.1 Channel 1 (for step-up)

µ

µ

µ µ

1935

The ON/OFF signal control method of the output oscillation of channel 1 is to input the ON/OFF signal from ON

1

as
shown in Figure 3-3. For channel 1, soft start or timer latch (SCP) is internally selected. Soft start is executed when the
first start signal is input. When the end of soft start is detected, the soft start select switch is turned OFF and the timer
latch circuit operates.

Figure 3-3 ON/OFF Control (channel 1 for step-up)

V

O1

FB

R

11

I

I1

R

12

–
+

Error amplifier

0.3 V

1

SCP comparator
(common to each channel)

+
–

Q

1

0.63 V

V

REF

R
Dead time
setting: 85 %
(internally fixed)

Q

11

C

DLY

1

Oscillation section

SW

(common to each channel)

+
+
–

To output stage

PWM comparator

DLY

ON

(Converter
output
voltage)

D

11

1

(1) When ON

11

Q

: ON → DLY pin: Low level → Output duty of PWM comparator: 0 %

11

D

: ON → I

(2) When ON

Q

: OFF → C

11

D

: OFF → II1 pin: Low level → FB1 output: High level

11

(3) When ON

11

Q

: ON → DLY pin: Low level (Nothing happens because SW is OFF.)

is high: OFF status

1

I1

pin: High level → FB1 output: Lo w level

1

is low: ON status (start up)

is charged in the sequence of [V

DLY

goes high again after start up (SW: OFF): OFF status

1

→ R1 → SW → DLY pin → C

REF

] → Soft start

DLY

D11: ON → II1 pin: High level → FB1 output: Lo w level → PWM comparator output duty: 0 %

O1

Converter output voltage (V

→

Caution Even if start up is executed by making ON

) drops.

low again afte r (3), soft sta rt is n ot executed b ecause the

1

soft start select switch (SW) remains OFF. To execute soft start of channel 1 again, drop V
once.

Data Sheet G13418EJ3V0DS00

to 0 V

CC

17

PC

3.5.2 Channel 2 (for step-up)

µ

µ

µ µ

1935

The ON/OFF signal control method of the output oscillation of channel 2 is to input the ON/OFF signal from ON

shown in Figure 3-4. The PWM converter can be turned ON/OFF by controlling the level of the DTC

2

pin. However, it is

2

as

necessary to keep the level of the FB2 output low (the SCP comparator input high) so that the timer latch does not start
when the PWM converter is OFF. In this circuit example, the FB

2

output level is controlled by controlling the level of the I

pin.

Figure 3-4 ON/OFF Control (channel 2: step-up)

V

O2

D

21

(Converter
output
voltage)

R

21

I

I2

–

R

22

+

0.3 V

V

REF

R

23

Error
amplifier

FB

2

SCP comparator

(common to each channel)

+
–

0.63 V

+
+
–

PWM comparator

DLY

Q

1

To output stage

C

DLY

I2

DTC

ON

2

(1) When ON

21

Q

: ON → DTC2 pin: Low level → Output duty of PWM comparator: 0 %

21

D

: ON → II2 pin: High level → FB2 output: Lo w level → SCP comparator output: High level → Timer latch stops.

(2) When ON

21

Q

: OFF → C21 is charged in the sequence of [V

is high: OFF status

2

is low: ON status

2

Q

21

R

24

C

21

2

REF

→ R23 → C21] → DTC2 pin voltage rises → Soft start

Oscillation section

(common to each channel)

D21: OFF → II2 pin: Low level → FB2 output: High level → SCP comparator output: Low level → Q1 is OFF

DLY

Charging C

→

Caution Keep the low-level voltage of the DTC

0.3 V or higher. The maximum voltage that is applied to the I
V

.

REF

starts (timer latch start).

pin within 1.2 V and the high-level voltage of the II2 pin at

2

pin must be equal to or lower than

I2

18

Data Sheet G13418EJ3V0DS00

PC

3.5.3 Channel 3 (for inverted output)

µ

µ

µ µ

1935

The ON/OFF signal control method of the output oscillation of channel 3 is to input the ON/OFF signal from ON

shown in Figure 3-5. The PWM converter can be turned ON/OFF by controlling the level of the DTC

3

pin. However, it is

3

as

necessary to keep the level of the FB3 output high so that the timer latch does not start when the PWM converter is OFF.
In this circuit example, the FB

3

output level is controlled by controlling the level of the II3 pin.

Because channel 3 supports an inverted converter, its PWM comparator logic is different from that of channels 1 and 2.

Figure 3-5 ON/OFF Control (channel 3: for inverted output)

V

REF

FB

3

SCP comparator

–
+

(common to each channel)

Error
amplifier

Oscillation section

(common to each channel)

+
–

0.63 V

–
–
+

PWM comparator

DLY

Q

1

To output stage

C

DLY

ON

R

31

I

I3

R

Q

33

32

–V

O3

0.3 V

(Converter
output voltage)

V

REF

Q

32

R

33

C

31

DTC

3

Q

31

R

34

3

(1) When ON

31

Q

: ON → Q32: ON → DTC3 pin: High level → Output duty of PWM comparator: 0 %

33

Q

: ON → II3 pin: Low level → FB3 output: High level → SCP comparator output: High level → Q1 is ON.

(2) When ON

31

Q

: OFF → Q32 is OFF. → C31 is charged in the sequence of [V

33

: OFF → II3 pin: High level → FB3 output: Low lev el → SCP comparator output: Low level → Q1: OFF

Q

Caution Keep the high-level voltage of the DTC

is high: OFF status

3

Timer latch stops.

→

is low: ON status

3

Soft start

→

Charging C

→

DLY

starts (timer latch start).

REF

→ C31 → R34] → DTC3 pin voltage drops.

pin at 1.6 V or higher and the low-level voltage of the II3 pin

3

within 0.3 V. The maximum voltage that is applied to the II3 pin must be equal to or lower than V

REF

.

Data Sheet G13418EJ3V0DS00

19

µ

PC

µ

µ µ

3.6 Maximum Duty Limit

Channel 1 is switched internally between Soft Start and Timer Latch. For this reason, the DTC voltage is fixed internally,

and the maximum duty is limited to 85%.

The DTC voltage for channel 2 and channel 3 can be set externally, so the maximum duty is not limited.

3.7 Notes on Actual Pattern Wiring

When actually carrying out the pattern wiring, it is necessary to separate control-related grounds and power-related
grounds, and make sure that they do not share impedances as far as possible. In addition, make sure the high-frequency
impedance is lowered using capacitors and other components to prevent noise input to the V

REF

pin.

1935

20

Data Sheet G13418EJ3V0DS00

PC

4. APPLICATION EXAMPLE

4.1 Application Example

Figure 4-1 shows an example circuit for obtaining ±5 V/50 mA and +12 V/50 mA from a +3 V power supply.

Figure 4-1 Chopper-Method/Inverting-Type Switching Regulator

µ

µ

µ µ

1935

COM

= +3 V

IN

V

CH2

= +5 V

= 50 mA

O2

O

I

V

21

D

L2147

= −5 V

100 pF

33

C

32

R

54 kΩ

9

16 15 14 13 12 11 10

312

R

20 kΩ

310

R

100 pF

33

VR

2

OUT

2

FB

I2

I

2

DTC

3

OUT

3

FB

I3

I

3

DTC

CH3

31

D

470 Ω

O3

V

10 kΩ

F

µ

C2168

21

Q

H

µ

28

R

21

R

22

211

C

R

68 Ω

22

Q

23

100 pF

C

470 Ω

29

22

R

47 kΩ

27

R

150 Ω R

F

µ

1

COM

212

R

20 kΩ

100 pF

23

Q

210

7.5 kΩ

R

20

kΩ

23

2.4

kΩ

1 kΩ

VR

F

F

F

F

µ

1

24

C

µ

µ

1

1

3300 pF

F

µ

1

213

30 kΩ

R

1SS220

22

D

µ

1

311

R

32

Q

33

C

C3168

32

C

10 Ω

39

R

20 Ω

313

3300 pF

R

31

R

20 kΩ

F

µ

H

µ

31

47

L

33

Q

30

kΩ

= 50 mA

O

I

31

Q

PC1935

µ

CH1

1

OUT

1

FB

I1

I

GND DLY

T

R

REF

Vcc V

= +12 V

= 50 mA

O1

O

I

V

11

D

L1147

15

R

R11120 kΩ

1 2 3 4 5 6 7 8

F

µ

C1168

11

Q

19

10 Ω

T

R

13

C

16

R

150 Ω

13

C

3300 pF

3.9 kΩ

12

C

100

20 kΩ

13

Q

pF

12

D

14

Q

R

100 pF

12

R

2.4 kΩ

1SS220

20 kΩ

SS

C

17

7.5 kΩ

R

13

VR

0.1 pF

1 kΩ

112

10 kΩ

111

R

5.1 kΩ

214

10 kΩ

R

R

215

ON/OFF 2 ON/OFF 1

R

10 kΩ

H

µ

18

R

12

Q

470 Ω

14

R

110

30 kΩ

R

F

µ

2.2

25

C

26

VR

25

R

24

R

24

Q

36

VR

5 kΩ

F

µ

12 kΩ

5.1 kΩ

0.1

0

F

µ

C

2.2

35

C

5 kΩ

35

R

12 kΩ

34

Q

34

R

10 kΩ

Data Sheet G13418EJ3V0DS00

36

Q

315

10 kΩ

R

ON/OFF 3

35

Q

38

R

5.1 kΩ

37

R

10 kΩ

314

R

5.1 kΩ

21

PC

4.2 List of External Parts

The list below shows the external parts.

Table 4-1 List of External Parts

Symbol Parameter Function Part number Maker Remark

11

C

11

D

11

L

11

Q

12

Q

13

Q

12

D

14

Q

21

C

21

D

21

L

21

Q

22

Q

23

Q

22

D

24

Q

31

C

31

D

31

L

31

Q

32

Q

33

Q

34

Q

35

Q

36

Q

68 µ F Output capacitor 20SA68M SANYO OS-CON, SA series

Schottkey diode D1FS4 SHINDENGEN

47 µ H Choke inductor 636FY-470M TOKO D73F series

Switching transistor 2SD2403 NEC
Buffer transistor 2SA812 NEC
Buffer transistor 2SC1623 NEC
Switching diode 1SS220 NEC
Transistor for switch 2SK2158 NEC

68 µ F Output capacitor 20SA68M SANYO OS-CON, SA series

Schottkey diode D1FS4 SHINDENGEN

47 µ H Choke inductor 636FY-470M TOKO D73F series

Switching transistor 2SD2403 NEC
Buffer transistor 2SA812 NEC
Buffer transistor 2SC1623 NEC
Switching diode 1SS220 NEC
Transistor for switch 2SK2158 NEC

68 µ F Output capacitor 20SA68M SANYO OS-CON, SA series

Schottkey diode D1FS4 SHINDENGEN

47 µ H Choke inductor 636FY-470M TOKO D73F series

Switching transistor 2SB1572 NEC
Buffer transistor 2SA812 NEC
Buffer transistor 2SC1623 NEC
Transistor for switch 2SA812 NEC
Transistor for switch 2SC1623 NEC
Transistor for switch 2SC1624 NEC

µ

µ

µ µ

1935

Remarks 1. The capacitors that are not specified in the above list are multilayer ceramic capacitors.

2. The resistors that are not specified in the above list are 1/4W resistors.

22

Data Sheet G13418EJ3V0DS00

PC

5. PACKAGE DRAWING

16-PIN PLASTIC TSSOP (5.72 mm (225))

µ

µ

µ µ

1935

16

9

detail of lead end

F

G

R

P

L
S

1

A

A'

8

E

H

I

J

S

C

D

M

M

B

K

S

N

NOTE

Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.

Data Sheet G13418EJ3V0DS00

ITEM

MILLIMETERS

A

A'

B

C
D

E 0.09

F 1.01

G
H

I

J

K

L
M
N

P
R

S

S16GR-65-PJG-1

5.15±0.15

5.0±0.1

0.375 MAX.

0.65 (T.P.)
+0.06

0.24

−0.04
+0.06

−0.04
+0.09

−0.06

0.92

6.4±0.2

4.4±0.1

1.0±0.2

+0.055

0.145

−0.045

0.5

0.10

0.10

+5°

3°

−3°

0.25

0.6±0.15

23

µ

PC

µ

µ µ

6. RECOMMENDED SOLDERING CONDITIONS

Recommended solder conditions for this product are described below.
For details on recommended soldering conditions, refer to Information Document

Technology Manual” (C10535E)

For soldering methods and conditions other than those recommended, consult NEC.

Surface Mount Type

PC1935GR: 16-pin plastic TSSOP (5.72 mm (225))

µ

µ

µ µ

Soldering Method Soldering Conditions Symbol of Recommended

Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds MAX. (210 °C MIN.),

Number of times: 3 MAX.

VPS Package peak temperature: 215 °C, Time: 40 seconds MAX. (200 °C MIN.),

Number of times: 3 MAX.

Wave soldering

Soldering bath temperature: 260 °C MAX., Time: 10 seconds MAX., Number
of times: 1,
Preheating temperature: 120 °C MAX. (package surface temperature)

.

“Semiconductor Device Mounting

Conditions

IR35-00-3

VP15-00-3

WS60-00-1

1935

Caution Do not use two or more soldering methods in combination.

24

Data Sheet G13418EJ3V0DS00

PC

[MEMO]

µ

µ

µ µ

1935

Data Sheet G13418EJ3V0DS00

25

PC

[MEMO]

µ

µ

µ µ

1935

26

Data Sheet G13418EJ3V0DS00

PC

NOTES FOR BiCMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS

Note:

No connection for device inputs can be cause of malfunction. If no connection is provided to the
input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. Input levels of devices must be fixed high or low by using a pull-up or pull-

DD

down circuitry. Each unused pin should be connected to V
considered to have a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.

or GND with a resistor, if it is

µ

µ

µ µ

1935

3 STATUS BEFORE INITIALIZATION OF BiCMOS DEVICES

Note:

Power-on does not necessarily define initial status of device. Production process of BiCMOS does
not define the initial operation status of the device. Immediately after the power source is turned
ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

Data Sheet G13418EJ3V0DS00

27

µ

PC

µ

µ µ

[MEMO]

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

1935

M7 98. 8