Page 1
DATA SHEET
BiCMOS INTEGRATED CIRCUIT
µ
µ
PC1934
µ µ
DC-DC CONVERTER CONTROL IC
DESCRIPTION
The µ PC1934 is an IC that controls a low-voltage input DC-DC conver ter. This IC is suitable for an operation with 3-V,
3.3-V input or a lithium ion secondary battery input, because the minimum operation supply voltage is 2.5 V. Because of
its wide operating voltage range, it can also be used to control DC-DC converters that use an AC adapter for input.
FEATURES
Low supply voltage: 2.5 V (MIN.)
•
Operating voltage range: 2.5 to 20 V (breakdown voltage: 30 V)
•
Timer latch circuit for short-circuit protection.
•
Ceramic capacitor with low capacitance (0.1
•
Open drain outputs (Each of the outputs can be used to control a step-down converter, a step-up converter and an
•
inverted converter.)
Can control two output channels.
•
ORDERING INFORMATION
Part Number Package
PC1934GR-1JG 16-pin plastic SSOP (5.72 mm (225))
µ
PC1934GR-PJG 16-pin plastic TSSOP (5.72 mm (225))
µ
F) can be used for short-circuit protection.
µ
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G13567EJ3V0DS00 (3rd edition)
Date Published April 2000 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
1998
Page 2
BLOCK DIAGRAM
µ
µ
PC1934
µ µ
Channel 2
DTC
V
REF
16
DLY
15
I
N2
I
I2
14 13 12 11 10
FB
2
2
OUT
2
V
CC
9
MOS output
Reference
voltage
section
Timer latch for
short-circuit
protection section
–
+
E/A
2
–
–
+
PWM
2
MOS input
MOS input
Oscillation
section
MOS output
+
–
E/A
1
+
–
–
PWM
1
12 34 56 78
FB
R
T
C
T
I
I
N1
I1
1
DTC
1
1
Channel 1
GNDOUT
2
Data Sheet G13567EJ3V0DS00
Page 3
PIN CONFIGURATION (Top View)
16-pin plastic SSOP (5.72 mm (225))
••••
µµµµ
PC1934GR-1JG
16-pin plastic TSSOP (5.72 mm (225))
••••
µµµµ
PC1934GR-PJG
µ
µ
PC1934
µ µ
FB
DTC
OUT
GND
C
T
R
T
I
N1
I
I1
1
1
1
1
2
3
4
512
611
710
89
16
15
14
13
V
REF
DLY
I
N2
I
I2
FB
DTC
OUT
V
CC
2
2
2
PIN FUNCTIONS
Pin No. Symbol Function Pin No. Symbol Function
1CTFrequency setting capacitor connection 9 V
2RTFrequency setting resistor connection 10 OUT
3IN1Channel 1 error amplifier non-inverted
11 DTC
input
4II1Channel 1 error amplifier inverted input 12 FB
5FB1Channel 1 error amplifier output 13 I
6DTC1Channel 1 dead time setting 14 I
7OUT1Channel 1 open drain output 15 DLY Delay capacitor connection of short-
8 GND Ground 16 V
CC
I2
N2
Power supply
2
Channel 2 open drain output
2
Channel 2 dead time setting
2
Channel 2 error amplifier output
Channel 2 error amplifier inverted input
Channel 2 error amplifier non-inverted
input
circuit protection
REF
Reference voltage output
Data Sheet G13567EJ3V0DS00
3
Page 4
µ
µ
PC1934
µ µ
CONTENTS
1. ELECTRICAL SPECIFICATIONS................................................................................................................5
2. CONFIGURATION AND OPERATION OF EACH BLOCK....................................................................10
2.1 Reference V oltage Generator ...........................................................................................................................10
2.2 Oscillator ...........................................................................................................................................................10
2.3 Under Voltage Lock-out Circuit........................................................................................................................11
2.4 Error Amplifiers.................................................................................................................................................11
2.5 PWM Comparators............................................................................................................................................11
2.6 Timer Latch-Method Short Circuit Protection Circuit....................................................................................11
2.7 Output Circuit....................................................................................................................................................11
3. NOTES ON USE........................................................................................................................................12
3.1 Setting the Output Voltage ...............................................................................................................................12
3.2 Setting the Oscillation Frequency...................................................................................................................13
3.3 Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit..................................13
3.4 Connecting Unused Error Amplifiers ..............................................................................................................13
3.5 ON/OFF Control.................................................................................................................................................14
3.6 Notes on Actual Pattern Wiring........................................................................................................................14
4. APPLICATION EXAMPLE ......................................................................................................................... 15
4.1 Application Example.........................................................................................................................................15
4.2 List of External Parts........................................................................................................................................15
5. PACKAGE DRAWINGS..............................................................................................................................16
6. RECOMMENDED SOLDERING CONDITIONS .......................................................................................18
4
Data Sheet G13567EJ3V0DS00
Page 5
1. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (unless otherwise specified, TA
====
25
µ
µ
PC1934
µ µ
°°°°
C)
Parameter Symbol
Supply voltage V
Output voltage V
Output current (open drain output) I
Total power dissipation P
Operating ambient temperature T
Storage temperature T
µ
PC1934GR-1JG
CC
O
O
T
A
stg
417 400 mW
–20 to + 85
–55 to + 150
µ
PC1934GR-PJG Unit
30 V
30 V
21 mA
°
°
C
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions that ensure
that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter Symbol MIN. TYP. MAX. Unit
O
OSC
CC
O
A
2.5 20 V
020V
20 mA
−
20
20 1000 kHz
+
85
°
C
Supply voltage V
Output voltage V
Output current I
Operating temperature T
Oscillation frequency f
Caution The recommended operating range may be exceeded without causing any problems provided that the
absolute maximum ratings are not exceeded. However, if the device is operated in a way that exceeds
the recommended operating conditions, the margin between the actual conditions of use and the
absolute maximum ratings is small, and therefore thorough evaluation is necessary. The recommended
operating conditions do not imply that the device can be used with all values at their maximum values.
Data Sheet G13567EJ3V0DS00
5
Page 6
µ
µ
PC1934
µ µ
Electrical Characteristics (unless otherwise specified, TA = 25
°°°°
C, VCC
====
3 V, f
OSC
= 100 kHz)
Block Parameter Symbol Conditions MIN. TYP. MAX. Unit
Under
voltage
Lock-out
section
Reference
Voltage
section
Start-up voltage V
Operation stop voltage V
Hysteresis voltage V
Reset voltage (timer latch) V
Reference voltage V
Line regulation REG
Load regulation REG
Temperature coefficient
OSC
f
setting accuracy
section
Dead time
control
section
Error
Amplifier
section
OSC
f
total stabilit y
Input bias current I
Low-level threshold voltage V
High-level threshold voltage V
Input offset voltage V
Input offset current I
Input bias current I
Common mode input voltage range V
Open loop gain A
Unity gain f
Maximum output voltage (+)
Maximum output voltage (−)
Output sink current I
Output source current I
Output
section
Drain cutoff current I
Output ON voltage V
Rise time t
Fall time t
Short-circuit
Protection
section
Input sense voltage V
UV sense voltage V
Source current on short-circuiting I
Delay time t
Overall Circuit operation current I
CC (L-H)IREF
CC (H-L)IREF
H
CCR
REF
IN
L
REF
∆
/∆T−20 °C≤T
V
OSC
∆
f
OSC
∆
f
BD
TH (L)
TH (H)
IO
IO
B
IMC
v
unity
+
OM
V
−
OM
V
Osink
Osource
LEAK
OL
r
f
TH
UV
OUV
DLY
CC
= 0.1 mA 1.57 V
= 0.1 mA 1.5 V
REF
I
= 0.1 mA 30 70 mV
REF
I
= 0.1 mA 1.0 V
REF
I
= 1 mA 2.0 2.1 2.2 V
CC
≤
2.5 V≤V
0.1 mA≤I
RT = 11 kΩ, CT = 330 pF
−
20 °C≤T
2.5 V≤V
20 V 2 12.5 mV
REF
≤
1 mA 2 7.5 mV
A
≤+
A
≤+
CC
≤
20 V
85 °C, I
85 °C,
REF
= 0 A 0.5 %
−
15
−
30
+
15 %Oscillation
+
30 %
0.4 1.0
Duty = 100 % 1.2 V
Duty = 0 % 1.6 V
−
−
−
100
100
10
+
10 mV
+
100 nA
+
100 nA
00.4V
VO = 0.3 V 70 80 dB
VO = 0.3 V 1.5 MHz
IO = −45 µA1.62V
IO = 45 µA 0.02 0.5 V
VFB = 0.5 V 0.8 1.4 mA
VFB = 1.6 V
−
70
−
45
VO = 30 V 100
RL = 150
RL = 150
RL = 150
Ω
Ω
Ω
0.2 0.6 V
50 ns
60 ns
0.5 0.63 0.75 V
0.6 0.8 0.95 V
1.0 1.6 2.5
DLY
C
= 0.1 µF50ms
VCC = 3 V 1.4 2.2 3.7 mA
µ
A
µ
A
µ
A
µ
A
Caution Connect a capacitor of 0.01 to 10
PC1934
µ
6
µ
µ
F to the V
µ µ
REF
pin.
16
8
Data Sheet G13567EJ3V0DS00
C
REF
= 0.01 to 10 F
µ
Page 7
Timing Charts
Short-load Stop output
DTC
Channel 1 soft start Normal operation
1
Channel 1
C
T
FB
1
OUT
1
Data Sheet G13567EJ3V0DS00
V
TH
OFFON
DTC
2
Channel 2
C
T
FB
2
OUT
2
OFFON
DLY
Remark These timings are an example when the channel 1 output has been a short- load. The outputs of channel 1 and 2 are also stopped when a short-
V
UV
µ µ
µ
µ
PC1934
circuit protection circuit starts operation by detecting a short- load of channel 2.
7
Page 8
µ
µ
PC1934
µ µ
Typical Characteristic Curves (unless otherwise specified, VCC = 3 V, f
PT vs T
A
0.5
(W)
0.4
T
µ
PC1934GR-1JG
300 °C/W
0.3
µ
PC1934GR-PJG
0.2
312.5 °C/W
0.1
Total power dissipation P
0 25 50 75 100 125 150
Operating ambient temperature T
V
REF
vs T
A
2.13
I
REF
= 0 A
2.12
(V)
REF
2.11
A
(°C)
2.5
2.0
(V)
REF
1.5
1.0
0.5
Reference voltage V
1000
(kHz)
OSC
100
OSC
= 100 kHz, TA = 25
V
REF
I
REF
= 0 A
vs V
°°°°
C) (Nominal)
CC
012345
Supply voltage VCC (V)
f
OSC
vs R
T
CT = 150 pF
2.10
2.09
2.08
Reference voltage V
2.07
–25 0 25 50 75 100
Operating ambient temperature T
∆f
OSC
vs T
A
6
(%)
OSC
CT = 330 pF
RT = 10 kΩ
4
2
0
–2
–4
–6
Oscillation frequency accuracy ∆f
0–25 25 50 75 100
Operating ambient temperature T
A
(°C)
A
(°C)
10
CT = 1500 pF
Oscillation frequency f
1 10 1000100
Timing resistance R
VOL vs T
A
0.5
IO = 20 mA
0.4
(V)
OL
0.3
0.2
0.1
Output ON voltage V
0
0–25 25 7550 100
Operating ambient temperature TA (°C)
CT = 330 pF
T
(kΩ)
8
Data Sheet G13567EJ3V0DS00
Page 9
(V)
OL
0.5
0.4
0.3
0.2
VOL vs I
µ
µ
PC1934
µ µ
t
DLY
vs C
O
(ms)
600
DLY
DLY
500
400
300
200
0.1
Output ON voltage V
0
4 8 12 16 20
O
Output current I
Av, vs f
(mA)
φ
100
80
60
(dB)
v
40
20
Gain A
φ
A
v
0
–20
100 10 k1 k 10 M
Frequency f (Hz)
100
180
0
Short-circuit protection circuit delay time t
DLY pin capacitor capacitance C
ICC vs V
CC
4
DLY
1.00.80.60.40.2
( F)
µ
135
3
90
φ
45
0
Phase (deg)
(mA)
CC
2
1
–20
Circuit operation I
–90
1 M100 k
0 5 10 15 20 25
CC
Supply voltage V
(V)
30
Data Sheet G13567EJ3V0DS00
9
Page 10
2. CONFIGURATION AND OPERATION OF EACH BLOCK
Figure 2-1 Block Diagram
Oscillation
section
V
FB
FB
V
I
I
REF
6
1
5
1
4
I
I1
3
N1
11
2
12
2
13
I
I2
14
N2
16
Error amplifier
Error amplifier
PWM
comparator
PWM
comparator
Under voltage
lock-out
CC
Reference
9
voltage
section
section
DTC
DTC
Output
section
Output
section
µ
µ
PC1934
µ µ
2
T
R
1
C
T
7
OUT
10
OUT
1
2
SCP
DLY
comparator
Q
Q
1
2
0.63 V
15
DLY
C
Timer latch for
short-circuit
protection section
SQ
Q
8
GND
2.1 Reference Voltage Generator
The reference voltage generator is comprised of a band-gap reference circuit, and outputs a temperature-compensated
reference voltage (2.1 V). The reference voltage can be used as the power supply for internal circuits, or as a reference
voltage, and can also be accessed externally via the V
REF
pin (pin 16).
2.2 Oscillator
The oscillator self-oscillates if a timing resistor is attached to the RT pin (pin 2). Also, the oscillator outputs the
symmetrical triangular waveform if a timing capacitor is attached to the C
T
pin (pin 1). This oscillator wavefor m is input to
the non-inverted input pins of the two PWM comparators to determine the oscillation frequency.
10
Data Sheet G13567EJ3V0DS00
Page 11
µ
µ
PC1934
µ µ
2.3 Under Voltage Lock-out Circuit
The under voltage lock-out circuit prevents malfunctioning of the internal circuits when the supply voltage is low, such as
when the supply voltage is first applied, or when the power supply is interrupted. When the voltage is low, the two output
transistors are cut off at the same time.
2.4 Error Amplifiers
The circuits of the error amplifiers E/A
channel MOS transistor input. Be careful of the input voltage ranges (the common mode input voltage ranges are all 0 to
0.4 V (TYP.)).
2.5 PWM Comparators
The output ON duty is controlled according to the outputs of the error amplifiers and the voltage input to the Dead Time
Control pin.
A triangular waveform is input to the non-inverted pin, and the error amplifier output and Dead Time Control pin voltage
are input to the inverted pins of the PWM comparators. Therefore, the output transistor ON period is the period when the
triangular waveform is higher than the error amplifier output and Dead Time Control pin voltage (refer to
2.6 Timer Latch-Method Short Circuit Protection Circuit
When the conver ter outputs either a channel or both channels drop, the FB outputs of the error amplifiers of those
outputs go low. If the FB output goes lower than the timer latch input detection voltage (V
the SCP comparator goes low, and Q
When Q1 turns OFF, the constant-current supply charges C
flip-flop. When the DLY pin voltage reaches the UV detection voltage (V
1
and E/A2 are exactly the same. The first stage of the error amplifier is a P-
Timing Charts
TH
= 0.63 V)), then the output of
1
goes off.
DLY
via the DLY pin. The DLY pin is internally connected to a
UV
= 0.8 V (TYP.)), the output Q of the flip-flop goes
).
low, and the output stage of each channel is latched to OFF (refer to
Make the power supply voltage briefly less than the reset voltage (V
short-circuit protection circuit has operated.
2.7 Output Circuit
The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum
rating), and an output current of 21 mA (absolute maximum rating).
Figure 2-1 Block Diagram
CCR
, 1.0 V TYP.) to reset the latch circuit when the
).
Data Sheet G13567EJ3V0DS00
11
Page 12
µ
µ
PC1934
µ µ
3. NOTES ON USE
3.1 Setting the Output Voltage
Figure 3-1 illustrates the method of setting the output voltage. The output voltage is obtained using the formula shown in
the figure.
The common mode input voltage range of the error amplifier is 0 to 0.4 V (TYP.) for both the error amplifiers, E/A
E/A2. Therefore, select a resistor value that gives this voltage range.
Figure 3-1 Setting the Output Voltage
1
(1) When setting a positive output voltage using error amplifier E/A
R
1
R
4
V
V
OUT
(positive voltage) V
R
1
R
R
2
R
C
3
4
OUT
= 1 +
16
V
REF
4
NF
3
R
NF
5
••
R
2
R3 + R
E/A
1
REF
4
.
1
and
12
(2) When setting a negative output voltage using error amplifier E/A
16
V
REF
R
1
13
C
R
2
R
3
R
4
V
OUT
(negative voltage)
NF
14
R
NF
12
V
Data Sheet G13567EJ3V0DS00
E/A
2
R1R4−R2R
OUT
= •
R1 (R3+R4)
3
V
REF
2
.
Page 13
3.2 Setting the Oscillation Frequency
µ
µ
PC1934
µ µ
Choose R
T
according to the oscillation frequency (f
Characteristics Curves f
OSC
vs CT, R
). The formula below (3-1) gives an approximation of f
T
OSC
) vs timing resistor (CT, RT) characteristics (refer To
OSC
. However, the result of
Typical
formula 3-1 is only an approximation, and the value must be confirmed in actual operation, especially for high-frequency
operation.
OSC
f
[Hz] ≅ 0.375/(CT [F] x RT [Ω]) (3-1)
3.3 Preventing Malfunction of the Timer Latch-Method Short Circuit Protection Circuit
The timer latch short-circuit protection circuit operates when the error amplifier outputs (pin 5 and 12) goes below
approximately 0.63 V, and cuts off the output. However, if the rise of the power supply voltage is fast, or if there is noise on
the DLY pin (pin 15), the latch circuit may malfunction and cut the output off.
To prevent this, lower the wiring impedance between the DLY pin and the GND pin (pin 8), and avoid applying noise to
the DLY pin.
3.4 Connecting Unused Error Amplifiers
When one of the two control circuits is used, connect the circuit so that the output of the error amplifier of unused circuit
is high. Figure 3-2 shows examples of how to connect unused error amplifiers.
Figure 3-2 Examples of Connecting Unused Error Amplifiers
(1) Error amplifier E/A
16
V
REF
3
E/A
4
5
6
DTC
1
(2) Error amplifier E/A
16
V
REF
14
E/A
2
13
1
1
2
12
11
DTC
2
Data Sheet G13567EJ3V0DS00
13
Page 14
µ
µ
PC1934
µ µ
3.5 ON/OFF Control
The ON/OFF control method of the output oscillation is to input the ON/OFF signal from ON as shown in Figure 3-3.
The PWM converter can be turned ON/OFF by controlling the level of the DTC pin. However, it is necessary to keep the
level of the FB
the FB
output high so that the timer latch does not start when the PWM converter is OFF. In this circuit example,
output level is controlled by controlling the level of the II pin.
Figure 3-3 ON/OFF Control
V
O
V
REF
FB
SCP comparator
–
+
Error
(common to each channel)
amplifier
Oscillation section
(common to each channel)
+
–
0.63 V
–
–
+
DLY
Q
To output stage
PWM
comparator
ON Q
1
R
R
2
Q
3
R
Q
2
5
I
I
I
N
0.3 V
R
6
V
REF
R
3
C
1
DTC
1
R
4
(1) When ON is high: OFF status
Q1: ON → Q2: ON → DTC pin: High le v el → Output duty of PWM compa rator: 0 %
Q3: ON → II pin: Low le v el → FB output: High level → SCP comparator output: High level → Q is ON. → Timer latch stops.
3
(2) When ON
1
Q
: OFF → Q2 is OFF. → C1 is charged in the sequence of [V
3
Q
: OFF → II pin: High lev el → FB output: Low lev el → SCP comparator output: Low lev el → Q: OF F
is low: ON status
Charging C
→
DLY
starts (timer latch start).
REF
→ C1 → R4] → DTC pin v oltag e drop s. → Soft start
C
DLY
I
Caution Keep the high-level voltage of the DTC pin at 1.6 V or higher and the low-level voltage of the I
REF
within (R6/(R5+R6))
REF
than V
.
••••
V
. The maximum voltage that is applied to the II pin must be equal to or lower
pin
3.6 Notes on Actual Pattern Wiring
When actually carrying out the pattern wiring, it is necessary to separate control-related grounds and power-related
grounds, and make sure that they do not share impedances as far as possible. In addition, make sure the high-frequency
impedance is lowered using capacitors and other components to prevent noise input to the V
14
Data Sheet G13567EJ3V0DS00
REF
pin.
Page 15
4. APPLICATION EXAMPLE
4.1 Application Example
Figure 4-1 shows an example circuit for obtaining ±5 V/50 mA from a +3 V power supply.
Figure 4-1 Chopper-Method Step-up/Inverting-Type Switching Regulator
µ
µ
PC1934
µ µ
R
28
R
24
15 kΩ
2 kΩ
R
27
5 kΩ
23
R
12 kΩ
0.1
C
C
11
µ
F
R
12 kΩ
R
16
11
C
21
µ
F1
2 kΩ
18
10 kΩ
1
100 pF
R
µ
10 kΩ
18
F
R
26
V
REF
CTRTI
T
C
C
DLY IN
R
5.1 kΩ
18
R
12 kΩ
17
R
5 kΩ
DLY
µ
T
4.2 List of External Parts
The list below shows the external parts.
3300 pF
F0.1
12 kΩ
1316 15 14 912 11 10
II
2
2
FB2DTC2OUT
µ
PC1934
I
I1
N1
4123 8567
3300 pF
12 kΩ
VIN = 3 V COM
1
1
µ
C
C
2
10
µ
C
23
R
25
23
C
R
15
R
29
510 Ω
V
CC
2
GNDFB1DTC1OUT
1
F
F
D
470 Ω
24 kΩ
R
10 kΩ
21
Q
23
24
C
µ
F
68
214
L
R
R
210
10 Ω
211
R
11
212
µ
H
100
R
111
Q
23
100 Ω
Q
23
23
C
100 pF
R
21
47 kΩ
R
5 kΩ
CH2
V
O
= +5.0 V
I
O
= 50 mA
22
GND
D
11
Q
470 Ω
R
80 Ω
R
112
20 Ω
C
100 pF
13
113
10 kΩ
R
L
11
µ
H
100
113
C
14
µ
F
68
R
111
Q
11
19
Q
12
111
R
10 Ω
R
12
20 kΩ
11
R
5.1 kΩ
CH1
O
= −5.0 V
V
IO = 50 mA
GND
Table 4-1 List of External Parts
Symbol Parameter Function Part number Maker Remark
2
C
14
C
11
D
11
L
Q11, Q
13
Q
21
C
21
D
21
L
Q21, Q
23
Q
12
22
10 µ F Input stable capacitor 25SC10M SANYO OS-CON, SC series
68 µ F Output capacitor 20SA68M SANYO OS-CON, SA series
Schottkey diode D1FS4 SHINDENGEN
100 µ H Choke inductor 636FY-101M TOKO D73F series
Buffer transistor
µ
PA609T NEC Transistor array
Switching transistor 2SB1572 NEC
68 µ F Output capacitor 20SA68M SANYO OS-CON, SA series
Schottkey diode D1FS4 SHINDENGEN
100 µ H Choke inductor 636FY-101M TOKO D73F series
Buffer transistor
µ
PA609T NEC Transistor array
Switching transistor 2SD2403 NEC
Remarks 1. The capacitors that are not specified in the above list are multilayer ceramic capacitors.
2. The resistors that are not specified in the above list are 1/4W resistors.
Data Sheet G13567EJ3V0DS00
15
Page 16
5. PACKAGE DRAWINGS
16-PIN PLASTIC SSOP (5.72 mm (225))
16 9
18
A
detail of lead end
P
µ
µ
PC1934
µ µ
F
G
S
C
D
M
M
B
E
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
H
I
L
J
SN
K
ITEM
MILLIMETERS
A
5.2±0.3
B
0.475 MAX.
C
0.65 (T.P.)
D
0.22±0.8
E
0.125±0.075
F
1.565±0.235
G
1.44
H
6.2±0.3
I
4.4±0.2
J
0.9±0.2
K 0.17
L
M
N
+0.08
−0.07
0.5±0.2
0.10
0.10
5°±5°P
P16GM-65-225B-4
16
Data Sheet G13567EJ3V0DS00
Page 17
16-PIN PLASTIC TSSOP (5.72 mm (225))
µ
µ
PC1934
µ µ
16
9
detail of lead end
F
G
R
P
L
S
1
A
A'
8
E
H
I
J
S
C
D
M
M
B
K
N
S
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
A'
B
C
D
E 0.09
F 1.01
G
H
I
J
K
L
M
N
P
R
S
S16GR-65-PJG-1
5.15±0.15
5.0±0.1
0.375 MAX.
0.65 (T.P.)
+0.06
0.24
−0.04
+0.06
−0.04
+0.09
−0.06
0.92
6.4±0.2
4.4±0.1
1.0±0.2
+0.055
0.145
−0.045
0.5
0.10
0.10
+5°
3°
−3°
0.25
0.6±0.15
Data Sheet G13567EJ3V0DS00
17
Page 18
6. RECOMMENDED SOLDERING CONDITIONS
Recommended solder conditions for this product are described below.
µ
µ
PC1934
µ µ
For details on recommended soldering conditions, refer to Infor mation Document
Technology Manual” (C10535E)
For soldering methods and conditions other than those recommended, consult NEC.
Surface Mount Type
µ
µ
PC1934GR-1JG: 16-pin plastic SSOP (5.72 mm (225))
µ µ
µ
µ
PC1934GR-PJG: 16-pin plastic TSSOP (5.72 mm (225))
µ µ
Soldering Method Soldering Conditions Symbol of Recommended
Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds MAX. (210 °C MIN.),
Number of times: 3 MAX.
VPS
Wave soldering Soldering bath temperature: 260 °C MAX., Time: 10 seconds MAX.,
Caution Do not use two or more soldering methods in combination.
Package peak temperature: 215 °C, Time: 40 seconds MAX. (200 °C MIN.),
Number of times: 3 MAX.
Number of times: 1,
Preheating temperature: 120 °C MAX. (package surface temperature)
.
“Semiconductor Device Mounting
Conditions
IR35-00-3
VP15-00-3
WS60-00-1
18
Data Sheet G13567EJ3V0DS00
Page 19
NOTES FOR BiCMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS
Note:
No connection for device inputs can be cause of malfunction. If no connection is provided to the
input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. Input levels of devices must be fixed high or low by using a pull-up or pull-
DD
down circuitry. Each unused pin should be connected to V
considered to have a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
or GND with a resistor, if it is
µ
µ
PC1934
µ µ
3 STATUS BEFORE INITIALIZATION OF BiCMOS DEVICES
Note:
Power-on does not necessarily define initial status of device. Production process of BiCMOS does
not define the initial operation status of the device. Immediately after the power source is turned
ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet G13567EJ3V0DS00
19
Page 20
µ
µ
PC1934
µ µ
[MEMO]
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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