Page 1
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC1862
BURST LOCK CLOCK GENERATOR
The µPC1862 is an LSI incorporating a PLL circuit to generate nfSC clocks (fSC: color subcarrier frequency), ideal
for the processing of digital video signals as in extended definition television (EDTV) systems.
FEATURES
• VCO is incorporated.
• Horizontal and vertical sync separation circuits are incorporated (with output pins).
• Horizontal and vertical sync output pulses (TTL level)
• ACC amplifier and killer detector circuits are incorporated.
• 1/4 and 1/8 (1/2 × 1/4) frequency dividers are incorporated.
SC phase control circuits is incorporated.
•f
• Applicable to both NTSC and PAL systems.
• Possible to input burst gate pulse from external
ORDERING INFORMATION
Part number Package
µ
PC1862GS 36-pin plastic shrink SOP (300 mil)
Document No. S11431EJ3V0DS00 (3rd edition)
Date Published December 1997 N CP(K)
Printed in Japan
The information in this document is subject to change without notice.
The mark shows major revised points.
©
1991, 1996
Page 2
BLOCK DIAGRAM
µ
PC1862
SSI
CSO
VSSI
HDF
HDO
SGND
HKO
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
H
sync
SEP
Phase
shift
LPF
V
sync
SEP
ACC
DET
ACC
AMP
Color
Killer DET
1 2 3 4 5 6 7 8 9101112131415161718
SCO
CV
CC1
TINT
CIN
ACCF
CKF
CKO
Remark AFC : Automatic Frequency Control
ACC : Automatic Color saturation level Control
APC : Automatic Phase Control
HSOF2
HSOF1
H count down
V count down
APCF
COUT
HSOF3
APC
CGND
AFCF
SCOF1
SV
CC
AFC32fH VCOH DET
f
2
nfSC VCO
SCOF2
BGPE
SCOF3
NHSO
f
4
CV
CC2
CPO
CV
CC3
FIO
VCOO
VSO
N/P
DIVS
ESCI
Selecting divide ratio by DIVS pin Selecting TV transmission by N/P pin
DIVS Divide ratio N/P pin TV transmission
H 1/8 H PAL
Open EXT IN with pin 18 L NTSC
L 1/4
In PAL, only correspond 4fSC (DIVS = L).
2
Page 3
System Block Diagram
Application to Process of Digital Video Signal
Analog
video input
A/D converter
PC659A
µ
Gate array, etc
Processing of
digital video
Clock
generator
PC1862
µ
D/A converter
µ
PC665 (1ch.)
µ
PC664 (2ch.)
µ
PC662 (3ch.)
µ
PC1862
Analog
video output
3
Page 4
PIN CONFIGURATION (Top View)
36-pin plastic shrink SOP (300 mil)
µ
PC1862
SCO
CC1
TINT
CC2
CC3
1
2CV
3
4CIN
5ACCF
6CKO
7CKF
8COUT
9APCF
10CGND
11SCOF1
12SCOF2
13SCOF3
14CV
15CV
16VCOO
17DIVS
18ESCI
36
35 CSO
34
33 HDF
32 HDO
31 HKO
30 SGND
29 HSOF1
28 HSOF2
27 HSOF3
26 AFCF
25 SV
24 BGPE
23 NHSO
22 CPO
21 FIO
20 VSO
19 N/P
SSI
VSSI
CC
4
Page 5
ACCF : Chroma ACC Filter
AFCF : Horizontal Sync AFC Filter
APCF : Chroma APC Filter
BGPE : Burst Gate Pulse from External
CGND : Chroma GND
CIN : Chroma Input
CKF : Color Killer Filter
CKO : Color Killer Output
COUT : Chroma Output
CPO : Clamp Pulse Output
CSO : Composite Sync Output
CC1-CVCC3 : Chroma VCC
CV
DIVS : Divider Setting Input
ESCI : External Subcarrier Input
FIO : Field ID Output
HDF : Horizontal Sync Detect Filter
HDO : Horizontal Sync Detect Output
HKO : Horizontal Sync Killer Output
HSOF1-HSOF3 : 32f
H VCO Filter
NHSO : Negative Horizontal Sync Output
N/P : NTSC/PAL Mode Select
SCO : Subcarrier Output
SCOF1-SCOF3 : f
SC VCO Filter
SGND : Sync GND
SSI : Horizontal Sync Separation Input
CC : Sync VCC
SV
TINT : Tint Control
VCOO : VCO Output
VSO : Vertical Sync Output
VSSI : Vertical Sync Separation Input
µ
PC1862
5
Page 6
µ
PIN FUNCTIONS
Pin No. Symbol Pin Name Equivalent Circuit Function
1 SCO Sub Carrier Output Burst locked sub carrier output
5 kΩ
µ
400 A
DC voltage of a standard 2.9 V
2CVCC1 Chroma VCC1 Power supply for chroma signal
3 TINT Tint Control Tint control input (DC voltage)
3.3 V
5 kΩ
CV
CC3 (pin 15)
CV
CC3
(pin 15)
1
processing circuit (pin 1 to pin 18)
This power supply must be
isolated from the power supply
for sync processing circuit use.
This pin adjusts the tint of sub
carrier output (SCO pin).
PC1862
(1/12)
100 A
µ
15 kΩ
3
Internal bias voltage of a standard 2.5 V
6
Page 7
µ
PC1862
(2/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
4 CIN Chroma Signal Input Chroma signal input
4.0 V
10 kΩ
200 A
µ
Internal bias voltage of a standard 3.2 V
5 ACCF Chroma ACC Filter Pin for connecting filter of ACC
5 kΩ
CV
CC3
100 A
4
(pin 15)
CV
CC1
(pin 2)
µ
(Automatic Color Control)
detector
2 kΩ
5
DC voltage of a standard
6 CKO Color Killer Output Color Killer Detection output
200 Ω
1 kΩ
2 kΩ
CV
CC3
(pin 15)
6
Note
1.0 V
When Killer (without burst) signal:
Low level output
When color signal: High level
output
Note Chroma burst amplitude from pin 4: 150 mVp-p
7
Page 8
µ
PC1862
(3/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
CC3
7 CKF Chroma Killer Filter Pin for connecting filter of Color
1 kΩ
2 kΩ
500 Ω
14 kΩ
1 kΩ
7
CV
(pin 15)
3.6 V
killter detector
DC voltage of a standard
8 COUT Chroma Signal Automatic color controlled chroma
Output output
5 kΩ
µ
400 A
DC voltage of a standard 2.4 V
Note
2.2 V
CV
CC3
(pin 15)
For APC circuit
8
Note Chroma burst amplitude from pin 4: 150 mVp-p
8
Page 9
µ
PC1862
(4/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
9 APCF APC Filter Pin for connecting filter of APC
1 kΩ 12 kΩ
60 k
Ω
5 kΩ
65 kΩ
(Automatic Phase Control)
detector
4.5 kΩ
µ
1.8 V
Note
CV
CC2
(pin 14)
2.7 V
processing circuit (pin 1 to pin 18)
VCO
1 kΩ
9
DC voltage of a standard
10 CGND Chroma GND Ground for chroma signal
11 SCOF1 nfSC VCO Filter (1) Pin for connecting filter of nfSC
500 Ω
11
200 A
Bias voltage of a standard 3.0 V
Note Chroma burst amplitude from pin 4: 150 mVp-p
9
Page 10
µ
PC1862
(5/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
12 SCOF2 nfSC VCO Filter (2) Pin for connecting filter of nfSC
3.8 V
20 kΩ 1 kΩ
1 kΩ
CV
CC2
(pin 14)
VCO
200 A 200 A
Internal bias voltage of a standard 3.0 V
13 SCOF3 nfSC VCO Filter (3) Pin for connecting filter of nfSC
200 A
µ
DC voltage of a standard 2.9 V
14 CVCC2 Chroma VCC 2 Power supply for chroma signal
12
µµ
1 mA
CV
CC2
(pin 14)
13
VCO
processing circuit (pin 1 to pin 18)
This power supply must be
isolated from the power supply
for sync processing circuit use.
15 CVCC3 Chroma VCC 3 Power supply for chroma signal
processing circuit (pin 1 to pin 18)
This power supply must be
isolated from the power supply
for sync processing circuit use.
10
Page 11
µ
PC1862
Pin No. Symbol Pin Name Equivalent Circuit Function
16 VCOO VCO Output Burst locked VCO output
5 kΩ
µ
400 A
DC voltage of a standard 2.8 V
17 DIVS Dividing ratio selec- Divider ratio selection input
tion When 1/4: Low level input
25 kΩ
µµ
100 A 100 A
CVCC2
(pin 14)
16
CV
CC3
(pin 15)
When 1/8: High level input
When external dividing: Middle
level input
(6/12)
10 kΩ
18 ESCI External subcarrier External subcarrier input.
Input When no use (pin 17 is not middle
(External Divide) level): Low level input
18
17
5 kΩ
25 kΩ
16 kΩ
25 kΩ
16 kΩ
µ
100 A
16 kΩ
16 kΩ
CV
(pin 15)
2.5 V
22 kΩ
CC3
11
Page 12
µ
PC1862
(7/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
19 N/P NTSC/PAL selection NTSC/PAL system selection input
µ
100 A
CVCC3
(pin 15)
When NTSC system: Low level
input
When PAL system: High level
input
5 kΩ
19
16 kΩ
20 VSO Vertical Sync Output Negative polarity vertical sync
1 kΩ
21 FIO Field ID Output Odd/Even field ID output
1 kΩ
SVCC (pin 25)
40 kΩ
SVCC (pin 25)
40 kΩ
2.0 V
output
20
When Odd ID: Low level output
When Even ID: High level output
When a input is non-standard
signal, this pin outputs an
indefiniteness.
21
22 CPO Clamp Pulse Output Pedestal Clamp pulse (burst gate
1 kΩ
SVCC (pin 25)
pulse) output
40 kΩ
22
12
Page 13
µ
PC1862
(8/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
23 NHSO Negative Horizontal Negative polarity horizontal sync
Sync Output output
SVCC (pin 25)
1 kΩ
24 BGPE Burst Gate Pulse Burst gate pulse input
from External In inside burst gate pulse
5 kΩ
8 kΩ 5 kΩ 7 kΩ
25 SVCC Sync VCC Power supply for sync signal
2.5 kΩ
40 kΩ
SV
23
CC
(pin 25)
BGP
24
generation mode: Low level fix
In external burst gate pulse input
mode:
When Non-burst period: Middle
level input
When burst period: High level
input
processing circuit (pin 19 to pin
36)
This power supply must be
isolated from the power supply
for chroma processing circuit use.
13
Page 14
µ
PC1862
(9/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
26 AFCF AFC Filter Pin for connecting filter of
200 Ω
3.2 V
SV
CC
(pin 25)
horizontal AFC (Automatic
Frequency Control) detector
26
3 kΩ
30 kΩ
100 A
µ
Note
SVCC (pin 25)
27
3.2 V
VCO
300 Ω
1 kΩ
DC voltage of a standard
27 HSOF3 32fH VCO Filter (3) Pin for connecting filter of 32fH
1 mA
DC voltage of a standard 2.4V
28 HSOF2 32fH VCO Filter (2) Pin for connecting filter of 32fH
4.6 V
100 A
µ
Internal bias voltage of a standard 3.8 V
3.3 kΩ
SVCC (pin 25)
28
VCO
Note When only 0.3 Vp-p sync signal is input to pin 36
14
Page 15
µ
PC1862
(10/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
29 HSOF1 32fH VCO Filter (1) Pin for connecting filter of 32fH
VCO
29
Bias voltage of a standard 3.8 V
30 SGND Sync GND Ground for sync processing circuit
(pin 19 to pin 36)
31 HKO Horizontal Horizontal killer output (Open
Killer Output Corrector)
When No sync: High impedance
31
24 kΩ
output
When sync: Low level output
32 HDO Horizontal Sync Horizontal sync detection signal
Detection Output output
1 kΩ
SV
CC
32
(pin 25)
When No sync: High level output
When sync: Low level output
15
Page 16
Pin No. Symbol Pin Name Equivalent Circuit Function
33 HDF Horizontal Sync Pin for connecting filter of
Detection Filter Horizontal sync detector
1 kΩ
10 kΩ
H gate
pulse
SVCC (pin 25)
33
µ
PC1862
(11/12)
Bias voltage of a standard
34 VSSI Vertical Sync Vertical sync separation input pin
Separator Input
16 kΩ
20 kΩ
100 Ω
1 kΩ
30 kΩ
34
35 CSO Composite Sync Negative polarity composite sync
Separator Output output
1 kΩ
Note
5 kΩ
SVCC (pin 25)
35
4.1 V
SV
CC
(pin 25)
Note When only 0.3 Vp-p sync signal is input to pin 36
16
Page 17
µ
PC1862
(12/12)
Pin No. Symbol Pin Name Equivalent Circuit Function
36 SSI Horizontal Sync Horizontal sync separation input
Separator Input pin
16 kΩ
20 kΩ
100 Ω
1 kΩ
30 kΩ
36
5 kΩ
SV
CC
(pin 25)
17
Page 18
µ
PC1862
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise specified)
Parameter Symbol Ratings Unit
Supply voltage VCC 7V
Input signal voltage (Chroma signal) ei4 3Vp-p
Input signal voltage (H sync separation) ei36 3Vp-p
Input signal voltage (V sync separation) ei34 3Vp-p
Input signal voltage (EXT) ei18 VCC Vp-p
Tint control signal voltage ec3 VCC V
Output current IO –7 mA
Permissible package power dissipation PD 570 (TA = 75°C) mW
(when mounted on PCB)
Operating ambient temperature TA –10 to +75 °C
Storage temperature Tstg –40 to +125 °C
Caution Expose to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the
ratings could cause permanent damage. The parameters apply independently.
The device should be operated within the limits specified under DC and AC Characteristics.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol MIN. TYP. MAX. Unit
Supply voltage VCC 4.5 5.0 5.5 V
Input signal voltage (Chroma signal) ei4 150 mVp-p
Input signal voltage (H sync separation) ei36 1.0 Vp-p
Input signal voltage (V sync separation) ei34 1.0 Vp-p
Input signal voltage (EXT IN HIGH voltage) eiH18 2.0 V
Input signal voltage (EXT IN LOW voltage) eiL18 0.8 V
Divider selector voltage 1 (1/8) V17 (8) 4.8 V
Divider selector voltage 2 (1/4) V17 (4) 0.2 V
Tint control voltage V3 2.5 V
NTSC/PAL select voltage (PAL) V19P 4.5 V
NTSC/PAL select voltage (NTSC) V19N 0.5 V
18
Page 19
µ
PC1862
ELECTRICAL CHARACTERISTICS (at TA = 25±3 ° C, RH ≤ 70 %, VCC = 5 V, unless otherwise specified)
Chroma section
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply current ICC (C) VCC (C) = 5 V 17 21 25 mA
of chroma section No current on pin 2, 14 and 15
ACC amplitude ACC1 Fluctuation of chroma output level at +6 dB –2.0 0 +2.0 dB
characteristic 1 change of chroma input burst signal
(0 dB = 150 mVp-p)
ACC amplitude ACC2 Fluctuation of chroma output level at –20 dB –5.0 –1.0 +1.0 dB
characteristic 2 change of chroma input burst signal
(0 dB = 150 mVp-p)
Color killer set point eKS Input level at killer ON with chroma input burst –45 –39 –33 dB
sig. (0 dB = 150 mVp-p) being attenuated
Color residual of color killer eKR Residual level of chroma output in Killer ON - - 15 mVp-p
state when chroma input burst signal of
150 mVp-p is input
Chroma output level ECOUT Chroma output level when chroma input burst 1.1 1.3 1.5 Vp-p
signal of 150 mVp-p is input
Color killer output ECKOH (1) High level of color killer output at color killer 2.7 3.5 - V
High level (1) OFF
IOH = –400 µA
Color killer output ECKOH (2) High level of color killer output at color killer 3.5 4.0 - V
High level (2) OFF
IOH = –20 µA
Color killer output ECKOL Low level of color killer output at color killer ON - 0.2 0.4 V
Low level IOL = +2 mA
APC lock-in range fP Frequency pulled by APC with chroma input ±400 ±600 - Hz
burst frequency changed (fSC conversion)
VCO control sensitivity
Phase variable range
VCO output level eVCOO VCO output level when chroma input burst 1.0 1.3 1.6 Vp-p
fSC output level eSCO fSCO output level when chroma input burst 210 300 390 mVp-p
Divider select voltage
NTSC/PAL select voltage VN/PT fV = 60 Hz if VN/P < VN/PT 1.7 2.0 2.3 V
β
P Rate of variation of frequency when APC filter 8.0 10.0 12.0 Hz/mV
pin is changed from –0.025 V to +0.025 V
(fSC conversion)
θ
CONT Amount of phase shift when voltage of phase ±40 ±55 - deg
control pin is set at 2.5 V + 1 V
signal of 150 mVp-p is input
signal of 150 mVp-p is input
VDIVSL
VDIVSH
1/4 freq. division if VDIVS < VDIVSL
EXT IN with VDIVS : OPEN
1/8 freq. division if VDIVSH < VDIVS
fV = 50 Hz if VN/PT < VN/P
- - 0.5 V
4.5 - - V
19
Page 20
µ
Sync section
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply current ICC (1) VCC (1) = 5 V 12 15 18 mA
of Sync section No current on pin 25
DC level of H sync VSSI Voltage of pin 36 when connected to GND via 1.9 2.2 2.5 V
separation input 10 kΩ resistor
DC level of V sync VVSSI Voltage of pin 34 when connected to GND via 1.9 2.2 2.5 V
separation input 10 kΩ resistor
Sync separation output ECSOH1 High level of sync separation output when only 2.7 3.8 - V
High level (1) 0.3 Vp-p sync signal is input to pin 36
IOH = –400 µA
Sync separation output ECSOH2 High level of sync separation output when only 3.5 4.3 - V
High level (2) 0.3 Vp-p sync signal is input to pin 36
IOH = –20 µA
Sync separation output ECSOL Low level of sync separation output when only - 0.1 0.4 V
Low level 0.3 Vp-p sync signal is input to pin 36
IOL = +2 mA
HD output ENHSOH1 High level of synchronized HD output when 2.7 3.8 - V
High level (1) only 0.3 Vp-p sync signal is input to pin 36
IOH = –400 µA
HD output ENHSOH2 High level of synchronized HD output when 3.5 4.3 - V
High level (2) only 0.3 Vp-p sync signal is input to pin 36
IOH = –20 µA
HD output ENHSOL High level of synchronized HD output when - 0.1 0.4 V
Low level only 0.3 Vp-p sync signal is input to pin 36
IOL = +2 mA
VD output EVSOH1 High level of synchronized VD output when 2.7 3.8 - V
High level (1) only 0.3 Vp-p sync signal is input to pin 36
IOH = –400 µA
VD output EVSOH2 High level of synchronized VD output when 3.5 4.3 - V
High level (2) only 0.3 Vp-p sync signal is input to pin 36
IOH = –20µA
VD output EVSOL High level of synchronized VD output when - 0.1 0.4 V
Low level only 0.3 Vp-p sync signal is input to pin 36
IOL = +2 mA
Clamp output ECPOH1 High level of synchronized Clamp output when 2.7 3.8 - V
High level (1) only 0.3 Vp-p sync signal is input to pin 36
IOH = –400 µA
Clamp output ECPOH2 High level of synchronized Clamp output when 3.5 4.3 - V
High level (2) only 0.3 Vp-p sync signal is input to pin 36
IOH = –20 µA
Clamp output ECPOL High level of synchronized Clamp output when - 0.1 0.4 V
Low level only 0.3 Vp-p sync signal is input to pin 36
IOL= +2 mA
PC1862
20
Page 21
µ
PC1862
Parameter Symbol Condition MIN. TYP. MAX. Unit
Field ident. output EFIOH1 High level of synchronized Field ident. output 2.7 3.8 - V
High level (1) when only 0.3 Vp-p sync signal is input to pin 36
IOH = –400 µA
Field ident. output EFIOH2 High level of synchronized Field ident. output 3.5 4.3 - V
High level (2) when only 0.3 Vp-p sync signal is input to pin 36
IOH = –20 µA
Field idnet. output EFIOL High level of synchronized Field ident. output - 0.1 0.4 V
Low level when only 0.3 Vp-p sync signal is input to pin 36
IOL = +2 mA
H detection output EFIOH1 High level of asynchronized H detect output 2.7 3.8 - V
High level (1) without H sync input
IOH = –400 µA
H detection output EFIOH2 High level of asynchronized H detect output 3.5 4.3 - V
High level (2) without H sync input
IOH = –20 µA
H detection output EFIOL High level of synchronized H detect output - 0.1 0.4 V
Low level when only 0.3 Vp-p sync signal is input to pin 36
IOL= +2 mA
H sync lock-in range fHP Frequency range that can be pulled when only ±400 ±500 - Hz
0.3 Vp-p sync signal is input to pin 36 and H
sync frequency is varied (fSC conversion)
Horizontal VCO control
sensitivity pin is changed form 3.0 V to 3.4 V without H
Horizontal VCO free-run fHO Frequency difference of HD output from fH –100 –25 +50 Hz
frequency when H sync input is not applied
Pulse width of HD output PWNHSO Pulse width of synchronized HD output when 3.8 4.0 4.2
Pulse width of VD output PWVSO1 Pulse width of synchronized VD ODD - 6.0 - H
Pulse width of Clamp output PWCPO Pulse width of synchronized Clamp output when 3.4 3.6 3.8
Oscillation start voltage of VST Output voltage at HD when VCC is gradually - - 4.2 V
horizontal VCO increased from 0 V without H sync input
H killer output Low level EHKOL Low level of synchronized H killer output when - - 0.4 V
Burst gate input VBGPE1 Burst gate pulse input voltage when Clamp 1.6 1.9 2.0 V
Threshold level 1 voltage begins Low level is gradually increased
β
H Rate of variation of frequency when APC filter –1.6 –1.3 –0.9 Hz/mV
sync input (fSC conversion)
only 0.3 Vp-p sync signal is input to pin 36
PWVSO2
output when only 0.3 Vp-p sync
signal is input to pin 36
only 0.3 Vp-p sync signal is input to pin 36
only 0.3 Vp-p sync signal is input to pin 36
Change value of Chroma output
from 0 V without signal input
EVEN - 5.5 - H
µ
µ
s
Note
Note
s
Note H: Horizontal scanning period
21
Page 22
µ
PC1862
Parameter Symbol Condition MIN. TYP. MAX. Unit
Burst gate input VBGPE2 Burst gate pulse input voltage when Clamp 3.8 4.0 4.2 V
Threshold level 2 voltage begins High level is gradually
increased from VBGPE1 without signal input
Vertical free-running fV1 (50) Frequency ratio of HD output to VD output - fH/352 - Hz
frequency 1 H sync input: No signal
fV1 (60) Pin 33 input: VCC -fH/288 - Hz
V sync input: VCC
Vertical free-running fV2 (50) Same as fV1 with the following exception - fH/288 - Hz
frequency 2 fV2 (60) V sync input: GND - fH/240 - Hz
Vertical free-running fV3 (50) Same as fV1 with the following exception - fH/368 - Hz
frequency 3 fV3 (60) Pin 33 input: GND - fH/296 - Hz
Vertical free-running fV4 (50) Same as fV1 with the following exception - fH/272 - Hz
frequency 4
fV4 (60)
Pin 33 input: GND
V sync input: GND
-fH/232 - Hz
22
Page 23
TIMING CHARTS (Horizontal Period)
1 s
µ
Comp Video
Input
Comp Sync
Output
(CSO)
This delay is fixed by the application of pin 36.
HD Output
(NHSO)
4 s
µ
PC1862
Burst Signal
µ
CLAMP
Output
(CPO)
4 s
µ
This rising edge is cut by Comp Sync Output.
23
Page 24
24
TIMING CHARTS (Vertical Period)
Comp Video Input
HD Output
(NHSO)
CLAMP Output
(CPO)
VD Output
(VSO)
FIELD Output
(FIO)
<Odd Field>
Note
0.5 H
<Even Field>
6 H
Note
Comp Video Input
HD Output
(NHSO)
CLAMP Output
(CPO)
VD Output
(VSO)
FIELD Output
(FIO)
Note H: Horizontal scanning period
0.5 H
Note
5.5 H
Note
µ
PC1862
Page 25
µ
PC1862
CAUTION AT DESIGNING
Resonators
NEC evaluates µPC1862 using resonators which are shown below in design and development process.
If the different product is used as a resonator, electrical specification value described in this document is not assured.
And when connecting resonator to external circuit, there is need to consider temperature specification, voltage
fluctuation and product variation. In this case, normal operation is not assured in the application circuit including the
different product.
Use the resonators which are shown below when you design circuit.
H VCO resonator X1 : in application example circuit
32 f
X1 (PAL) : CSB500F2 (MURATA)
(NTSC) : CSB503F2 (MURATA)
SC VCO resonator X2
nf
X2 : HC-49/U (KINSEKI, µPC1860 adoption)
Reference data of 4f
Item NTSC for 4fSC NTSC for 8fSC PAL for 4fSC
Name HC-49/U
Frequency 14.31818 MHz 28.63636 MHz 17.34475 MHz
Overtone Order Fundamental (AT cut) Fundamental (BT cut) Fundamental (AT cut)
Operating Temperature –10 to +70°C
Frequency Permitted ±30 × 10
Tolerance (25±5°C)
Frequency Temperature ±30 × 10
Specification (to 25°C)
Equivalent Serial Resistance 50 Ω or less
Parallel Capacitance 7.0 pF or less
3rd harmonic standard 3rd harmonic frequency is over – 3rd harmonic frequency is over
SC, 8fSC VCO resonator (KINSEKI)
–6
–6
3fO (42.95454 MHz) + 7.5 kHz 3fO (53.203425 MHz) + 7.5 kHz
±50 × 10
±100 × 10
–6
–6
±30 × 10
±30 × 10
–6
–6
25
Page 26
Recommended pattern
µ
PC1862 generates system clock for synchronous signal processing and clock generate processing.
The
If the supply voltage, line placement and routing are not set appropriately that the µPC1862 cannot generate correct
system clock.
Though the recommended pattern is not shows in this document, note points shown below at designing.
1. For synchronous section and chroma section, each power supply must be isolated.
2. Lines to pin 9 to pin 13 should be as thick and short as possible.
3. Connect resonator as near IC as possible. Don’t put GND line between resonator pins for parasitism capacitance.
µ
PC1862
26
Page 27
APPLICATION CIRCUIT
5 V
1 kΩ
2SA1175
or
equivalent
39 kΩ
10 F
+
75 Ω 11
k Ω
Comp
video IN
4.7 F
100 k
Ω
++
Comp
sync OUT
100
kΩ
4.7
F
220
Ω
100 kΩ
220 Ω
1000
pF
0.01
F
H DET
OUT
1.5 kΩ
1500pF2.7
kΩ
2.2 kΩ
270 Ω X
1
4.7 F
+
0.015 F
5 V
X1:CSB503F2(Murata)
Burst gate input
‘H’: In the period of burst
‘M’: Out the period of burst
‘L’: Internal
HD
Clamp output
Field ID output
VD
NTSC/PAL
H DET 32f
H
VCO AFC
H count down
LPF ACC DET
f
2
Phase shift
ACC AMP
Color
killer
DET
APC nf
SC
VCO
BPF
47 pF
68 pF
15 H
680 Ω
0.01 F
10 kΩ
5 V
0.01 F
680 Ω
10 kΩ
2SC2785
or
equivalent
f
SC
OUT
5 V
Tint
cont.
0.1
F
CGND
0.47
F
0.01
F
5 V
++
+
1
M Ω
0.1
F
2.2 kΩ
4.7
kΩ
4.7
F
Chroma
OUT
0.022 F
510 Ω
68 pF
100 Ω
C
2 C1
X2
X2:HC-49/U(KINSEKI)
5 V
VCO OUT
External subcarrier input
Divider ratio select input
C1
C2
4 fSC
18 pF
22 pF
8 f
SC
No connect
10 pF
‘H’
‘M’
‘L’
12345
6
7 8 9 10111213 161718
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
220 pF
SGND SV
CC
8.2
kΩ
12 pF
18 pF
NTSC
(N/P =‘L’)
PAL
(N/P =‘H’)
–
–
X
2
C1
C2
15
Cannot correspond 8f
SC
of PAL.
H
sync
SEP
V
sync
SEP
V count down
Color killer OUT
…1/8
…EXT
…1/4
f
4
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
2.2 kΩ
Chroma IN
14
27
µ
PC1862
Page 28
Care Point for Planning of Application Circuit
µ
PC1862
1. Processing of V
CC pin
Please isolate Chroma. VCC from Sync. VCC as follows. If you have external processing block of digital signal, don’t
directly supply of the block’s VDD.
VDD
Processing IC of
digital signal, etc
GND
5 V
SGND
Sync (Pin 19 to pin 36)
Chroma (Pin 1 to pin 18)
CV
CC1 CVCC2 CVCC3
0.01 F 47 F 0.01 F
µµ µ
CGND
µµ
0.01 F 47 F
30 25
SV
µ
PC1862
1410215
CC
2. Application of no using Chroma pin
µ
If you don’t use Chroma pin but use Sync pin on
5 V
SCO
CV
CC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CIN CKOACCF CKF
TINT
PC1862, you process pin 1 to pin 18 as follows.
PC1862
µ
CV
COUT APCF
CGND
SCOF1 SCOF2SCOF3
CV
CC2
CC3
VCOO DIVS ESCI
0.01
µ
F
47 F
µ
0.01 F
µ
3. Application of no using Sync pin
If you don’t use Sync pin but use Chroma pin on µPC1862, you process pin 19 to pin 36 as follows. In this case, you
need to input a pin 24 with burst gate pulse from external.
In this application, you can’t use output of pin 20 to pin 23.
Video signal
input
Comp Sync Output
5 V
Open
36 35 3334 32 31 30 29 28 27 26 25 24 23 22 21 20 19
SSI CSO VSSI HDF
HDO SGND
HKO
2.2 kΩ
HSOF1
HSOF2
PC1862
µ
HSOF3
AFCF
3.3 kΩ
BGPENHSO CPO FIO VSO N/P
SV
CC
3.3 k
5 V
0 V
Ω
Burst Gate Input
Open
(Don’t use)
28
Page 29
PACKAGE DRAWING
36 PIN PLASTIC SHRINK SOP (300 mil)
µ
PC1862
118
A
G
F
E
C
MD
N
M
NOTE
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
1936
detail of lead end
5°±5°
H
I
K
L
B
P36GM-80-300B-3
ITEM MILLIMETERS INCHES
0.612 MAX.
0.039 MAX.
0.031 (T.P.)
+0.004
0.014
–0.003
0.005±0.003
0.071 MAX.
0.061
0.303±0.012
0.220
0.043
+0.004
0.008
–0.002
+0.008
0.024
–0.009
0.004
M
A
B
C
D
E
F
G
H
I
J
K
L
15.54 MAX.
0.97 MAX.
0.8 (T.P.)
+0.10
0.35
–0.05
0.125±0.075
1.8 MAX.
1.55
7.7±0.3
5.6
1.1
+0.10
0.20
–0.05
0.6±0.2
0.10
N 0.10 0.004
J
29
Page 30
µ
PC1862
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering
processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales
offices.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Surface Mount Device
µ
PC1862GS: 36-pin plastic shrink SOP (300 mil)
Process Conditions Symbol
Infrared ray reflow Peak temperature: 235 °C or below (Package surface temperature), IR35-00-2
Reflow time: 30 seconds or less (at 210 °C or higher),
Maximum number of reflow processes: 2 times.
VPS Peak temperature: 215 °C or below (Package surface temperature), VP15-00-2
Reflow time: 40 seconds or less (at 200 °C or higher),
Maximum number of reflow processes: 2 times.
Wave Soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or less, WS60-00-1
Maximum number of flow process: 1 time,
Pre-heating temperature: 120 °C or below (Package surface temperature).
Partial heating method Pin temperature: 300 °C or below, –
Heat time: 3 seconds or less (Per each side of the device).
Caution Apply only one kind of soldering condition to a device, except for “Partial heating method”, or the
device will be damaged by heat stress.
30
Page 31
[MEMO]
µ
PC1862
31
Page 32
µ
PC1862
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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