Using the latesthigh voltage MESH OVERLAY
process, STMicroelectronics has designed an
advanced family ofpower MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
APPLICATIONS
■ HIGHCURRENT, HIGH SPEEDSWITCHING
■ SWITCHMODE POWER SUPPLIES(SMPS)
■ DC-AC CONVERTERS FORWELDING
EQUIPMENTAND UNINTERRUPTIBLE
POWERSUPPLIESAND MOTOR DRIVE
2
1
I2PAK
TO-262
(suffix ”-1”)
3
D2PAK
TO-263
(Suffix ”T4”)
3
1
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
DM
P
dv/ dt(
T
(•) Pulsewidth limited by safe operating area(1)ISD≤ 5A, di/dt ≤ 200A/µs, VDD≤ V
January 2000
Drain-source Voltage (VGS=0)600V
DS
Dra in- gate Volt age (RGS=20kΩ)
DGR
Gate -sourc e Vo ltage± 30V
GS
Drain Current (continuous ) at Tc=25oC5A
I
D
I
Drain Current (continuous ) at Tc=100oC3.1A
D
600V
(•)Drain Current (pulsed)20A
Total Dissipation at Tc=25oC100W
tot
Derating Factor0.8W/
1) P eak Diode Recove ry volt age slope4.5V/ns
St orage T emper ature-65 t o 1 50
stg
Max. Op era t ing J unction Temperatu r e150
T
j
,Tj≤T
(BR)DSS
JMAX
o
C
o
C
o
C
1/9
Page 2
STB5NB60
THERMAL DATA
R
thj-case
Rthj-a mb
R
thc-sink
T
AVALANCHE CHARACTERISTICS
SymbolPara meterMax Val ueUni t
I
AR
E
Ther mal Resis t an ce Junc ti on-cas eMax
Ther mal Resis t an ce Junc ti on-ambien tMax
Thermal Resistance Case-sinkTyp
Maximum Lead Tem per at ure For Sold er ing Purpose
l
Avalanche Curr ent, Repet it ive or No t - Re petitive
(pulse width limited by T
Single Pulse Avalanche Energy
AS
(starting T
=25oC, ID=IAR,VDD=50V)
j
max)
j
1.25
62.5
0.5
300
5A
300mJ
o
C/W
oC/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS (T
=25oC unless otherwisespecified)
case
OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
(BR)DSS
Drain-sourc e
=250µAVGS=0 atTc=100oC
I
D
600V
Break d own Voltage
I
DSS
I
GSS
Zero Gate Voltage
Drain Cu rr ent (V
GS
Gat e- b ody Leak a ge
Current (V
DS
=0)
=0)
V
=600V
DS
= Max RatingTc=125oC
V
DS
= ± 30 V
V
GS
1
50
± 100nA
ON(∗)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
GS(th)
Gate Threshold
V
DS=VGSID
= 250 µA
345V
Voltage
R
DS(on)
Static Drain-source On
VGS=10V ID= 2.5 A1.82
Resistanc e
I
D(on)
On S t ate Drain Current VDS>I
D(on)xRDS(on)max
5A
VGS=10V
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.Unit
g
(∗)Forward
fs
Tr ansconduc tance
C
C
C
Input Cap acitan ce
iss
Out put Capac it ance
oss
Reverse Transfer
rss
Capacitance
VDS>I
D(on)xRDS(on)maxID
=2.5A2.54.5S
VDS=25V f=1MHz VGS=0680
103
10.5
µA
µ
Ω
pF
pF
pF
A
2/9
Page 3
STB5NB60
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
d(on)
Turn-on Time
r
Rise Time
t
VDD= 300 VID=2.5A
R
=4.7
G
Ω
VGS=10V
12
10
(see test circu it, figure 3)
Q
Q
Q
Total Gate Charge
g
Gat e- Source Char ge
gs
Gate-Drain Charge
gd
VDD= 480 V ID=5 A VGS=10V21
7.6
7.5
30nC
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
r(Voff)
t
t
Off -voltage Rise Ti me
Fall Time
f
Cross-ov er Ti m e
c
VDD= 480 VID=5 A
=4.7 ΩVGS=10V
R
G
(see test circu it, figure 5)
8
5
14
SOURCEDRAINDIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed: Pulse duration = 300µs, dutycycle 1.5%
(•) Pulse width limited by safeoperating area
Source-drain Curr ent
(•)
Source-drain Curr ent
5
20
(pulsed)
(∗)F orwar d On Volt ageISD=5A VGS=01.6V
Reverse Recov ery
rr
Time
Reverse Recov ery
rr
= 5 Adi/d t = 100 A/µs
I
SD
= 100 VTj=150oC
V
DD
(see test circu it, figure 5)
610
3.6
Charge
Reverse Recov ery
11.7
Current
ns
ns
nC
nC
ns
ns
ns
A
A
ns
µ
A
C
SafeOperating AreaThermalImpedance
3/9
Page 4
STB5NB60
OutputCharacteristics
Transconductance
TransferCharacteristics
Static Drain-sourceOn Resistance
Gate Charge vs Gate-sourceVoltage
4/9
CapacitanceVariations
Page 5
STB5NB60
Normalized GateThresholdVoltagevs
Temperature
Source-drainDiode Forward Characteristics
Normalized On Resistance vs Temperature
5/9
Page 6
STB5NB60
Fig. 1:
UnclampedInductive Load Test Circuit
Fig. 3: SwitchingTimes Test Circuits For
ResistiveLoad
Information furnished is believed tobeaccurateand reliable.However, STMicroelectronics assumes no responsibilityforthe consequences
of use of such information nor for any infringement of patents or other rights of third parties which may resultfrom its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in thispublication are
subjecttochange without notice. This publicationsupersedesandreplaces all information previouslysupplied. STMicroelectronicsproducts
are not authorized for use as critical components in lifesupport devices or systemswithout express written approval of STMicroelectronics.
The STlogo is a trademark ofSTMicroelectronics
1999STMicroelectronics – Printedin Italy – All RightsReserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China- Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia- Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom- U.S.A.
http://www.st.com
.
9/9
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