Datasheet SSM2275, SSM2475 Datasheet (Analog Devices)

Rail-to-Rail Output

1

2

3

4

8

7

6

5

(Not to Scale)

OUT A

–IN A

+IN A

V–

OUT B

–IN B

+IN B

V+

SSM2275

–IN A
+IN A

V–

OUT B
–IN B
+IN B

V+

1

4

5

8

SSM2275

OUT A

a

FEATURES
Single or Dual-Supply Operation
Excellent Sonic Characteristics
Low Noise: 7 nV/
Low THD: 0.0006%
Rail-to-Rail Output
High Output Current: ⴞ50 mA
Low Supply Current: 1.7 mA/Amplifier
Wide Bandwidth: 8 MHz
High Slew Rate: 12 V/␮s
No Phase Reversal
Unity Gain Stable
Stable Parameters Over Temperature

APPLICATIONS
Multimedia Audio
Professional Audio Systems
High Performance Consumer Audio
Microphone Preamplifier
MIDI Instruments

GENERAL DESCRIPTION

The SSM2275 and SSM2475 use the Butler Amplifier front
end, which combines both bipolar and FET transistors to offer
the accuracy and low noise performance of bipolar transistors
and the slew rates and sound quality of FETs. This product
family includes dual and quad rail-to-rail output audio amplifi­ers that achieve lower production costs than the industry stan­dard OP275 (the first Butler Amplifier offered by Analog
Devices). This lower cost amplifier also offers operation from a

single 5 V supply, in addition to conventional ±15 V supplies.

The ac performance meets the needs of the most demanding au-

dio applications, with 8 MHz bandwidth, 12 V/µs slew rate and

extremely low distortion.

The SSM2275 and SSM2475 are ideal for application in high
performance audio amplifiers, recording equipment, synthesiz­ers, MIDI instruments and computer sound cards. Where cas­caded stages demand low noise and predictable performance,
SSM2275 and SSM2475 are a cost effective solution. Both are
stable even when driving capacitive loads.

The ability to swing rail-to-rail at the outputs (see Applications sec­tion) and operate from low supply voltages enables designers to at­tain high quality audio performance, even in single supply systems.
The SSM2275 and SSM2475 are specified over the extended

industrial (–40°C to +85°C) temperature range. The SSM2275 is

available in 8-lead plastic DIPs, SOICs, and microSOIC surface­mount packages. The SSM2475 is available in narrow body
SOICs and thin shrink small outline (TSSOP) surface-mount
packages.

*Protected by U.S. Patent No. 5,101,126.

√

Hz

Audio Amplifiers

SSM2275/SSM2475*

PIN CONFIGURATIONS

8-Lead Narrow Body SOIC 14-Lead Narrow Body SOIC
(SO-8) (R-14)

1

OUT A

2

–IN A

3

+IN A

+IN B
–IN B

OUT B

V+

SSM2475

4

(Not to Scale)

5
6
7

8-Lead microSOIC 14-Lead TSSOP
(RM-8) (RU-14)

OUT A

–IN A
+IN A

+IN B
–IN B

OUT B

V+

114

SSM2475

78

8-Lead Plastic DIP

(N-8)

OUT A

–IN A

+IN A

1

2

3

4

V–

SSM2275

(Not to
Scale)

8

7

6

5

V+

OUT B

–IN B

+IN B

14
13
12
11
10

9
8

OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C

OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

SSM2275/SSM2475–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(VS = ⴞ15 V, TA = ⴙ25ⴗC, VCM = 0 V unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

OS

–40°C ≤ T

Input Bias Current I

B

–40°C ≤ T

Input Offset Current I

OS

–40°C ≤ T

V

Input Voltage Range V

IN

= ±15 V –14 +14 V

S

Common-Mode Rejection Ratio CMRR –12.5 V ≤ V

–40°C ≤ T
–12.5 V ≤ V

R

A

VO

= 2 kΩ, –12 V ≤ VO ≤ +12 V 100 240 V/mV

L

≤ +85°C16mV

A

≤ +85°C 300 500 nA

A

≤ +85°C 15 125 nA

A

≤ +12.5 V 80 100 dB

CM

≤ +85°C,

A

≤ +12.5 V 80 100 V/mV

CM

14 mV

250 400 nA

575 nA

–40°C ≤ TA ≤ +85°C 80 120 V/mV

OUTPUT CHARACTERISTICS

Output Voltage, High V

Output Voltage, Low V

Output Short Circuit Current Limit I

OH

OL

SC

I

≤ 20 mA 14 14.5 V

L

–40°C ≤ T

≤ +85°C 14.5 14.7 V

A

IL = 20 mA –14 –13.5 V

= 10 mA –14.6 –14.4 V

I

L

= 10 mA, –40°C ≤ TA ≤ +85°C –14.3 –13.9 V

I

L

±25 ±50 ±75 mA

–40°C ≤ TA ≤ +85°C ±17 ±40 ±80 mA

POWER SUPPLY

Power Supply Rejection Ratio PSRR ±2.5 V ≤ V

–40°C ≤ T

Supply Current/Amplifier I

SY

VO = 0 V 1.7 2.9 mA

≤ ±18 V 85 110 dB

S

≤ +85°C 80 105 dB

A

–40°C ≤ TA ≤ +85°C 1.75 3.0 mA

DYNAMIC PERFORMANCE

Total Harmonic Distortion THD R
Slew Rate SR R

= 10 kΩ, f = 1 kHz, V

L

= 2 kΩ储50 pF 9 12 V/µs

L

= 1 V rms 0.0006 %

O

Gain Bandwidth Product GBW 8 MHz
Channel Separation CS R

= 2 kΩ, f =1 kHz 128 dB

L

NOISE PERFORMANCE

Voltage Noise Spectral Density e
Current Noise Spectral Density i

Specifications subject to change without notice.

n

n

f > 1 kHz 8 nV/√Hz
f > 1 kHz < 1 pA/√Hz

REV. A–2–

SSM2275/SSM2475

ELECTRICAL CHARACTERISTICS

(VS = ⴙ5 V, TA = ⴙ25ⴗC, VCM = 2.5 V unless otherwise noted)

Parameter Symbol Conditions Min Typ Max Units

INPUT CHARACTERISTICS

Offset Voltage V

OS

–40°C ≤ T

Input Bias Current I

B

–40°C ≤ T

Input Offset Current I

OS

–40°C ≤ T

Input Voltage Range V

IN

Common-Mode Rejection Ratio CMRR +0.8 V ≤ V

–40°C ≤ T

R

A

VO

= 2 kΩ, –0.5 V ≤ VO ≤ +4.5 V 25 60 V/mV

L

≤ +85°C16mV

A

≤ +85°C 300 500 nA

A

≤ +85°C 15 125 nA

A

0.3 4.7 V

≤ +2 V 85 dB

CM

≤ +85°C80dB

A

14 mV

250 400 nA

575 nA

–40°C ≤ TA ≤ +85°C 20 50 V/mV

OUTPUT CHARACTERISTICS

Output Voltage, High V

Output Voltage, Low V

Output Short Circuit Current Limit I

OH

OL

SC

I

≤ –15 mA 4.2 4.5 V

L

≤ –10 mA, –40°C ≤ TA ≤ +85°C 4.5 4.8 V

I

L

I

≤ –15 mA 0.6 1.0 V

L

≤ –10 mA 0.3 0.5 V

I

L

≤ –10 mA, –40°C ≤ TA ≤ +85°C 0.7 1.1 V

I

L

–40°C ≤ TA ≤ +85°C40mA

POWER SUPPLY

Supply Current/Amplifier I

SY

VO = 0 V 1.7 2.9 mA

–40°C ≤ TA ≤ +85°C 1.75 3.0 mA

DYNAMIC PERFORMANCE

Total Harmonic Distortion THD R
Slew Rate SR R
Gain Bandwidth Product GBW R
Channel Separation CS R

NOISE PERFORMANCE

Voltage Noise Spectral Density e
Current Noise Spectral Density i

Specifications subject to change without notice.

n

n

= 10 kΩ, f = 1 kHz, V

L

= 2 kΩ储50 pF 12 V/µs

L

= 2 kΩ储10 pF 6 MHz

L

= 2 kΩ, f =1 kHz 128 dB

L

= 1 V rms 0.0006 %

O

f > 1 kHz 8 nV/√Hz
f > 1 kHz < 1 pA/√Hz

REV. A

–3–

SSM2275/SSM2475

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V
Input Voltage (V
Differential Input Voltage

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

S

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V

IN

2

. . . . . . . . . . . . . . . . . . . . . . . ±15 V

Storage Temperature Range . . . . . . . . . . . . ⫺ 65°C to ⫹150°C

Operating Temperature Range . . . . . . . . . . . ⫺40°C to ⫹85°C

Junction Temperature Range . . . . . . . . . . . . ⫺65°C to ⫹150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . ⫹300°C

ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2,000 V

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma -

1

Package Type ␪JA* ␪

JC

8-Lead Plastic DIP 103 43 °C/W
8-Lead SOIC 158 43 °C/W
8-Lead microSOIC 206 43 °C/W
14-Lead SOIC 120 36 °C/W
14-Lead TSSOP 180 35 °C/W

*θJA is specified for the worst case conditions, i.e., for device in socket for DIP

packages and soldered onto a circuit board for surface mount packages.

nent damage to the device. This is a stress rating only; the functional operation of
the device at these or any other conditions above those indicated in the opera tional
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

For supplies less than ±15 V, the input voltage and differential input voltage
must be less than ±15 V.

ORDERING GUIDE

Temperature Package Package

Model Range Description Options

SSM2275P –40°C to +85°C 8-Lead PDIP N-8
SSM2275S –40°C to +85°C 8-Lead SOIC SO-8
SSM2275RM –40°C to +85°C 8-Lead microSOIC RM-8
SSM2475S –40°C to +85°C 14-Lead SOIC R-14
SSM2475RU –40°C to +85°C 14-Lead TSSOP RU-14

Units

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2275/SSM2475 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

100

80

60

40

20

GAIN – dB

0

–20

–40

10 1M100

VS = 62.5V

= 2kV

R

L

= 10pF

C

L

1k 10k 100k

FREQUENCY – Hz

10M 40M

Figure 1. Phase/Gain vs. Frequency

225

180

135

90

45

PHASE – Degrees

0

–45

–90

100

80

60

40

20

GAIN – dB

0

–20

–40

10 1M100

1k 10k 100k

FREQUENCY – Hz

Figure 2. Phase/Gain vs. Frequency

VS = 62.5V

= 600V

R

L

= 10pF

C

L

10M 40M

225

180

135

90

45

PHASE – Degrees

0

–45

–90

REV. A–4–

g

g

Typical Characteristics–SSM2275/SSM2475

100

80

60

40

20

GAIN – dB

0

–20

–40

10 1M100

100

80

60

40

VS = 615V

= 2kV

R

L

= 10pF

C

L

1k 10k 100k

FREQUENCY – Hz

10M 40M

Figure 3. Phase/Gain vs. Frequency

VS = 615V

= 600V

R

L

= 10pF

C

L

225

180

135

90

45

0

–45

–90

225

180

135

90

rees

PHASE – De

rees

60

VS = 615V

= 1258C

T

A

50

40

30

20

10

VOLTAGE NOISE DENSITY – nV/ Hz

0

10 100k100

1k 10k

FREQUENCY – Hz

Figure 6. SSM2275 Voltage Noise Density (Typical)

140

120

100

80

VS = 615V

= 1258C

T

A

20

GAIN – dB

0

–20

–40

10 1M100

1k 10k 100k

FREQUENCY – Hz

10M 40M

45

0

–45

–90

PHASE – De

Figure 4. Phase/Gain vs. Frequency

2.0
VS = 615V

= 1258C

T

1.8

A

1.6

1.4

1.2

1.0

0.8

0.6

CURRENT NOISE DENSITY – pA/ Hz

0.4

0.2

10 10k100

FREQUENCY – Hz

1k

Figure 5. SSM2275 Current Noise Density vs. Frequency

60

40

COMMON MODE REJECTION – dB

20

0

100 30M1k

10k 1M 10M

FREQUENCY – Hz

Figure 7. Common-Mode Rejection vs. Frequency

140

120

100

80

60

40

POWER SUPPLY REJECTION – dB

20

0
100 10M1k

FREQUENCY – Hz

10k 1M

VS = 615V

= 1258C

T

A

Figure 8. Power Supply Rejection vs. Frequency

REV. A –5–

SSM2275/SSM2475–Typical Characteristics

29.5mV

0

200ns

20mV

0

SSM2275/SSM2475

–100

–110

–120

–130

–140

AMPLITUDE – dBV

–150

–160

VSY = +5V
A
R
V

0222

4 6 8 101214 161820

FREQUENCY – kHz

Figure 9. THD vs. Frequency (FFT)

= +1

V

= 100kV

L

= 0dBV

IN

11.0mV

1.0

0.9

0.8

0.7

0.6

0.5

0.4

(VOLTS-TO-RAIL) – V

OL

0.3

, V

OH

V

0.2

0.1

0

520

10 15

LOAD CURRENT – mA

V

OUT –

(V+)

V

– (V–)

OUT

Figure 12. Headroom (VOH and VOL-to-Rails), TA = +25°C

0 0

20mV

200ns

Figure 10. Small Signal Response; RL = 600 Ω, CL = 0 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

22.5mV

0 0

20mV

200ns

Figure 13. Small Signal Response; RL = 600 Ω, CL = 200 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

35.5mV

0 0

20mV

200ns

Figure 11. Small Signal Response; RL = 600 Ω, CL = 100 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

Figure 14. Small Signal Response; RL = 600 Ω, CL = 300 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

REV. A–6–

REV. A–6–

SSM2275/SSM2475

17.5mV

0 0

20mV

200ns

Figure 15. Small Signal Response; RL = 2 kΩ, CL = 0 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

31.0mV

0 0

43.0mV

00

20mV

200ns

Figure 18. Small Signal Response; RL = 2 kΩ, CL = 300 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

10.5mV

0 0

20mV

200ns

Figure 16. Small Signal Response; RL = 2 kΩ, CL = 100 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

38.0mV

0 0

20mV

200ns

Figure 17. Small Signal Response; RL = 2 kΩ, CL = 200 pF,
V

= ±2.5 V, AV = +1, VIN = 100 mV p-p

S

20mV

100ns

Figure 19. Small Signal Response; RL = 600 Ω, CL = 0 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

22.5mV

0

20mV

0

100ns

Figure 20. Small Signal Response; RL = 600 Ω, CL = 100 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

REV. A –7–

SSM2275/SSM2475–Typical Characteristics

29.0mV

0 0

20mV

200ns

Figure 21. Small Signal Response; RL = 600 Ω, CL = 200 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

35.5mV

28.0mV

0 0

20mV

100ns

Figure 24. Small Signal Response; RL = 2 kΩ, CL = 100 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

36.5mV

0 0

20mV

200ns

Figure 22. Small Signal Response; RL = 600 Ω, CL = 300 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

13.0mV

0 0

20mV

100ns

Figure 23. Small Signal Response; RL = 2 kΩ, CL = 0 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

0 0

20mV

100ns

Figure 25. Small Signal Response; RL = 2 kΩ, CL = 200 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

42.0mV

00

20mV

200ns

Figure 26. Small Signal Response; RL = 2 kΩ, CL = 300 pF,
V

= ±15 V, AV = +1, VIN = 100 mV p-p

S

REV. A–8–

SSM2275/SSM2475

THEORY OF OPERATION

The SSM2275 and SSM2475 are low noise and low distortion
rail-to-rail output amplifiers that are excellent for audio applica­tions. Based on the OP275 audiophile amplifier, the SSM2275/
SSM2475 offers many similar performance characteristics with
the advantage of a rail-to-rail output from a single supply
source. Its low input voltage noise figure of 7 nV/√Hz allows the
device to be used in applications requiring high gain, such as

microphone preamplifiers. Its 11 V/µs slew rate also allows the

SSM2275/SSM2475 to produce wide output voltage swings
while maintaining low distortion. In addition, its low harmonic
distortion figure of 0.0006% makes the SSM2275 and
SSM2475 ideal for high quality audio applications.

Figure 27 shows the simplified schematic for a single amplifier.
The amplifier contains a Butler Amplifier at the input. This
front-end design uses both bipolar and MOSFET transistors in
the differential input stage. The bipolar devices, Q1 and Q2,
improve the offset voltage and achieve the low noise perfor­mance, while the MOS devices, M1 and M2, are used to obtain
higher slew rates. The bipolar differential pair is biased with a
proportional-to-absolute-temperature (PTAT) bias source, IB1,
while the MOS differential pair is biased with a non-PTAT
source, IB2. This results in the amplifier having a constant gain­bandwidth product and a constant slew rate over temperature.

The amplifier also contains a rail-to-rail output stage that can
sink or source up to 50 mA of current. As with any rail-to-rail
output amplifier the gain of the output stage, and consequently
the open loop gain of the amplifier, is proportional to the load

resistance. With a load resistance of 50 kΩ, the dc gain of the

amplifier is over 110 dB. At load currents less than 1 mA, the
output of the amplifier can swing to within 30 mV of either sup­ply rail. As load current increases, the maximum voltage swing
of the output will decrease. This is due to the collector to emit­ter saturation voltage of the output transistors increasing with an
increasing collector current.

Input Overvoltage Protection

The maximum input differential voltage that can be applied to

the SSM2275/SSM2475 is ±7 V. A pair of internal back-to-back

Zener diodes are connected across the input terminals. This
prevents emitter-base junction breakdown from occurring to the
input transistors, Q1 and Q2, when very large differential volt­ages are applied. If the device’s differential voltage could exceed

±7 V, then the input current should be limited to less than
±5 mA. This can be easily done by placing a resistor in series

with both inputs. The minimum value of the resistor can be
determined by:

V

IN

=

DIFF MAX

001

R

7

−

,

.

(1)

There are also ESD protection diodes that are connected from
each input to each power supply rail. These diodes are normally
reversed biased, but will turn on if either input voltage exceeds
either supply rail by more than 0.6 V. Again, should this condi­tion occur the input current should be limited to less than

±5 mA. The minimum resistor value should then be:

V

IN MAX

R

IN

,

=

(2)

5

mA

In practice, RIN should be placed in series with both inputs to
reduce offset voltages caused by input bias current. This is
shown in Figure 28.

V+

R

IN

R

IN

V–

Figure 28. Using Resistors for Input Overcurrent Protection

Output Voltage Phase Reversal

The SSM2275/SSM2475 was designed to have a wide common­mode range and is immune to output voltage phase reversal with
an input voltage within the supply voltages of the device. How­ever, if either of the device’s inputs exceeds 0.6 V above the posi­tive voltage supply, the output could exhibit phase reversal.
This is due to the input transistor’s B–C junction becoming for­ward biased, causing the polarity of the input terminals of the
device to switch.

IB2

IN– Q1

M1

Q2 IN+

M2

IB1

Figure 27. Simplified Schematic

REV. A –9–

CFI

V

CC

OUT

V

EE

SSM2275/SSM2475

SSM2275

R

FB

V

OUT

R

L

V

IN

R1

0.1mF
10mF

V–

0.1mF

10mF

V+

R

B

SSM2275

R

FB

V

OUT

R

L

V

IN

R1

0.1mF
10mF

V–

0.1mF

10mF

V+

R

B

This phase reversal can be prevented by limiting the input cur­rent to +1 mA. This can be done by placing a resistor in series
with the input terminal that is expected to be overdriven. The
series resistance should be at least:

.

V

R

IN MAX

=

IN

06

−

,

1

mA

(3)

An equivalent resistor should be placed in series with both in­puts to prevent offset voltages due to input bias currents, as
shown in Figure 28.

Output Short Circuit Protection

To achieve high quality rail-to-rail performance, the output of
the SSM2275/SSM2475 is not short-circuit protected. Shorting
the output may damage or destroy the device when excessive
voltages or currents are applied. To protect the output stage, the

maximum output current should be limited to ±40 mA. Placing

a resistor in series with the output of the amplifier as shown in
Figure 29, the output current can be limited. The minimum
value for R

can be found from Equation 4.

X

V

R

SY

=

X

(4)

mA

40

For a +5 V single supply application, RX should be at least

125 Ω. Because R

affected. The trade off in using R

is inside the feedback loop, V

X

is a slight reduction in output

X

voltage swing under heavy output current loads. R

is not

OUT

will also

X

increase the effective output impedance of the amplifier to

+ RX, where RO is the output impedance of the device.

R

O

R

FB

X

FEEDBACK

V

OUT

A1

125V

A1 = 1/2 SSM2275

R

Figure 29. Output Short Circuit Protection Configuration

Power Dissipation Considerations

While many designers are constrained to use very small and low
profile packages, reliable operation demands that the maximum
junction temperatures not be exceeded. A simple calculation
will ensure that your equipment will enjoy reliable operation
over a long lifetime. Modern IC design allows dual and quad
amplifiers to be packaged in SOIC and microSOIC packages,
but it is the responsibility of the designer to determine what the
actual junction temperature will be, and prevent it from exceed-

ing the 150°C. Note that while the θ
age options, the θ

for the SOIC and TSSOP are nearly double

JA

is similar between pack-

JC

the PDIP. The calculation of maximum ambient temperature is
relatively simple to make.

For example, with the 8-lead SOIC, the calculation gives a
maximum internal power dissipation (for all amplifiers, worst
case) of P

= (150°C – 85°C)/158°C/W = 0.41 W. For the

MAX

DIP package, a similar calculation indicates that 0.63 W (ap­proximately 50% more) can be safely dissipated. Note that am­bient temperature is defined as the temperature of the PC board
to which the device is connected (in the absence of radiated or
convected heat loss). It is good practice to place higher power
devices away from the more sensitive circuits. When in doubt,
measure the temperature in the vicinity of the SSM2275 with a
thermocouple thermometer.

Maximizing Low Distortion Performance

Because the SSM2275/SSM2475 is a very low distortion amplifier,
careful attention should be given to the use of the device to prevent
inadvertently introducing distortion. Source impedances seen by
both inputs should be made equal, as shown in Figure 28, with

= R1储RF for minimum distortion. This eliminates any offset

R

B

voltages due to varying bias currents. Proper power supply
decoupling reduces distortion due to power supply variations.

Because the open loop gain of the amplifier is directly dependent

on the load resistance, loads of less than 10 kΩ will increase the

distortion of the amplifier. This is a trait of any rail-to-rail op
amp. Increasing load capacitance will also increase distortion.

It is recommended that any unused amplifiers be configured as a
unity gain follower with the noninverting input tied to ground.
This minimizes the power dissipation and any potential crosstalk
from the unused amplifier.

As with many FET-type amplifiers, the PMOS devices in the
input stage exhibit a gate-to-source capacitance that varies with
the common mode voltage. In an inverting configuration, the in­verting input is held at a virtual ground and the common-mode
voltage does not vary. This eliminates distortion due to input
capacitance modulation. In noninverting applications, the gate­to-source voltage is not constant, and the resulting capacitance
modulation can cause a slight increase in distortion.

Figure 30 shows a unity gain inverter and a unity gain follower
configuration. Figure 31 shows an FFT of the outputs of these
amplifiers with a 1 kHz sine wave. Notice how the largest har­monic amplitude (2nd harmonic) is –120 dB below the funda­mental (0.0001%) in the inverting configuration.

P

TT

=

MAX

−

I MAX A

,

θ

J

A

(5)

Figure 30. Basic Inverting and Noninverting Amplifiers

REV. A–10–

SSM2275/SSM2475

R1

1kV

R

S

909V

R

F

10kV

+5V

–5V

R

L

10kV

V

OUT

V

IN

2V p-p

10kHz

–100
–110
–120
–130
–140

NOISE – dBV

–150
–160

022

–100
–110
–120
–130
–140

NOISE – dBV

–150
–160

022

VSY = 65V

= 11

A

V

= 100kV

R

L

= 0dBV

V

IN

VSY = 15V

= –1

A

V

= 100kV

R

L

= 0dBV

V

IN

10 20

FREQUENCY – kHz

10 20

FREQUENCY – kHz

Figure 31. Spectral Graph of Amplifier Outputs

Settling Time

The high slew rate and wide gain-bandwidth product of the
SSM2275 and SSM2475 amplifiers result in fast settling times

< 1 µs) that are suitable for 16- and 20-bit applications. The

(t

S

test circuit used to measure the settling time of the SSM2275/
SSM2475 is shown in Figure 32. This test method has advan­tages over false-sum node techniques of measuring settling times
in that the actual output of the amplifier is measured, instead of
an error voltage at the sum node. Common-mode settling ef­fects are also taken into account in this circuit in addition to
slew rate and bandwidth factors.

The output waveform of the device under test is clamped by
Schottky diodes and buffered by the JFET source follower. The
signal is amplified by a factor of ten by the OP260 current feed­back amplifier and then Schottky-clamped at the output to the
oscilloscope. The 2N2222 transistor sets up the bias current for
the JFET and the OP41 is configured as a fast integrator, pro­viding overall dc offset nulling at the output.

10

8

6
4

2
0

–2

STEP SIZE – V

–4

–6
–8

–10

400 600

10.1% 10.01%

–0.01%

800 1000 1200

SETTLING TIME – ns

Figure 33. Settling Time vs. Step Size

Overdrive Recovery

The overdrive, or overload, recovery time of an amplifier is the time
required for the output voltage to return to a rated output voltage
from a saturated condition. This recovery time can be important in
applications where the amplifier must recover quickly after a large
transient event, or overload. The circuit in Figure 34 was used to
evaluate the recovery time for the SSM2275/SSM2475. Also shown

are the input and output voltages. It takes approximately 0.5 µs for

the device to recover from output overload.

Figure 34. Overload Recovery Time Test Circuit

9V–15V

–+

0.1mF

0.1mF

+

9V–15V

65V

R

1kV

1N4148

L

D1 D2

V+

DUT

V–

–

–15V

15kV

+15V

2N4416

2N2222A

1/2 OP260AJ

R

F

2kV

R

G

222V

1kV

D3

10kV

10kV

750V

SCHOTTKY DIODES D1–D4 ARE
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
IC2 IS PMI OP41EJ

D4

1mF

IC2

OUTPUT
(TO SCOPE)

Figure 32. Settling Time Test Fixture

REV. A –11–

SSM2275/SSM2475

SSM2475-A

+12V

R2

10kV

R1

10kV

C3

33pF

R9

50V

R5

10kV

SSM2475-B

+12V

R8

10kV

R7

10kV

C4

33pF

R10

50V

R3

10kV

SSM2475-C

+5V

R4

10kV

C4

10mF

R12

10kV

R11

10kV

R13

100kV

C1*

10mF

R14

100kV

C2

10mF

+12V

V

IN

V

01

R6
10kV

C3
10mF

V

02

C1* IS OPTIONAL

Capacitive Loading

The output of the SSM2275/SSM2475 can tolerate a degree of
capacitive loading. However, under certain conditions, a heavy
capacitive load could create excess phase shift at the output and
put the device into oscillation. The degree of capacitive loading
is dependent on the gain of the amplifier. At unity gain, the am­plifier could become unstable at loads greater than 600 pF. At
gain greater than unity, the amplifier can handle a higher degree
of capacitive load without oscillating. Figure 35 shows how to
configure the device to prevent oscillations from occurring.

C

FB

R

R

V

IN

R

B

50kV

INVERTING GAIN AMPLIFIER

FB

I

SSM2275

V

OUT

V

C

L

IN

50kV

NONINVERTING GAIN AMPLIFIER

R

R

B

I

C

FB

R

FB

SSM2275

V

OUT

C

L

Figure 35. Configurations for Driving Heavy Capacitive
Loads

R

should be at least 50 kΩ. To minimize offset voltage, the

B

parallel combination of R
ting a minimum C

of 15 pF bandlimits the amplifier enough to

F

and RI should be equal to RB. Set-

FB

eliminate any oscillation problems from any sized capacitive
load. The low-pass frequency is determined by:

For the values given in Figure 36, R

= 5 kΩ. With C1 omitted

IN

the circuit will provide a balanced output down to dc, otherwise
the –3 dB corner for the input frequency is set by:

=

2

π

1

(8)

RC

IN L

f

dB

−

3

The circuit can also be configured to provide additional gain if
desired. The gain of the circuit is:

where V

V

A

=

V

= VO1 – VO2, R1 = R3 = R5 = R7 and,

OUT

V

OUT

IN

2( R2)

=

(9)

R1

R2 = R4 = R6 = R8

Figure 37 shows the THD+N versus frequency response of the

circuit while driving a 600 Ω load at 1 V rms.

1

=

2

π

(6)

RC

FB F

= 15 pF, this results in an amplifier

With R

= 50 kΩ and C

FB

f

dB

−

3

F

with a 210 kHz bandwidth that can be used with any capacitive
load. If the amplifier is being used in a noninverting unity gain
configuration and R
If the offset voltage can be tolerated at the output, R
replaced by a short and C
typical input bias current of 200 nA and R

is omitted, CFB should be at least 100 pF.

I

can be removed entirely. With the

FB

= 50 kΩ, the in-

B

can be

FB

crease in offset voltage would be 10 mV. This configuration will
stabilize the amplifier under all capacitive loads.

Single Supply Differential Line Driver

Figure 36 shows a single supply differential line driver circuit

that can drive a 600 Ω load with less than 0.001% distortion.

The design mimics the performance of a fully balanced trans­former based solution. However, this design occupies much less
board space while maintaining low distortion and can operate
down to dc. Like the transformer based design, either output
can be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1.

R13 and R14 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the input’s dc voltage is equal to half of
the supply voltage. The minimum input impedance of the cir­cuit as seen from V

is:

IN

RRRRRR

IN

=+

15 37 11|| ||

()

+

()

(7)

Figure 36. A Low Noise, Single Supply Differential
Line Driver

0.1
VSY = 12V

= 600V

R

L

0.01

THD + N – %

0.001

0.0001
20 20k100

FREQUENCY – Hz

1k

10k

Figure 37. THD+N vs. Frequency of Differential Line Driver

REV. A–12–

SSM2275/SSM2475

100pF

TO LPF

SSM2275-A

+12V

16

12

11

10

R

FB

(OPTIONAL)

V

CC

ACOM

I

OUT

R

F

AD1862

NOTE: ADDITIONAL PIN CONNECTIONS OMITTED FOR CLARITY

Multimedia Soundcard Microphone Preamplifier

The low distortion and low noise figures of the SSM2275 make
it an excellent device for amplifying low level audio signals. Fig­ure 38 shows how the SSM2275 can be configured as a stereo
microphone preamplifier driving the input to a multimedia
sound codec, the AD1848. The SSM2275 can be powered from
the same +5 V single supply as the AD1848. The V

REF

pin on
the AD1848 provides a bias voltage of 2.25 V for the SSM2275.
This voltage can also be used to provide phantom power to a
condenser microphone through a 2N4124 transistor buffer and

2 kΩ resistors. The phantom power circuitry can be omitted for

dynamic microphones. The gain of SSM2275 amplifiers is set
by R2/R1 which is 100 (40 dB) as shown. Figure 39 shows the

1/2

7

RMS

+5V

0.1mF

output.

35/36

34/37

0.1mF

29

32

28

LMIC
V

CC

GND

V

REF

AD1848

RMIC

device’s THD+N performance with a 1 V

R2

10kV

+5V

L CHANNEL

MIC IN

R CHANNEL

MIC IN

10mF

2kV

+5V

2N4124

2kV

10mF

10kV

10kV

R1

100V

R1

100V

2

3

5
6

10mF

8

SSM2275

4

10mF

SSM2275

R2

10kV

1

1/2

Figure 38. Low Noise Microphone Preamplifier for
Multimedia Soundcard Codec

1

AV = +40dB

= ±2.5V

V

SY

= –40dBV

V

IN

> 10kV

R

L

= 22kHz

B

W

0.1

The AD1862 has a built in 3 kΩ resistor that is connected from

the inverting input to the output of the amplifier. The full-scale

output current of the AD1862 is ±1 mA, resulting in a maximum
output voltage of ±3 V. Additional feedback resistance can be

added in the feedback loop to increase the output voltage. With

connected the maximum output voltage will be:

R

FB

VmAkR

OUT MAX FB,

=× +

13Ω

()

(10)

Figure 40. A High Performance I-V Converter for a 20-Bit DAC

In Figure 41, the SSM2275 is used as a low-pass filter for one
channel of the AD1855, a 24-bit 96 kHz stereo sigma-delta
DAC, which uses a complementary voltage output. The filter is
configured as a second order low-pass Bessel filter with a cutoff
frequency of 50 kHz. This provides a phase linear response from
dc to 24 kHz, which is ideal for high quality audio applications.
The SSM2275 can be connected to the same +5 V power sup­ply source, that the AD1855 is connected to, eliminating the
need for extra power circuitry. The FILT output (Pin 14) from
the AD1855 provides a common reference voltage equal to half
of the supply voltage for the SSM2275.

Amplifier A1 is used as a unity-gain inverter for the positive out­put of the AD1855. The output of A1 is combined with a nega­tive output of the AD1855 into the active low pass filter around
A2. The output impedance of each output of the AD1855 is

100 Ω which must be taken into account to achieve proper dc

gain, which in Figure 41 is unity gain. In this configuration the
SSM2275 can drive reasonable capacitive loads, making the de­vice suitable for the RCA jack line outputs found in most con­sumer audio equipment.

THD + N – %

0.01

0.001
20 20k100

FREQUENCY – Hz

Figure 39. THD+N vs. Frequency (V
V

= 1 V rms)

OUT

High Performance I-V Converters and Filters for 20-Bit DACs

Because of the increasing resolution and lower harmonic distor­tions required by more audio applications, the need for high
quality amplifiers at the output of D/A converters becomes criti­cal. The SSM2275 and SSM2475 can be used as current-to­voltage converters and smoothing filters for 18- and 20-bit
DACs, achieving 0.0006% THD+N figures while running from
the same +5 V or +12 V source used to power the D/A con­verter. Figure 40 shows how the SSM2275 can be used with the
AD1862, a current output 20-bit DAC.

REV. A –13–

1k

= +5 V, AV = 40 dB,

SY

10k

+5V

28

V

DD

V

OUT–

AD1855

OUT+

FILT

GND
GND

DD

18

13 OR 18

12 OR 17

14

1

15

+5V

1.05kV

1.15kV

1.05kV
A1

0.1mF

10mF

NOTE: ADDITIONAL PIN CONNECTIONS
OMITTED FOR CLARITY

562V

1.15kV

A1 AND A2 ARE SSM2275
OR 1/2 SSM2475

4.7nF

237V

A2

10mF

Figure 41. Low-Pass Filter for a 24-Bit Stereo Sigma­Delta DAC

OUT

SSM2275/SSM2475

SPICE Macro-model

The SPICE macro-model for the SSM2275 is shown in Listing
1 on the following page. This model is based on typical values
for the device and can be downloaded from Analog Devices’
Internet site at www.analog.com. The model uses a common
emitter output stage to provide rail-to-rail performance. A resis­tor and dc voltage source, in series with the collector, accurately
portray output dropout voltage versus output current. The
VCMH and VCML sources set the upper and lower limits of
the input common mode voltage range. Both are set up as a
function of the supply voltage to mimic the varying common
mode range with supply voltage. The EOS voltage source estab­lishes the offset voltage and is also used to create the common­mode rejection and power supply rejection characteristics for
the model.

+5V SUPPLY

18-BIT

DAC

VL1
LL

2

3

4

5

6

7

8

DL

CK

DR

LR

DGND

VBR

18-BIT

SERIAL

REG.

18-BIT

SERIAL

REG.

18-BIT

DAC

V

REF

AD1868

V

REF

VBL

VOL

AGND

VOR

16

15

14

13

12

11

10

V

S

7.68kV

330pF

7.68kV

9

330pF

A secondary pole section is also set up to vary the gain band­width product and phase margin of the model based on the
supply voltage. The H1 and VR1 sources set up an equivalent
resistor that is linearly varied with supply voltage. This equiva­lent resistance, in parallel with C2, creates the secondary pole.
G2 is also linearly varied to increase the GBW at higher supply
voltages. With a supply voltage of 5 V, the gain bandwidth
product is 6.3 MHz with a 47 degree phase margin. At a 30 V
supply voltage, the GBW product moves out to 7.5 MHz with

48° phase margin.

The broadband input referred voltage noise for the model is

6.8 nV/√Hz. Flicker noise characteristics are also accurately
modeled with the 1/f corner frequency set through the KF and
AF terms in the input stage transistors. Finally, a voltage-con­trolled current source, GSY, is used to model the amplifier’s
supply current versus supply voltage characteristics.

1/2

SSM2275

9.76kV

9.76kV

3

2

7.68kV

7.68kV

6

5

8

4

100pF

100pF

1/2

SSM2275

220mF

1

47kΩ

220mF

7

47kV

LEFT
CHANNEL
OUTPUT

RIGHT
CHANNEL
OUTPUT

Figure 42. A Smoothing Filter for an 18-Bit Stereo DAC

REV. A–14–

SSM2275/SSM2475

Listing 1: SSM2275 SPICE Macro-Model

* SSM2275 SPICE Macro-Model Typical Values
* 8/97, Ver. 1
* TAM / ADSC
*
* Node assignments
* non-inverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* |||||
* |||||
.SUBCKT SSM2275 1 2 99 50 45
*
* INPUT STAGE
*
Q1 4 3 5 QNIX
Q2 6 2 7 QNIX
RC1 99 11 15E3
RC2 99 12 15E3
RE1 5 8 1E3
RE2 7 8 1E3
EOS 3 1 POLY(2) (61,98) (73,98) 1.5E-3 1.78E-5 1
IOS 1 2 5E-9
ECMH1 4 11 POLY(1) (99,50) 0.9 -30E-3
ECMH2 6 12 POLY(1) (99,50) 0.9 -30E-3
ECML1 9 50 POLY(1) (99,50) 0.1 30E-3
ECML2 10 50 POLY(1) (99,50) 0.1 30E-3
D1 9 5 DX
D2 10 7 DX
D3 13 1 DZ
D4 2 13 DZ
IBIAS 8 50 200E-6
*
* CMRR=115 dB, ZERO AT 1kHz, POLE AT 10kHz
*
ECM1 60 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 60 61 159.2E3
RCM2 61 98 17.66E3
CCM1 60 61 1E-9
*
* PSRR=120dB, ZERO AT 1kHz
*
RPS1 70 0 1E6
RPS2 71 0 1E6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 1E-10
RPS4 73 98 1.59
*
* INTERNAL VOLTAGE REFERENCE
*
RSY1 99 91 100E3
RSY2 50 90 100E3
VSN1 91 90 DC 0
EREF 98 0 (90,0) 1
GSY 99 50 POLY(1) (99,50) 0.97E-3 -7E-6
*

* ADAPTIVE POLE AND GAIN STAGE
* AT Vsy= 5, fp=12.50MHz,Av=1
* AT Vsy=30, fp=18.75MHz,Av=1.16
*
G2 98 20 POLY(2) (4,6) (99,50) 0 80.3E-6 0 0 2.79E-6
VR1 20 21 DC 0
H1 21 98 POLY(2) VR1 VSN1 0 11.317E3 0 0 -28.29E6
C2 20 98 1.2E-12
*
* POLE AT 90MHz
*
G3 98 23 (20,98) 565.5E-6
R5 23 98 1.768E3
C3 23 98 1E-12
*
* GAIN STAGE
*
G1 98 30 (23,98) 733.3E-6
R1 30 98 9.993E3
CF 30 45 200E-12
D5 31 99 DX
D6 50 32 DX
V1 31 30 0.6
V2 30 32 0.6
*
* OUTPUT STAGE
*
Q3 46 42 99 QPOX
Q4 47 44 50 QNOX
RO1 46 48 30
RO2 47 49 30
VO1 45 48 15E-3
VO2 49 45 10E-3
RB1 41 42 200
RB2 43 44 200
EO1 99 41 POLY(1) (98,30) 0.7528 1
EO2 43 50 POLY(1) (30,98) 0.7528 1
*
* MODELS
*
.MODEL QNIX NPN(IS=1E-16,BF=400,KF=1.96E-14,AF=1)
.MODEL QNOX NPN(IS=1E-16,BF=100,VAF=130)
.MODEL QPOX PNP(IS=1E-16,BF=100,VAF=130)
.MODEL DX D(IS=1E-16)
.MODEL DZ D(IS=1E-14,BV=6.6)
.ENDS SSM2275

REV. A –15–

SSM2275/SSM2475

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

0.1968 (5.00)

0.1890 (4.80)

8

5

41

PIN 1

0.0500
(1.27)

BSC

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

8-Lead Plastic DIP

0.430 (10.92)

0.348 (8.84)

8

14

PIN 1

0.100

(2.54)

BSC

5

0.070 (1.77)

0.045 (1.15)

8-Lead microSOIC

8-Lead SOIC

(SO-8)

0.2440 (6.20)

0.2284 (5.80)

0.0098 (0.25)

0.0075 (0.19)

(N-8)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

(RM-8)

0.0196 (0.50)

0.0099 (0.25)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

x 45°

0.195 (4.95)

0.115 (2.93)

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

0.177 (4.50)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

14 8

PIN 1

0.0500
(1.27)

BSC

0.201 (5.10)

0.193 (4.90)

14 8

0.169 (4.30)

1

PIN 1

0.0256
(0.65)

BSC

14-Lead SOIC

(R-14)

0.3444 (8.75)

0.3367 (8.55)

71

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

14-Lead TSSOP

(RU-14)

7

0.0118 (0.30)

0.0075 (0.19)

0.2440 (6.20)

0.2284 (5.80)

0.0099 (0.25)

0.0075 (0.19)

0.256 (6.50)

0.246 (6.25)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.0196 (0.50)

0.0099 (0.25)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

0.028 (0.70)

8°
0°

0.020 (0.50)

C3239a–0–4/99

x 45°

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)
SEATING

0.122 (3.10)

0.114 (2.90)

8

1

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

PLANE

5

4

0.199 (5.05)

0.187 (4.75)

0.043 (1.09)

0.037 (0.94)

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

33°
27°

0.028 (0.71)

0.016 (0.41)

PRINTED IN U.S.A.

REV. A–16–