Page 1
Semiconductor
Hex Schmitt-Trigger Inverter
SL74HCT14
High-Performance Silicon-Gate CMOS
The SL74HCT14 may be used as a level converter for interfacing
TTL or NMOS outputs to high-speed CMOS inputs.
The SL74HCT14 is identical in pinout to the LS/ALS14.
The SL74HCT14 is useful to “square up” slow input rise and
fall times. Due to the hysteresis voltage of the Schmitt trigger, the
SL74HCT14 finds applications in noisy environments.
• TTL/NMOS-Compatible Input Levels.
• Outputs Directly Inferface to CMOS, NMOS and TTL.
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
LOGIC DIAGRAM
ORDERING INFORMATION
SL74HCT14N Plastic
SL74HCT14D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
SLS
FUNCTION TABLE
Inputs Output
A Y
L H
H L
PIN 14 =VCC
PIN 7 = GND
System Logic
Page 2
SL74HCT14
Semiconductor
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
V
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
OUT
IIN DC Input Current, per Pin ±20 mA
I
DC Output Current, per Pin ±25 mA
OUT
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
260 °C
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, V
*
When VIN ≈ 50% VCC ,ICC>1.0 mA.
DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
OUT
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) 0 No
Limit*
mW
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and V
GND≤(VIN or V
OUT
)≤VCC.
should be constrained to the range
OUT
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs
must be left open.
System Logic
SLS
Page 3
SL74HCT14
Semiconductor
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Lim it
Symbol Parameter Test Conditions V 25 °C
-55°C
VT+max Maximum Positive-
Going Input Threshold
V
OUT
I
OUT
=0.1 V
≤ 20 µA
4.5
5.5
1.9
2.1
Voltage
VT+min Minimum Positive-
Going Input Threshold
V
OUT
I
OUT
=0.1 V
≤ 20 µA
4.5
5.5
1.2
1.4
Voltage
VT-max Maximum Negative-
Going Input Threshold
V
OUT=VCC
I
OUT
-0.1 V
≤ 20 µA
4.5
5.5
1.2
1.4
Voltage
VT-min Minimum Negative-
Going Input Threshold
V
OUT=VCC
I
OUT
-0.1 V
≤ 20 µA
4.5
5.5
0.5
0.6
Voltage
VHmax
Note 1
VHmin
Note 1
VOH Minimum High-Level
VOL Maximum Low -Level
IIN Maximum Input
Maximum Hysteresis
Voltage
Minimum Hysteresis
Voltage
V
=0.1 V or VCC-0.1V
OUT
I
≤ 20 µA
OUT
V
=0.1 V or VCC-0.1V
OUT
I
≤ 20 µA
OUT
VIN≤VT -min
Output Voltage
I
OUT
≤ 20 µA
VIN≤VT -min
I
≤4mA
OUT
VIN≥VT +max
Output Voltage
I
OUT
≤ 20 µA
VIN≥VT +max
I
≤ 4mA
OUT
VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
1.4
1.5
0.4
0.4
4.4
5.4
3.98 3.84 3.7
0.1
0.1
0.26 0.33 0.4
Leakage Current
to
≤85
°C
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
0.4
0.4
4.4
5.4
0.1
0.1
≤125
°C
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
0.4
0.4
4.4
5.4
0.1
0.1
Unit
V
V
V
V
V
V
V
V
ICC Maximum Quiescent
Supply Current
VIN=VCC or GND
I
=0µA
OUT
(per Package)
∆ICC Additional Quiescent
VIN=2.4 V, Any One Input ≥-55° C 25°C to
Supply Current
VIN=VCC or GND, Other
Inputs
I
=0 µA
OUT
Note: 1 VHmin>(VT+min) -(VT-max); VHmax=(VT+max)-(VT-min)
System Logic
SLS
5.5 1.0 10 40 µA
mA
125 °C
5.5 2.9 2.4
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SL74HCT14
Semiconductor
AC ELECTRICAL CHARACTERISTICS(V
=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
CC
Temperature Limits
Symbol Parameter 25 °C to
≤85°C ≤125°C Unit
-55°C
t
, t
PLH
Maximum Propagation Delay, Input A
PHL
32 40 48 ns
or B to Output Y (L to H)
(Figures 1 and 2)
t
, t
TLH
Maximum Output Transition Time, Any
THL
15 19 22 ns
Output (Figures 1 and 2)
CIN Maximum Input Capacitance 10 10 10 pF
Power Dissipation Capacitance (Per
Typical @25°C,VCC=5.0 V
Inverter)
CPD Used to determine the no-load dynamic
power consumption:
PD=CPDV
2
f+ICCVCC
CC
32 pF
Figure 1. Switching Waveform s Figure 2. Test Circuit
SLS
System Logic
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