Datasheet PI6C104H, PI6C104S Datasheet (PERICOM)

2

PI6C104

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

Spread Spectrum Clock Synthesizer

for Desktop Pentium II

Features

• Up to 112 MHz operation

• Spread Spectrum Modulation for CPUCLK, and PCICLK

• Two copies of CPU clock with V

of 2.5V ±5%

DD

• Seven copies of PCI clock,

(synchronous with CPU clock) 3.3V

• One copy of Ref. clock @ 14.31818MHz (3.3V

TTL

)

• 48MHz USB Clock, 24MHz Super I/O clock

2

• I

C Serial Configuration Interface

• Low cost 14.31818MHz crystal oscillator input

• Power management control

• Isolated core V

, VSS pins for noise reduction

DD

• 28-pin SSOP (H) and SOIC package (S)

Block Diagram

V

DDAPIC

APIC

V

Div

DDP

2

DDREF

V

DDCPU

V

DDPCI

0,1

REF1

2

CPUCLK[0:1]

6

PCICLK[1:6]

PCICLK_F

48MHz

24MHz/REF

XTAL_IN

XTAL_OUT

SEL

S[0..2]

S

DATA

SCLOCK

REF

OSC

PLL1

I2C

V

PLL2

MUX

PI4

Description

The PI6C104 is a high-speed low-noise clock generator designed
to work with the PI6C18X family of clock buffer to meet all clock
needs for Desktop Intel Architecture platforms. CPU and chipset
clock frequencies from 66.6 MHz to 112 MHz are supported.

Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers a portion of the I/O and the core. The 2.5V is used to power
the remaining outputs (CPU and APIC). 2.5V signaling follows
JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V
supplies is not required.

An asynchronous PD# signal may be used to orderly power down
(or up) the system during power on.

Pin Configuration

XTAL_IN

XTAL_OUT

V

SS

PCICLK_F/S1

PCICLK1

PCICLK2

PCICLK3

PCICLK4

V

DD

PCICLK5

PCICLK6/PD#

V

DD

48M/MODE

24M/REF/S2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28-Pin

H, S

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

SS

REF1/P14

V

DD

V

DD2

APIC

V

DD2

CPUCLK0

CPUCLK1

V

DD

V

SS

SDATA

SCLK

S0

V

SS

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

Pin Description

niPemaNlangiSepyT.ytQnoitpircseD

1NI_LATXIX1 tupnilatsyrczHM813.41

2TUO_LATXOX1 tupnilatsyrczHM813.41

F_KLCICPO1 .tuptuokcolcICPgninnureerF

4

1SUP+I1tibtceleSycneuqerF

01,8,7,6,5]5:1[KLCICPO5 .stuptuokcolcICP

6KLCICPO

11

#DPUP+I

1

M84O

31

EDOMUP+I tuptuo6KLCICP=1,tupni#DP=0,11nipfonoitinifedehtsenimretedEDOM

1

M42O

FERO .tuptuoecnerefeRdereffuB

41

2SUP+I.2tibtceleSycneuqerF

1

610SUP+I1 0tibtceleSycneuqerF

71KLCSUP+I1 IrofkcolClaireS

81ATADSUP+OI1 IrofataDlaireS

esiwrehtotuptuoF_KLCICP,tupni1SsinipsihtpurewopgniruD

.stuptuokcolcICP

nehwdelbasideraskcolcUPCdnaICP.tupninwoDrewoPwolevitcA

F_KLCICProftpecxe,wolsi#DP

,tupni#DP:0=EDOM.)31nip(EDOMybtessinipsihT

tuptuo6KLCICP:1=EDOM

tuptuozHM84

purewopretfatuptuozHM84semoceB.purewopgniruddelpmas,tupninaasisihT

tuptuozHM42

:stcelesedom)72nip(41P.esiwrehtotuptuo,tupni2SsinipsihtpurewopgniruD

zHM42=1,FER=0

2

2

ecafretniC

ecafretniC

22,12]1:0[KLCUPCO2 tuptuokcolcUPC

42CIPAO1 .tuptuolatsyrCdereffuB

1FERO1 .tuptuolatsyrCdereffuB

72

62,02,21,9V

52,32V

82,91,51,3V

41P11 zHM42=1,1FER=0,tcelesedom41niP

DD

2DD

SS

4V3.3.LLP,FER,eroC,ICProfylppusrewoP

2V5.2.skcolcUPC&CIPArofylppusrewoP

4sdnuorG

235

.esiwrehtotuptuo1FER,tupni41PsinipsihtpurewopgniruD

PS8164B 03/15/99

2

PI6C104

Spread Spectrum Clock Synthesizer

234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901

for Desktop Pentium II

Clock Enable Configuration

#DP]1:0[KLCUPC]5:1[KLCICPF_KLCICPskcolCrehtOlatsyrCs'OCV

0wolwolgninnuRgninnuRgninnuRgninnuR

1gninnuRgninnuRgninnuRgninnuRgninnuRgninnuR

PI6C104 I2C Address Assignment 0D2H

7A6A5A4A3A2A1A0A

11010010

2-Wire I2C Control

The I2C interface permits individual enable/disable of each clock
output and test mode enable.

The PI6C104 is a slave receiver device. It can not be read back. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.

Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH to LOW transition on SDATA while
SCLK is HIGH indicates a start condition. A LOW to HIGH
transition on SDATA while SCLK is HIGH is a stop condition
and indicates the end of a data transfer cycle.

elbaTycneuqerF

0S1S2SUPCICP

000 5703

001 8.664.33

010 6.663.33

011 8.664.33

100 2113.73

10 1 3.383.33

110 0013.33

111 0013.33

Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is always
a 7-bit address byte followed by a read/write bit. (HIGH = read
from addressed device, LOW = write to addressed device).

If the devices own address is detected, PI6C104 generates an
acknowledge by pulling SDATA line LOW during ninth clock
pulse, then accepts the following data bytes until another start or
stop condition is detected.

Following acknowledgement of the address byte (D2), two more
bytes must be sent:

1. Command Code byte, and

2. Byte Count byte.

Although the data bits on these two bytes are dont care, they
must be sent and acknowledged.

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

Byte 3 : Frequency, Spread Spectrum

#tiBpuP#niPemaNnoitpircseD

7

~DVSRdevreseR

6~0S0tiBtceleSycneuqerF

5~1S1tiBtceleSycneuqerF

4~2S2tiBtceleSycneuqerF

0

3~SFS

2~DVSRdevreseR

1~1EDOM1tiBedoM

0~0EDOM0tiBedoM

1M0M

00 ffOmurtcepSdaerpS

01 edoMtseT

10 nOmurtcepSdaerpS

11 Z-iH

Byte 4 : Clock Controls (1 = Enabled, 0 = Disabled)

#tiBpuP#niPemaNnoitpircseD

7

6~
5~

0

4~

3~
21 12NE1UPCelbanEsitluafeD,elbanE1KLCUPC

10~ DVSRdevreseR

0122NE0UPCelbanEsitluafeD,elbanE0KLCUPC

~

DVSRdevreseR

tceleSycneuqerFerawdraH=0

2

1(tceleSycneuqerFerawtfoS=1

).gerC

Byte 5 : PCI Clock Control (1 = Enabled, 0 = Disabled)

#tiBpuP#niPemaNnoitpircseD

714 NEFICPelbanEsitluafeD,elbanEF_ICP

60 11NE6ICPelbanEsitluafeD,elbanE6ICP
51 01NE5ICPelbanEsitluafeD,elbanE5ICP

40~ ~ devreseR

3
27NE3ICPelbanEsitluafeD,elbanE3ICP

16NE2ICPelbanEsitluafeD,elbanE2ICP

1

05NE1ICPelbanEsitluafeD,elbanE1ICP

8NE4ICPelbanEsitluafeD,elbanE4ICP

237

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

Byte 6 : REF Clock Control (1 = Enabled, 0 = Disabled)

#tiBpuP#niPemaNnoitpircseD

7
6~DVSRdevreseR

0

542NECIPAelbanEsitluafeD,elbanECIPA
4~DVSRdevreseR
2

1

1621NEFR1elbanEevirdhgiH1FER

0620NEFR0elbanEevirdhgiH1FER

~DVSRdevreseR

~DVSRdevreseR

evirDwoL10

tluafeD,evirDlamroN01

evirDhgiH11

0NEFR1NEFR

00

Note: Outputs are disabled @ low state

Table 1: Byte 3 Frequency and Spread Spectrum Table

SFS3tiBNESS1tiB0S6tiB1S5tiB2S4tiB)zHM(UPC)zHM(ICP)%(daerpS

100005703FFO
10001 8.664.33FFO
10010 6.663.33FFO
10011 8.664.33FFO
10100 2113.73FFO
10101 3.383.33FFO
10110 0013.33FFO
10111 0013.33FFO

1100057035.0+~5.0­11001 8.664.339.0+~9.0­11010 6.663.730.0+~0.1­11011 8.664.335.0+~5.0­11100 2113.735.0+~5.0­11101 3.383.335.0+~5.0­11110 0013.330.0+~1­11111 0013.330.0+~5.0-

Notes:

Bit 3 = Enable Software

Frequency Select

Bit 1 = Enable Software

Frequency Select
Bit 6 = Frequency Select 0
Bit 5 = Frequency Select 1
Bit 4 = Frequency Select 0

Byte 0: Test Mode Table

1tiB0tiBUPCICPM84M42CIPA/FERedoM

00 1elbat1elbatzHM84feR/zHM42zHM813.41lamroN
01 2/niX6/niX2/niX4/niXniXtseT

10 1elbat1elbatzHM84feR/zHM42zHM813.41CSS
11 Z-iHZ-iHZ-iHZ-iHZ-iHetats-irT

238

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

Power Management Timing

When MODE = 0, the device supports power management and pin
11 is input PD#. When MODE = 1, this function is not available).
A particular output is enabled only when both the I2C serial
interface and this pin indicate that it should be enabled. The clocks
may be disabled according to the following table in order to reduce
the power consumption. All clocks are stopped in the low state.

PCI_F

PD#

All clocks maintain a valid high period on transitions from running
to stopped. The CPU and PCI clocks transition between running and
stopped by waiting for one positive edge on PCI_F followed by a
negative edge on the clock of interest, after which high levels of the
outputs are either enabled or disabled. See Figure 1 below.

PCI (1:5)

CPU (0:1)

A: Represents one PCI clock wait cycle
B: Represents one CPU clock wait cycle

Figure 1. PD# Timing Diagram

Note:

1. Please note that all clocks can also be individually (asynchronously) enabled or stopped
via the 2-wire I2C control interface. In this case all clocks are stopped in the low state.

A

B

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .............................................................. 65°C to +150°C

Ambient Temperature with Power Applied ............................... 0°C to +70°C

3.3V Supply Voltage to Ground Potential .................................. 0.5V to +4.6V

2.5V Supply Voltage to Ground Potential .................................. 0.5V to +3.6V

DC Input Voltage ....................................................................... 0.5V to +4.6V

Note:

Stresses greater than those listed under MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

DC Electrical Characteristics (V

sretemaraPnoitpircseDsnoitidnoCtseT.niM.pyT.xaMstinU

I

2DD

I

2DD

I

2DD

I

DD

I

DD

I

DD

V

V

tnerruCV5.2

tnerruCV3.3

2DD

V

2DD

V

DD

V

DD

V

DD

= +3.3V ± 5%, V

DD

2DD

= +2.5V ± 5%, TA = 0°C to +70°C)

DD2

0=#DP,V526.2=

.xaM=DAOLC

zHM66.66@V526.2=

.xaM=DAOLC

001

mA

27

Am

zHM001@V526.2=

.xaM=DAOLC

0=#DP,V564.3=

.xaM=DAOLC

zHM66.66@V564.3=

.xaM=DAOLC

001

005

mA

071

Am

zHM001@V564.3=

.xaM=DAOLC

071

240

PS8164B 03/15/99

2

PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

DC Operating Specifications

lobmySsretemaraPsnoitidnoC.niM.xaMstinU

V,egatloVtupnI

DD

V

3HI

%5±V3.3=

egatlovhgihtupnIV

EROCDD

0.2V

EROCDD

3.0+
V

V

3LI

I

LI

V,egatloVtuptuO

V

HO

V

LO

V,egatloVtuptuO

DD

V

HO

5.2=%5±V

2DD

egatlovwoltupnIV

tnerrucegakaeltupnIV<0

egatlovhgihtuptuOI

egatlovwoltuptuOI

V<

NI

HO

LO

EROCDD

Am1-=0.2

Am1=4.0

%5±V3.3=

egatlovhgihtuptuOI

HO

Am1-=4.2

3.0-8.0

SS

5-5+

mA

V

V

V

LO

V,egatloVtuptuO

V

HOP

3.3=%5±V

DD

egatlovwoltuptuOI

egatlovhgihtuptuosuBICPI

HO

Am1=4.0

LO

Am1-=4.2

V

V

LOP

C

NI

C

LATX

egatlovwoltuptuosuBICPI

ecnaticapacniptupnI5

ecnaticapacsniplatX5.310.815.22

Am1=55.0

LO

Fp

C

TUO

L

NIP

T

A

ecnaticapacniptuptuO6

ecnatcudnIniP7Hn

erutarepmeTtneibmAwolfriaoN007C°

241

PS8164B 03/15/99

2

PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

Buffer Specifications

V

DD

)V(egnaR(ecnadepmI W)epyTreffuB

526.2-573.254-5.311epyT

564.3-531.355-215epyT

Type 1: 2.5V Clock Buffers

lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

t

HR

t

HF

tnerrucpu-lluPV

tnerrucpu-lluPV

tnerrucnwod-lluPV

tnerrucnwod-lluPV

Type 5: 3.3V Clock Buffers

lobmySsretemaraPsnoitidnoC.niM.pyT.xaMstinU

V0.1=72-

TUO

TUO

TUO

TUO

V573.2=72-

Am

V2.1=72

V3.0=03

etaregdeesirtuptuo1epyTV5.2V0.2-V4.0@%5±V5.214

sn/V

etaregdellaftuptuo1epyTV5.2V4.0-V0.2@%5±V5.214

I

NIMHO

I

XAMHO

I

NIMLO

I

XAMLO

t

HR

t

HF

tnerrucpu-lluPV

tnerrucpu-lluPV

tnerrucnwod-lluPV

tnerrucnwod-lluPV

etaregdeesirtuptuo5epyTV3.3V4.2-V4.0@%5±V3.314

etaregdellaftuptuo5epyTV3.3V4.0-V4.2@%5±V3.314

V0.1=33-

TUO

TUO

TUO

TUO

V531.3=33-

V59.1=03

V4.0=83

Am

sn/V

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

AC Timing

kcolCtsoH.1erugiF

tesffOKLCICPot

t

t

t

t

t

t

)V5.2(doirepKLCtsoH0.515.510.015.01

PKH

HKH

LKH

)V5.2(emithgihKLCtsoH2.50.3

)V5.2(emitwolKLCtsoH0.58.2

)V5.2(emitesirKLCtsoH4.06.14.06.1

ESIRH

)V5.2(emitllafKLCtsoH4.06.14.06.1

LLAFH

)V5.2(rettiJKLCtsoH052052sp

RETTIJ

sretemaraP

zHM66zHM001

stinU

.niM.xaM.niM.xaM

sn

)V5.2(elcyCytuDV52.1taderusaeM54555455%

t

WKSH

t

LZP

)V5.2(wekSKLCsuBtsoH571571sp

t,

HZP

yaledelbanetuptuO0.10.80.10.8

sn

t

t,

ZLP

ZHP

t

BTSH

t

PKP

t

SPKP

HKPt

yaledelbasidtuptuO0.10.80.10.8

pu-rewopmorfnoitazilibatSKLCtsoH33sm

doirepKLCICP0.03

µ

0.03

ytilibatsdoirepKLCICP005005sp

emithgihKLCICP0.210.21

µ

sn

sn

t

LKP

emitwolKLCICP0.210.21

t

WKSP

t

t

TESFFOPH

BTSP

wekSKLCsuBICP005005sp

tesffOkcolCICPottsoH5.10.45.10.4sn

pu-rewopmorfnoitazilibatSKLCICP33sm

243

PS8164B 03/15/99

2

PI6C104

Spread Spectrum Clock Synthesizer

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1.25V

1.25V

Host CLK

t

HSKW

1.25V

1.25V

Host CLK

t

HPOFFSET

1.5V

1.5V

t

HPOFFSET

PCI CLK

t

PSKW

1.5V

PCI CLK

for Desktop Pentium II

2.5V

V

SS

2.5V

V

SS

3.3V

V

SS

3.3V

V

SS

2.5V
Clocking
Interface

Figure 1. Host Clock and PCI CLK Timing

Test Load

tHKP

t

Hfall

tPKP

Test
Point

2.0

1.25

0.4

t

Hrise

Output
Buffer

Duty Cycle

tHKH

tPKH

tHKL

3.3V
Clocking
Interface

(TTL)

2.4

1.5

0.4

t

Prise

Figure 2. Clock Output Waveforms

244

t

tPKL

Pfall

PS8164B 03/15/99

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

PCB Layout Suggestion

FB1

VCC

C1

22µF

1

2

VSS

3

4

5

6

7

8

9

10

C2

VDD

11

12

13

14

28

VSS

27

26

25

24

23

22

21

20

19

18

17

16

15

C6

VDD

VDD

C5
C4

VDD

C3

VDD

VSS

VSS

FB2

VCC

C7

22µF

Via to VDD Plane

Via to GND Plane

Void in Power Plane

Note:

This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C6 should be placed as close as possible to
their respective VDD.

Recommended capacitor values:

C2-C6 ............... 0.1uF, ceramic

C1, C7 ............. 22uF

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

Minimum and Maximum Expected Capacitive Loads

kcolCdaoL.niMdaoL.xaMstinUsetoN

)KLCH(skcolCUPC0102

)KLCP(skcolCICP0303stnemeriuqer1.2ICPsteeM

Fp

sdaol2elbissop,daolecived1

zHM84,FER0102daolecived1

Notes:

1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.

2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.

3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an

additional 500Ω resistor in parallel.

Design Guidelines to Reduce EMI

1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.

2. Minimize the number of vias of the clock traces.

3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock
traces from plane to plane (refer to rule #2).

4. Position clock signals away from signals that go to any cables or any external connectors.

PI6C104

Rs

CPUCLK

PCICLK

REF

APIC

2

CL

Rs

7

CL

Rs

2

CL

Rs

Ct

1 Device load

Meets PCI2.1 Req.

1 Device load

1 Device load

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PI6C104

Spread Spectrum Clock Synthesizer

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for Desktop Pentium II

28-Pin SSOP Package Data

28

5.00

.197

5.60

.220

1

X.XX

DENOTES DIMENSIONS

X.XX

IN MILLIMETERS

.0256

BSC

0.65

.390
.413

9.90

10.50

.0098
Max.

0.25

28-Pin SOIC Package Data

28

1

.021
.031

.6969
.7125

0.533

0.787

.050

BSC

1.27

17.70

18.10

REF

.013
.020

0.33

0.51

.0926
.1043

.2914
.2992

.0040
.0118

2.35

2.65

7.40

7.60

SEATING
PLANE

0.10

0.30

.002

0.050

.078

2.0

Min

Max

SEATING

PLANE

0-8˚

.010
.029

0.41

1.27

10.00

10.65

.394
.419

.016
.050

0.254

0.737

x 45˚

0.55

0.95

.291
.322

7.40

8.20

.0091
.0125

.022
.037

0.23

0.32

.004
.009

0.09

0.25

X.XX

DENOTES DIMENSIONS

X.XX

IN MILLIMETERS

Ordering Information

N/PnoitpircseD

H401C6IPegakcaPPOSSnip-82

S401C6IPegakcaPCIOSnip-82

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax [phone] • http://www.pericom.com

247

PS8164B 03/15/99