Datasheet OPA2658E-250, OPA2658UB, OPA2658UB-2K5, OPA2658U-2K5, OPA2658U Datasheet (Burr Brown)
...Page 1
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®
OPA2658
FEATURES
● UNITY GAIN STABLE BANDWIDTH:
800MHz
● LOW POWER: 50mW/Chan.
● LOW DIFFERENTIAL GAIN/PHASE
ERRORS: 0.01%/0.03
°
● HIGH SLEW RATE: 1700V/µs
● PACKAGE: 8-Pin DIP, SO-8 and MSOP-8
Dual Wideband, Low Power, Current Feedback
OPERATIONAL AMPLIFIER
DESCRIPTION
The OPA2658 is a dual, ultra-wideband, low power
current feedback video operational amplifier featuring
high slew rate and low differential gain/phase error.
The current feedback design allows for superior large
signal bandwidth, even at high gains. The low differential gain/phase errors, wide bandwidth and low
quiescent current make the OPA2658 a perfect choice
for numerous video, imaging and communications
applications.
The OPA2658 is optimized for low gain operation,
and is also available in single, OPA658 and quad,
OPA4658 configurations.
OPA2658
APPLICATIONS
● MEDICAL IMAGING
● HIGH-RESOLUTION VIDEO
● HIGH-SPEED SIGNAL PROCESSING
● COMMUNICATIONS
● PULSE AMPLIFIERS
● ADC/DAC GAIN AMPLIFIER
● MONITOR PREAMPLIFIER
● CCD IMAGING AMPLIFIER
C
COMP
Current Mirror
+Input –Input
V
OUT
I
BIAS
I
BIAS
+V
S
–V
S
Current Mirror
Buffer
NOTE: Diagram reflects only one-half of the OPA2658
®
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1994 Burr-Brown Corporation PDS-1269D Printed in U.S.A. March, 1998
OPA2658
OPA2658
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OPA2658
SPECIFICATIONS
At TA = +25°C, VS = ±5V, RL = 100Ω, RFB = 402Ω, unless otherwise noted.
OPA2658P, U, E OPA2658UB
PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS
FREQUENCY RESPONSE
Closed-Loop Bandwidth
(2)
G = +1
(3)
800 ✻
(1)
MHz
G = +2 500 300 ✻ MHz
G = +5 210 ✻ MHz
G = +10 130 ✻ MHz
Bandwidth for 0.1dB Flatness
(2)
VO < 0.5Vp-p 135 ✻ MHz
Slew Rate
(4)
G = +2, 2V Step 1700 1000 ✻ V/µs
Over Temperature Range 1500 900 ✻ V/µs
Settling Time: 0.01% G = +2, 2V Step 15 ✻ ns
0.1% G = +2, 2V Step 12.6 ✻ ns
1% G = +2, 2V Step 4.8 ✻ ns
Spurious Free Dynamic Range f = 5MHz, G = +2, V
O
= 2Vp-p 68 ✻ dB
f = 20MHz, G = +2, V
O
= 2Vp-p 56 ✻ dB
Third-Order Intercept Point f = 10MHz, 4dBm, Each Tone 39 ✻ dBm
Differential Gain G = +2, NTSC, V
O
= 1.4Vp-p, RL = 150Ω 0.01 ✻ %
Differential Phase G = +2, NTSC, V
O
= 1.4Vp-p, RL = 150Ω 0.03 ✻ degrees
Crosstalk Input Referred, 5MHz, Channel-to-Channel –78 ✻ dB
OFFSET VOLTAGE
Input Offset Voltage V
CM
= 0V ±3 ±5.5 ±2 ±4.5 mV
Over Temperature Range ±5 ±8 ±4 ±7mV
Power Supply Rejection Input Referred, V
S
= ±4.5 to ±5.5V 55 64 58 68 dB
INPUT BIAS CURRENT
Non-Inverting V
CM
= 0V ±4.0 ±30 ✻ ±18 µA
Over Temperature Range ±10 ±80 ✻ ±35 µA
Inverting V
CM
= 0V ±2.9 ±35 ✻✻ µA
Over Temperature Range ±30 ±75 ✻✻ µA
NOISE
Input Voltage Noise
Noise Density: f = 100Hz 16 ✻ nV/√Hz
f = 10kHz 3.6 ✻ nV/√Hz
f ≥ 1MHz 3.2 ✻ nV/√Hz
Integrated Noise:
f
B
= 100Hz to 200MHz 45 ✻ µVrms
Input Bias Current Noise Density
Inverting: f ≥ 1MHz 32 ✻ pA/√Hz
Non-Inverting: f ≥ 1MHz 11.9 ✻ pA/√Hz
INPUT VOLTAGE RANGE
Common-mode Input Range ±2.9 ✻ V
Over Temperature Range ±2.5 ✻ V
Common-mode Rejection Input Referred, V
CM
= ±1V 45 50 ✻✻ dB
INPUT IMPEDANCE
Non-Inverting 500 || 1 ✻ kΩ || pF
Inverting 50 ✻ Ω
OPEN-LOOP TRANSIMPEDANCE
Open-loop Transimpedance V
O
= ±2V, RL = 100Ω 150 180 200 ✻ kΩ
Over Temperature Range 100 150 kΩ
OUTPUT
Voltage Output No Load ±2.7 ±3.0 ✻✻ V
Over Temperature Range ±2.5 ±2.8 ✻✻ V
Voltage Output R
L
= 250Ω±2.7 ±2.9 ✻✻ V
Over Temperature Range ±2.5 ±2.8 ✻✻ V
Voltage Output R
L
= 100Ω±2.2 ±2.6 ✻✻ V
Over Temperature Range ±2.0 ±2.4 ✻✻ V
Output Current, Sourcing 80 120 ✻✻ mA
Over Temperature Range 70 ✻ mA
Output Current, Sinking 60 80 ✻✻ mA
Over Temperature Range 35 ✻ mA
Short Circuit Current 150 ✻ mA
Output Resistance f < 100kHz, G = +2 0.06 ✻ Ω
POWER SUPPLY
Specified Operating Voltage ±5 ✻ V
Operating Voltage Range ±4.5 ±5.5 ✻✻V
Quiescent Current Both Channels, V
S
= ±5V ±10 ± 15.5 ✻ ±11.5 mA
Over Temperature ± 11 ±17 ✻ ±13 mA
THERMAL CHARACTERISTICS
Temperature Range Specification: P, U, E, UB –40 +85 ✻✻°C
Thermal Resistance,
θ
JA
P 8-Pin DIP 100 ✻ °C/W
U SO-8 125 ✻ °C/W
E MSOP-8 150 ✻ °C/W
NOTES: (1) An asterisk (✻) specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The
demonstration boards show low parasitic layouts for this part. Refer to the demonstration board layout for details. (3) At G = +1, R
FB
= 560Ω for DIP and
MSOP-8, and 402Ω for SO-8. (4) Slew rate is rate of change from 10% to 90% of output voltage step.
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OPA2658
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................................. ±5.5V
Internal Power Dissipation .......................... See Thermal Characteristics
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±V
S
Storage Temperature Range: P, U, UB, E ................... –40°C to +125°C
Lead Temperature (DIP, soldering, 10s) ..................................... +300°C
(SO-8 and MSOP-8, soldering, 3s) ................ +260°C
Junction Temperature (T
J
) ............................................................ +175°C
PIN CONFIGURATION
Top View DIP/SO-8/MSOP-8
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE
DRAWING TEMPERATURE PACKAGE ORDERING
PRODUCT PACKAGE NUMBER
(1)
RANGE MARKING
(2)
NUMBER
(3)
OPA2658P 8-Pin Plastic DIP 006 –40°C to +85°C OPA2658P OPA2658P
OPA2658U SO-8 Surface Mount 182 –40°C to +85°C OPA2658U OPA2658U
OPA2658UB SO-8 Surface Mount 182 –40°C to +85°C OPA2658UB OPA2658UB
OPA2658E 8-Pin MSOP-8 337 –40°C to +85°C B58 OPA2658E-250
OPA2658E-2500
NOTE: (1) For detailed drawing and dimension table, see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade will be marked with a
“B” by pin 8. (3) The MSOP-8 is available on 7" tape and reel with 250 parts, and on 14" tape and reel with 2500 parts. For example, ordering 250 pieces of
“OPA2658E-250” will get a single 250 piece tape and reel. Refer to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information.
PACKAGE/ORDERING INFORMATION
+V
S
Output
2
–Input
2
+Input
2
Output
1
–Input
1
+Input
1
–V
S
1
2
3
4
8
7
6
5
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OPA2658
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±5V, RL = 100Ω, RFB = 402Ω, unless otherwise noted.
55
50
45
40
35
30
25
–4 –3 –2 –1 0 1 2 3 4
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
Common-Mode Rejection (dB)
Common-Mode Voltage (V)
PSRR AND CMR vs TEMPERATURE
75
70
65
60
55
50
45
–50 –25 0 25 50 75 100
PSRR , CMR (dB)
Temperature (°C)
CMR
PSR–
PSRR
PSR+
SUPPLY CURRENT vs TEMPERATURE
5
4
–50 –25 0 25 50 75 100
Ambient Temperature (°C)
Supply Current /Chan. (±mA)
120
110
100
90
80
70
–50 –25 0 25 50 75 100
OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (°C)
Output Current (±mA)
IO–
I
O
+
3.20
3.10
3.0
2.90
2.80
2.70
2.60
2.50
2.40
2.30
OUTPUT SWING vs TEMPERATURE
Temperature (°C)
–40 –20 0 20 40 60 80 100
Output Swing (V)
+V
O
–V
O
RL = 250Ω
RL = 100Ω
–V
O
+V
O
NON-INVERTING INPUT BIAS CURRENT
vs TEMPERATURE
–50 –25 0 25 50 75 100
Ambient Temperature (°C)
Non-Inverting Input Bias Current I
B
+ (µA)
10
8
6
4
2
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OPA2658
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, RFB = 402Ω, unless otherwise noted.
10
6
10
5
10
4
10
3
10
2
10
1
1
0
–45
–90
–135
–180
–225
1k 10k 100k 1M 10M 100M 1G
OPEN-LOOP TRANSIMPEDANCE AND PHASE
vs FREQUENCY
Frequency (Hz)
Transimpedance (Ω)
Open-Loop Phase (°)
Phase
Transimpedance
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
Frequency (Hz)
60
40
20
0
–20
–40
–60
0
–45
–90
–135
–180
–225
1k 10k 100k 1M 10M 100M 1G
Open-Loop Gain (dB)
Open-Loop Phase (°)
Gain
Phase
INVERTING INPUT BIAS CURRENT
vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Inverting Input Bias Current I
B
– (µA)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
9
6
3
0
–3
–6
1M 10M 100M 1G
CLOSED-LOOP BANDWIDTH
Frequency (Hz)
Gain (dB)
DIP Bandwidth = 682MHz
SO-8 Bandwidth = 680MHz
G = +2
MSOP-8 Bandwidth = 351MHz
20
17
14
11
8
5
2
1M 10M 100M 1G
CLOSED-LOOP BANDWIDTH
Frequency (Hz)
Gain (dB)
MSOP-8/SO-8/DIP Bandwidth= 372MHz
G = +5
6
3
0
–3
–6
–9
1M 10M 100M 1G
CLOSED-LOOP BANDWIDTH
Frequency (Hz)
Gain (dB)
SO-8 Bandwidth = 881MHz, RFB = 402Ω
G = +1
DIP Bandwidth = 949MHz, RFB = 560Ω
MSOP-8 Bandwidth = 600MHz, RFB = 560Ω
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OPA2658
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, RFB = 402Ω, unless otherwise noted.
160
120
80
40
0
–40
–80
–120
–160
Time (5ns/div)
SMALL SIGNAL TRANSIENT RESPONSE
Output Voltage (mV)
G = +2
40
35
30
25
20
15
10
10
1009080706050403020
RECOMMENDED ISOLATION RESISTANCE
vs CAPACITIVE LOAD
Capacitive Load (pf)
Isolation Resistance
G = +2
OPA658
C
L
1kΩ
R
ISO
402Ω
402Ω
1.6
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
LARGE SIGNAL TRANSIENT RESPONSE
Time (5ns/div)
Output Voltage (V)
G = +2
–50
–60
–70
–80
–90
–100
100k 1M 10M 100M
HARMONIC DISTORTION vs FREQUENCY
Frequency (Hz)
Harmonic Distortion (dBc)
2f
O
3f
O
5MHz HARMONIC DISTORTION vs OUTPUT SWING
Output Swing (Vp-p)
–60
–65
–70
–75
–80
–85
–90
–95
–100
01234
Harmonic Distortion (dBc)
2f
O
3f
O
G = +2
26
23
20
17
14
11
8
1M 10M 100M 1G
CLOSED-LOOP BANDWIDTH
Frequency (Hz)
Gain (dB)
MSOP-8/SO-8/DIP Bandwidth = 200MHz
G = +10
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OPA2658
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, RFB = 402Ω, unless otherwise noted.
10MHz HARMONIC DISTORTION vs OUTPUT SWING
Output Swing (Vp-p)
–60
–70
–80
–90
–100
0.01 0.1
2f
O
14V10
Harmonic Distortion (dBc)
3f
O
–60
–65
–70
–75
–80
–85
–75 –50 –25 0 25 50 75 100 125
Temperature (°C)
HARMONIC DISTORTION vs TEMPERATURE
(V
O
= 2Vp-p, G = +2)
Harmonic Distortion (dBc)
3f
O
2f
O
HARMONIC DISTORTION vs GAIN
(f
O
= 5MHz, VO = 2Vp-p)
Non-Inverting Gain (V/V)
–50
–55
–60
–65
–70
–75
Harmonic Distortion (dBc)
012345678910
3f
O
2f
O
INPUT VOLTAGE AND CURRENT NOISE
vs FREQUENCY
Frequency (Hz)
100
10
1
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
10
2
10
3
10
4
10
5
10
6
10
7
Non-Inverting Noise
Inverting Current Noise
Voltage Noise
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OPA2658
For non-inverting operation, the input signal is applied to the
non-inverting (high impedance buffer) input. The output
(buffer) error current (IE) is generated at the low impedance
inverting input. The signal generated at the output is fed back
to the inverting input such that the overall gain is (1 + RFB/RFF).
Where a voltage-feedback amplifier has two symmetrical high
impedance inputs, a current feedback amplifier has a low
inverting (buffer output) impedance and a high non-inverting
(buffer input) impedance.
The closed-loop gain for the OPA2658 can be calculated
using the following equations:
(1)
(2)
At higher gains the small value inverting input impedance
causes an apparent loss in bandwidth. This can be seen from
the equation:
(3)
This loss in bandwidth at high gains can be corrected
without affecting stability by lowering the value of the
feedback resistor from the specified value of 402Ω.
OFFSET VOLTAGE AND NOISE
The output offset is the algebraic sum of the input offset
voltage and bias current errors, all with different gains to the
output. The output offset for non-inverting operation is
calculated by the following equation:
(4)
If all terms are divided by the gain (1 + R
FB/RFF
) it can be
observed that the input referred offset improves as gain
increases, and as RN decreases.
APPLICATIONS INFORMATION
THEORY OF OPERATION
Conventional op amps depend on feedback to drive their
inputs to the same potential, however the current feedback
op amp’s inverting and non-inverting inputs are connected
by a unity gain buffer, thus enabling the inverting input to
automatically assume the same potential as the non-inverting input. This results in very low impedance at the inverting
input, which makes it a very good current sensor. The
feedback loop reduces the error current seen at the inverting
input to a very small value.
DISCUSSION OF PERFORMANCE
The OPA2658 is a dual, low-power, unity gain stable,
current feedback operational amplifier which operates on
±5V power supply. The current feedback architecture offers
the following important advantages over voltage feedback
architectures: (1) the high slew rate allows the large signal
performance to approach the small signal performance, and
(2) there is very little bandwidth degradation at higher gain
settings.
The current feedback architecture of the OPA2658 provides
the traditional strength of excellent large signal response
plus wide bandwidth, making it a good choice for use in high
resolution video, medical imaging and DAC I/V Conversion. The low power requirements make it an excellent
choice for numerous portable applications.
DC GAIN TRANSFER CHARACTERISTICS
The circuit in Figure 1 shows the equivalent circuit for
calculating the DC gain. When operating the device in the
inverting mode, the input signal error current (I
E
) is ampli-
fied by the open loop transimpedance gain (T
O
). The output
signal generated is equal to T
O
x IE. Negative feedback is
applied through R
FB
such that the device operates at a gain
equal to –R
FB/RFF
.
Inverting Gain =
–
R
FB
R
FF
1 +
1
Loop Gain
Non−Inverting Gain =
1 +
R
FB
R
FF
1 +
1
Loop Gain
whereLoopGain =
T
O
RFB+ RS1 +
R
FB
R
FF
ƒ
ACTUAL
BW ≈
ƒ
AV=+2
()
BW
[]
x1.25
()
1+
R
S
R
FB
× 1 +
R
FB
R
FF
FIGURE 2. Output Offset Voltage Equivalent Circuit.
FIGURE 1. Equivalent Circuit. (1/2 of OPA2658)
V
O
T
O
C
C
L
SRS
(50Ω)
C
1
V
I
V
N
R
FF
R
FB
I
E
+
–
VIO1 +
R
FB
R
FF
± Ib
I
× R
FB
OutputOffset Voltage =±IbN× RN1 +
R
F
B
R
FF
±
R
FB
R
FF
Ib
I
R
N
Ib
N
V
IO
Page 9
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OPA2658
The feedback resistor value acts as the frequency response
compensation element for a current feedback type amplifier.
The 402Ω used in setting the specification achieves a nominal maximally flat Butterworth response while assuming a
2pF output pin parasitic. Increasing the feedback resistor
will over compensate the amplifier, rolling off the frequency
response, while decreasing it will decrease phase margin,
peaking up the frequency response. Note that a non-inverting, unity gain buffer application still requires a feedback
resistor for stability (560Ω for SO-8, 402Ω for PDIP and
560Ω for MSOP-8).
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
ISO
from
the plot of recommended R
ISO
vs capacitive load. Low
parasitic loads may not need an R
ISO
since the OPA2658 is
nominally compensated to operate with a 2pF parasitic load.
If a long trace is required and the 6dB signal loss intrinsic to
doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimensions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.
If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.
e) Socketing a high speed part like the OPA2658 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.
The effective noise at the output, generated by the op amp,
can be determined by taking the root sum of the squares of
equation (4) and applying the spectral noise values found in
the Typical Performance Curve graph section. This applies to
noise from the op amp only. Note that both the noise figure
(NF) and the equivalent input offset voltages improve as the
closed loop gain increases (by keeping R
FB
fixed and reduc-
ing R
FF
with RN = 0Ω).
INCREASING BANDWIDTH AT HIGH GAINS
The closed-loop bandwidth can be extended at high gains by
reducing the value of the feedback resistor R
FB
(see Equation
3). This bandwidth reduction is caused by the feedback
current being split between RS and R
FF
(refer to Figure 1).
As the gain increases (for a fixed R
FB
), more feedback
current is shunted through R
FF
, which reduces closed-loop
bandwidth.
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high frequency amplifier like the OPA2658 requires careful attention to layout
parasitics and selection of external components. Recommendations for PC board layout and component selection include:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1µF decoupling capacitors. At the pins,
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.
c) Careful selection and placement of external components will preserve the high frequency performance of the
OPA2658. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to
the package pins. Other network components, such as noninverting input termination resistors, should also be placed
close to the package.
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OPA2658
402Ω
1/2
OPA2658
V
AC
R
R
402Ω
R
L
+V
S
+V
S
V
S
2
R
OUT
V
S
2
V
OUT
= + AV V
AC
FIGURE 4. Closed-Loop Output Impedance vs Frequency.
100
10
1
0.1
0.01
0.001
10k 100k 1M 10M 100M
Output Impedance (Ω)
Frequency (Hz)
G = +2
SUPPLY VOLTAGES
The OPA2658 is nominally specified for operation using
±5V power supplies. A 10% tolerance on the supplies, or an
ECL –5.2V for the negative supply, is within the maximum
specified total supply voltage of 11V. Higher supply voltages
can break down internal junctions possibly leading to catastrophic failure. Single supply operation is possible as long as
common mode voltage constraints are observed. The common mode input and output voltage specifications can be
interpreted as a required headroom to the supply voltage.
Observing this input and output headroom requirement will
allow non-standard or single supply operation. Figure 3
shows one approach to single-supply operation.
OPA2658 maintains very low closed-loop output impedance
over frequency. Closed-loop output impedance increases with
frequency since loop gain decreases with frequency.
THERMAL CONSIDERATIONS
The OPA2658 will not require heatsinking under most
operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation
as described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
The total internal power dissipation (P
D
) is the sum of
quiescent (P
DQ
) and additional power dissipated in the two
output stages (P
DL1
and P
DL2
) while delivering load power.
Quiescent power is simply the specified no-load supply
current for both channels times the total supply voltage
across the part. P
DL1
and P
DL2
will depend on the required
output signals and loads. For grounded resistive loads, and
equal bipolar supplies, they would be at a maximum when
the outputs are fixed at a voltage equal to 1/2 either supply
voltage. Under this condition, P
DL1
= V
S
2
/(4•RL1) where
R
L1
includes feedback network loading. P
DL2
is calculated
the same way.
Note that it is the power in the output stages, and not into the
loads, that determines internal power dissipation.
Operating junction temperature (T
J
) is given by TA + PD
θ
JA
,
where T
A
is the ambient temperature.
As an example, compute the maximum T
J
for an OPA2658U
where both op amps are at G = +2, R
L
= 100Ω, RFB = 402Ω,
±V
S
= ±5V, and at the specified maximum TA = +85°C.
This gives:
PDQ= 10V • 17 mA
()
=170mW
P
DL1
= P
DL2
=
5V
()
2
4• 100 Ω | | 804 Ω
()
=70mW
P
D
=170 mW + 270mW
()
=310mW
T
J
= 85° C + 0.310 W •125° C/W=124° C
ESD PROTECTION
ESD static damage has been well recognized for MOSFET
devices, but any semiconductor device deserves protection
from this potentially damaging source. This is particularly
true for very high speed, fine geometry processes.
ESD static damage can cause subtle changes in amplifier
input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. Therefore,
static protection is strongly recommended when handling
the OPA2658.
OUTPUT DRIVE CAPABILITY
The OPA2658 has been optimized to drive 75Ω and 100Ω
resistive loads. The device can drive 2Vp-p into a 75Ω load.
This high-output drive capability makes the OPA2658 an
ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded.
Many demanding high-speed applications such as
ADC/DAC buffers require op amps with low wideband
output impedance. For example, low output impedance is
essential when driving the signal-dependent capacitances at
the inputs of flash A/D converters. As shown in Figure 4, the
FIGURE 3. Single Supply Operation.
Page 11
11
®
OPA2658
CAPACITIVE LOADS
The OPA2658’s output stage has been optimized to drive
low resistive loads. Capacitive loads, however, will decrease
the amplifier’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than
5pF should be buffered by connecting a small resistance,
usually 10Ω to 35Ω, in series with the output as shown in
Figure 5. This is particularly important when driving high
capacitance loads such as flash A/D converters.
In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated
with its characteristic impedance.
COMPENSATION
The OPA2658 is internally compensated and is stable in
unity gain with a phase margin of approximately 62°, and
approximately 64° in a gain of +2V/V when used with the
recommended feedback resistor value. Frequency response
for other gains are shown in the Typical Performance Curves.
The high-frequency response of the OPA2658 in a good
layout is very flat with frequency.
DISTORTION
The OPA2658’s Harmonic Distortion characteristics into a
100Ω load are shown versus frequency and power output in
the Typical Performance Curves. Distortion can be further
improved by increasing the load resistance as illustrated in
Figure 6. Remember to include the contribution of the
feedback resistance when calculating the effective load resistance seen by the amplifier.
Narrowband communication channel requirements will benefit from the OPA2658’s wide bandwidth and low
intermodulation distortion on low quiescent power. If output
signal power at two closely spaced frequencies is required,
third-order nonlinearities in any amplifier will cause spurious power at frequencies very near the two fundamental frequencies. If the two test frequencies, f
1
and f2,
are specified in terms of average and delta frequency,
fO = (f1 + f2)/2 and ∆f = f2 – f1, the two, third-order,
close-in spurious tones will appear at f
O
±3 • ∆f. The two
FIGURE 5. Driving Capacitive Loads.
C
L
R
L
50Ω
R
S
10Ω to 35Ω
402Ω402Ω
1/2
OPA2658
tone, third-order spurious plot shown in Figure 7 indicates
how far below these two equal power, closely spaced, tones
the intermodulation spurious will be. The single tone power
is at a matched 50Ω load. The unique design of the OPA2658
provides much greater spurious free range than what a twotone third-order intermodulation intercept specification would
predict. This can be seen in Figure 7 as the spurious free
range actually increases at the higher output power levels.
–55
–60
–65
–70
–75
–80
–85
5MHz HARMONIC DISTORTION vs
LOAD RESISTANCE (G = +2)
Load Resistance (Ω)
Harmonic Distortion (dBc)
10 100 1k
G = +2, VO = 2Vp-p, fO = 5MHz
3f
O
2f
O
FIGURE 6. 5MHz Harmonic Distortion vs Load Resistance.
–65
–70
–75
–80
–85
–90
–18 –16 –14 –12 –10 –8 –6 –4 –2 0 2 4
Third-Order Spurious Level (dBc)
TWO TONE, THIRD-ORDER SPURIOUS LEVELS
Single Tone Power (dBm)
20MHz
10MHz
5MHz
CROSSTALK
Crosstalk is the undesired result of the signal of one channel
mixing with and reproducing itself in the output of the other
channel. Crosstalk occurs in most multichannel integrated
circuits. In dual devices, the effect of crosstalk is measured by
driving one channel and observing the output of the undriven
channel over various frequencies. The magnitude of this effect
is referenced in terms of channel- to-channel isolation and
expressed in decibels. "Input referred" points to the fact that
there is a direct correlation between gain and crosstalk, therefore at increased gain, crosstalk also increases by a factor
equal to that of the gain. Figure 8 illustrates the measured
effect of crosstalk in the OPA2658U.
FIGURE 7. Third-Order Intercept Point vs Frequency.
Page 12
12
®
OPA2658
DIFFERENTIAL GAIN AND PHASE
Differential Gain (dG) and Differential Phase (dP) are among
the more important specifications for video applications. dG
is defined as the percent change in closed-loop gain over a
specified change in output voltage level. dP is defined as the
change in degrees of the closed-loop phase over the same
output voltage change. Both dG and dP are specified at the
NTSC sub-carrier frequency of 3.58MHz and the PAL subcarrier of 4.43MHz. All NTSC measurements were performed using a Tektronix model VM700A Video Measurement Set.
dG/dP of the OPA2658 were measured with the amplifier in
a gain of +2V/V with 75Ω input impedance and the output
back-terminated in 75Ω. The input signal selected from the
generator was a 0V to 1.4V modulated ramp with sync pulse.
With these conditions the test circuit shown in Figure 9
delivered a 100IRE modulated ramp to the 75Ω input of the
video analyzer. The signal averaging feature of the analyzer
was used to establish a reference against which the performance of the amplifier was measured. Signal averaging was
also used to measure the dg and dp of the test signal in order
to eliminate the generator’s contribution to measured amplifier performance. Typical performance of the OPA2658 is
0.025% differential gain and 0.02° differential phase to both
NTSC and PAL standards.
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
1M 10M 100M 1G
Frequency (MHz)
Crosstalk (dB)
G = +2
FIGURE 8. Channel-to-Channel Crosstalk.
FIGURE 9. Configuration for Testing Differential Gain/Phase.
SPICE MODELS
Computer simulation using SPICE is often useful when
analyzing the performance of analog circuits and systems.
This is particularly true for Video and RF amplifier circuits
where parasitic capacitance and inductance can have a major
effect on circuit performance. SPICE models are available
on a disk from the Burr-Brown Applications Department.
DEMONSTRATION BOARDS
Demonstration boards are available for each OPA2658 package style. These boards implement a very low parasitic
layout that will produce the excellent frequency and pulse
responses shown in the Typical Performance Curves. For
each package style, the recommended demonstration board
is:
DEMONSTRATION BOARD PACKAGE PRODUCT
DEM-OPA265xP 8-Pin DIP OPA2658P
DEM-OPA265xU SO-8 OPA2658U
OPA2658UB
DEM-OPA26xxE MSOP-8 OPA2658E
75Ω
75Ω
402Ω
402Ω
75Ω
75Ω
TEK TSG 130A
TEK VM700A
OPA2658
Contact your local Burr-Brown sales office or distributor to
order demonstration boards.
TYPICAL APPLICATION
FIGURE 10. Low Distortion Video Amplifier.
OPA2658
V
OUT
402Ω402Ω
Video
Input
75Ω
75Ω
75Ω Transmission Line
75Ω
1/2
Page 13
13
®
OPA2658
FIGURE 11. Circuit Detail For the DEM-OPA265xP Demonstration Board.
DEM-OPA265xP Board Layout
(A) (B)
(D)(C)
FIGURE 12a. Board Silkscreen (Bottom). 12b. Board Silkscreen (Top). 12c. Board Layout (Solder Side). 12d. Board Layout
(Layout Side).
R
6
R
1
Out
A
J
1
1
2
GND
–5V
P2
1
2
+5V
GND
P1
R
7
R
5
+In
A
R
3
R
4
R
2
R
15
R
16
–In
A
J
3
J
2
2
4
1
3
C
2
0.1µF
C
4
1µF
R
9
R
14
OPA2658
OPA2658
Out
B
J
6
R
10
R
8
+In
B
R
12
R
13
R
11
–In
B
J
4
J
5
6
8
7
5
C
3
1µF
C
1
0.1µF
1/2
1/2
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