Datasheet MT88L70AE, MT88L70AN, MT88L70AS, MT88L70AT, MT88L70AC Datasheet (MITEL)



ISO2-CMOS

MT88L70

3 Volt Integrated DTMF Receiver

Features

• 2.7 - 3.6 volt operation

• Comple te DTM F recei ver

• Low pow er co nsump tion

• Intern al gain s etti ng am plifie r

• Adjustable guard time

• Centr al office qualit y

• Power-d own mode

• Inhibi t m ode

• Functi onall y com patib le wit h Mit el’s MT887 0D

Applications

• Paging systems

• Repeater systems/mobile radio

• Credit card systems

• Remot e cont rol

• Persona l comp uters

• Telep hone a nswe rin g mach ine

ISSUE 2 May 1995

Ordering Information

MT88L70AC 18 Pin Cerami c DIP
MT88L70A E 18 Pin Pl asti c DIP
MT88L70A S 18 Pin SO IC
MT88L70A N 20 Pin SS O P
MT88L70AT 20 Pin T S S O P

-40 °C to + 85 °C

Descript io n

The MT88L70 is a complete 3 Volt, DTMF receiver
integrating both the bandsplit filter and digital
decoder functions. The filter section uses switched
capacitor techniques for high and low group
filters; the decoder uses digital counting
techniques to detect and decode all 16 DTMF tone­pairs into a 4-bit code. E xternal component count is
minimized by on c hip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.

PWDN

IN +

IN -

GS

VDD VSS VRef INH

Bias

Circuit

Chip

Chip

Power

Bias

Dial
Tone
Filter

OSC1 OSC2 St/GT ESt STD TOE

High Group

Filter

Low Group

Filter

to all
Chip
Clocks

VRef
Buffer

Zero Crossing
Detectors

Digital
Dete ction
Algorit hm

St
GT

Steering
Logic

Code
Converter
and Latch

Q1

Q2

Q3

Q4

Figure 1 - Functional Block Diagram

4-23

MT88L70

1

IN+

2

IN-

3

GS

VRef

PWDN

OSC1

OSC2

VSS

4
5

INH

6
7
8
9

18 PIN CERDIP/PDIP/SOIC

18
17
16
15
14
13
12
11
10

VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE

IN+

IN-

GS

VRef

INH

PWDN

NC
OSC1
OSC2

VSS

1
2

3
4
5

6
7
8
9

10

20 PIN SSOP/TSSOP

20
19
18
17
16
15
14
13
12
11

VDD
St/GT
ESt
StD
NC

Q4
Q3
Q2
Q1
TOE

Figure 2 - Pin Connections

Pin Description

Pin #

Name Description

18 20

11 IN+Non-Inverting Op-Amp (Input).
2 2 IN- Inverting Op-Amp (Input).
33 GSGai n Sel ect. Give s access to output of front end differential am plif ier for connection of

feedback resistor.

44 V

Reference Vol tage (Ou tput). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure

Ref

5 and Figure 6).

55 INHInhibit (Input). Logic high inhibits the detection of tones repr esenti ng cha racters A, B, C

and D. This pin input is internally pulled down.

66PWDNPower Down (Input). A ctive hig h. Powers down the device and inhi bit s the oscillat or. This

pin input is internally pulled dow n.
78OSC1Clock (Input ).
89OSC2Clock (Output). A 3.579545 MHz crystal connected between pins OS C1 and OSC2

completes the int ernal oscilla tor circuit.
910 V

Ground (Inpu t). 0V typ ical.

SS

10 11 TOE Three S tate Outpu t Enabl e (Inp ut). Logic high enables the outpu ts Q1-Q4. This pin is

pulled up internally.

11-1412-15Q1-Q4 Three State Data (Outpu t). When enabl ed by TOE, provide the code corresponding to the

last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high

impedance.

15 17 StD Delayed Steering (Output).Present s a logi c high wh en a received tone-pair has been

registered and the output latch updated; returns to logic low when the voltage on St/GT falls

below V

TSt

.

16 18 ESt Early Steering (Output). Presents a logic high once the digit al algori thm has detect ed a

valid tone pair (signal condition). Any mom enta ry loss of signal condition will cause ESt to

return to a logic low.

17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than V

detected at

TSt

St causes the device to register the detected tone pair and update the output latch. A

voltage less than V

frees the device to accept a new tone pair. T he GT out put acts to

TSt

reset the external steering time-constant ; its state is a function of ESt and the voltag e on St.

18 20 V

7, 16NC No Connect ion.

4-24

Positive power supply (Input). +3V typical.

DD

MT88L70

Functional Description

The MT88L70 monolithic DTMF receiver offers small
size, low power consumption and high performance,
with 3 volt operation. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.

Filter Section

Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.

Decoder Section

Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as v oice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see “S teering Circuit”).

Steering Circuit

Digit TOE INH ESt Q

ANYLXHZZZZ

1 HXH0001
2 HXH0010
3 HXH0011
4 HXH0100
5 HXH0101
6 HXH0110
7 HXH0111
8 HXH1000
9 HXH1001
0 HXH1010
* HXH1011
# HXH1000
A HLH1001

B HLH1010
C HLH1111
D HLH0000
A HHL
B HHL
C HHL
D HHL

undetected, the output code
will remain the same as the
previou s detected code

Q

Q

4

3

Q

2

1

Table 1. Functional Decode Table

L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE

validation period (t
(V

) of the steering logic to register the tone pair,

TSt

), vc reaches the threshold

GTP

latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v

to VDD. GT continues t o drive

c

high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three
state control input (TOE) to a logic high. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (dropout) too short to
be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.

Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC t ime constant driven by
ESt. A logic high on ESt causes v

(see Figure 3) to

c

rise as the capacitor discharges. Provided signal
condition is maintained (ESt remains high) for the

Guard Ti me Adju stm en t

In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 3 is applicable. Component
values are chosen according to the formula:

4-25

MT88L70

t

REC=tDP+tGTP

tID=tDA+t

GTA

The value of tDP is a devic e parameter (see Figure 7)
and t

is the minimum signal duration to be

REC

recognized by the receiver. A value for C of 0.1 µF is
recommended for most applications, leaving R to be

selected by the designer.

V

DD

C

v

c

=(RC)In(VDD/V
=(RC)In[VDD/(VDD-V

TSt

)

TSt

)]

St/GT

MT88L70

V

DD

ESt

StD

R

t

GTA

t

GTP

Figure 3 - Basic Steering Circuit

Different steering arrangements may be used to
select independently the guard times for tone
present (t

) and tone absent (t

GTP

). This may be

GTA

necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity. Increasing t

REC

improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short t
long t

would be appropriate for extremely noisy

DO

REC

with a

environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 4.

Power-down and Inhibit Mode

V

DD

St/GT

ESt

V

St/GT

ESt

DD

=(RPC1) In [VDD / (VDD-V

t

GTP

t

=(R1C1) In (VDD / V

C

1

R

R

1

2

a) decreasing t

C

1

R

R

2

1

GTA

R

= (R1R2) / (R1 + R2)

P

; (t

GTP

=(R1C1) In [VDD / (VDD-V

t

GTP

t

=(RPC1) In (VDD / V

GTA

R

= (R1R2) / (R1 + R2)

P

b) dec rea si ng t

GTA

GTP

; (t

GTP

< t

GTA

> t

TSt

TSt

TSt

TSt

)]

)

)

)]

)

GTA

Figure 4 - Guard Time Adjustment

Differe ntial Input Configuration

The input arrangement of the MT88L70 provides a
differential-input operational amplifier as well as a
bias source (V

) which is used to bias the input s at

Ref

mid-rail. Provision is made for connection of a
feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,

C

R

1

C

2

1

R

4

R

IN+

IN-

GS

R

3

5

R

2

V

Ref

MT88L70

+

-

)

A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.

Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).

4-26

DIFFERNTIAL INPUT AMPLIFIER

C

= C2 = 10 nF

1

= R4 = R5 = 100 kΩ

R

1

= 60 kΩ , R3, = 37.5 kΩ

R

2

R

R

VOLTAGE GAIN (AV diff) =
INPUT IMPEDANCE

2R5

=

3

R2 + R

5

(Z

INDIFF

) = 2

R

All resistors are ± 1% tolerance.
All capacitors are ± 5% tolerance.

R5
R1

2

1

2

+

1

ωC

Figure 5 - Differential Input Configur ation

DTMF
Input

MT88L70

V

DD

C

1

C

R

1

MT88L70

2

IN+
IN­GS
V

Ref

INH
PDWN
OSC1
OSC2
V

SS

X-tal

R

2

Figure 6 - Single-Ended Input Configuration

the input pins are connected as shown in Figure 6
with the op-amp connected for unity gain and V

Ref

biasing the input at 1/2VDD. Figure 5 shows the
differential configuration, which permits the
adjustment of gain with the feedback resistor R

.

5

Crystal Oscillator

V

DD

St/GT

ESt

StD

Q4
Q3
Q2
Q1

TOE

R

3

NOTES:
R

, R2 = 100 kΩ ±1%

1

R

= 30 0 kΩ ±1%

3

C

= 100 nF ±5%

1,C2

X-tal = 3.579545 MHz ±0.1%

= 3.0V + 20% / -10%

V

DD

Applications

A single-ended input configuration is shown in Figure

6. For applicat ions with differential signal inputs the
circuit shown in Figure 5 may be used.

The internal clock circuit is completed with the
addition of an exter nal 3.579545 MHz crystal and is
connected as shown in Figure 6 (Single-ended Input
Configuration).

4-27

MT88L70

Absolute Maximum Ratings

†

Parameter Symbol Min Max Units

1 DC Power Supply Vo ltag e V
2 Voltage on any pin V
3 Current at any pin (other than supply) I
4 Storage temperature T
5 Package power dissipation P

† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Derate ab o ve 75 °C at 16 m W / ° C . All le ad s s old ered to bo a rd.

Recommended Operating Conditions - Voltages are with respect to ground (V

Parameter Sym Min Typ

1 DC Power Supply Voltage V
2 Operating Tem perat u re T
3 Crystal/Clock Frequency fc

DD

2.7 3.0 3.6 V

-40 +85 °C

O

3.579545

DD

I

I

STG

D

‡

Max Units Test Conditions

VSS-0.3 VDD+0.3 V

-65 +150 ° C

) unless otherwise stated.

SS

MHz

4 Crystal/Clock Freq.Tolerance ∆fc ±0.1 %

‡ Typical figures are at 25°C and are for desi gn aid only: not guarante ed and not subject to prod ucti on testin g.

7V

10 mA

500 mW

DC Electrical Characteristics - V

Characteristics Sym Min Typ

S

1
2 Operating supply current I
3 Power consumption P

4
5 Low level input voltage V
6 Input leakage current I
7 Pull up (source) current I

8 Pull down (sink) current I

9 Input impedance (IN+, IN-) R
10 Steering thresho ld voltage V
11
12 High level output voltage V
13 Output low (sink) current I
14 Output high (source) current I
15 V
16 V

‡ Typical figures are at 25°C and are for desi gn aid only: not guarante ed and not subject to prod ucti on testin g.

Standby supply current I

U
P
P
L
Y

High level input V

I
N
P
U
T
S

Low level output voltag e V

O
U
T
P
U
T
S

output voltage V

Ref

output resistan ce R

Ref

=3.0V+ 20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise sta ted.

DD

DDQ

DD

O

IH

IL

IH/IIL

SO

SI

IN

TSt

OL

OH

OL

OH

Ref

OR

‡

1 10 µA PWDN=V

2.0 5.5 mA
6mWf

2.1 V VDD=3.0V

0.05 5 µA VIN=V
4 15 µA TOE (pin 10)=0,

15 40 µA INH= VDD, PWDN=VDD,

10 MΩ @ 1 kHz

0.465V

VDD-0.03

1.5 8 mA V

1.0 3.0 mA V

0.512V

1kΩ

Max Units Test Conditions

0.9 V VDD=3.0V

DD

VSS+0.03

V
V No load
V No load

DD

V No load

DD

=3.579545 MH z

c

or V

SS

DD

V

=3.0V

DD

V

=3.0V

DD

=0.4 V

OUT

=3.6 V, VDD=3.6V

OUT

4-28

MT88L70

Operating Char acteristics - V

=3.0V+20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.

DD

Gain Setting Amplifier

Characteristics Sym Min Typ

1 Input leakage current I
2 Input resistance R
3 Input offset voltage V

IN

IN

OS

10 MΩ

‡

Max Units Test Conditions

100 nA VSS ≤ V

25 mV
4 Power supply rejection PSRR 50 dB 1 kHz
5 Common mode rejection CMRR 40 dB V

6 DC open loop voltage gain A
7 Unity gain bandwidth f
8 Output voltage swing V
9 Maximum capacitive load (GS) C

10 Resistive load (GS) R

11 Common mod e range V

VOL

C

O

L

L

CM

32 dB

0.30 MHz

2.2 V

pp

100 pF

50 kΩ

1.5 V

pp

≤ V

IN

DD

+ 0.75 V ≤ V

SS

-0.75

V

DD

biased at V

Ref

≤

IN

=1.5 V

Load ≥ 100 kΩ to VSS @ GS

No Load

AC Electrical Characteristics - V

Characteristi cs Sym Min Typ

1 Valid in put signal levels

(each tone of composite
signal)

=3.0V +20%/-10%, VSS=0V, -40°C ≤ TO ≤ +85°C, using Test Circuit shown in Fig. 6.

DD

‡

Max Units Notes*

-34

15.4

-4.0
489

dBm

mV

RMS

1,2,3,5,6,9
Min @ V

DD

Max @ V
2 Negative twist accept 8 dB 2,3, 6, 9, 12
3 Positive twist accept 8 dB 2,3, 6, 9,12
4 Frequency deviation accept ±1.5% ± 2 Hz 2,3,5,9
5 Frequency deviation reject ±3.5% 2,3,5,9
6 Third zone tolerance -16 dB 2,3,4,5,9,10
7 Noise tolerance -12 dB 2,3,4, 5,7,9,10
8 Dial zone tolerance +22 dB 2,3,4, 5, 8,9, 11

‡ Typical figures are at 25 °C and are for design aid only: not guarante ed and not subject to pro duct ion testin g.

*NOTES

1. dBm= decibel s abov e or belo w a refer enc e power of 1 mW into a 600 ohm lo ad.

2. Digit sequence consists of all DTMF tones.

3. Tone duration= 4 0 m s , ton e pa us e= 40 ms.

4. Sign al c on dit ion cons is ts o f n om in al D TM F fr e qu en ci es .

5. Both to ne s in compo si t e si gn al h av e an equal am pl it ud e.

6. Tone pair is d ev ia ted b y ±1 .5 %± 2 H z .

7. Band w id th li mited (3 k H z ) G a us s ian n oi se .

8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.

9. For a n err o r ra te of bette r t ha n 1 i n 1 0, 00 0.

10. Refe ren ce d to lowes t l ev e l f r eq ue nc y co m po ne nt in D TM F si gn al .
11 . R e fe r en c ed to th e minimu m v ali d ac ce p t le v el.

12. Guaranteed by design and characterization.

=3.6V

DD

=2.7V

4-29

MT88L70

AC Electrical Characteristics - V

=3.0 V+20% /-10% , VSS=0V, -40°C ≤ To ≤ +85°C, usin g Test Ci rcuit shown in Figure 6.

DD

Characteristics Sym Min Typ

1
2 To ne absent det ect t im e t
3 Tone duration accept t
4 Tone duration reject t
5 Int erdigit pause a c cept t

Tone prese nt detect ti me t

T

I

M

I

N

G

6 Int erdigit pause reject t
7
8 Propag ation delay (St to StD) t
9 O utp ut data se t up (Q to StD) t

10 Propagation delay (TOE to Q ENABLE) t

11 Propagation delay (TOE to Q DISABLE) t

12
13 Power-down time t

Propagation delay (St to Q) t

O

U
T
P
U
T
S

P

Power-up time t

D

W

N

DP

DA

REC

REC

ID

DO

PQ

PStD

QStD

PTE

PTD

PU

PD

‡

Max Units Con ditio ns

5 11 14 ms Note 1

0.548.5msNote 1
40 ms Note 2

20 ms N o te 2

40 ms Note 2

20 ms N o te 2

5.0

11 µs TOE=V
20

µs
µs

TOE=V
TOE=V

DD

DD

DD

50 ns l oad of 10 kΩ,

50 pF

130 ns l oad of 10 kΩ,

50 pF
30 ms No te 3
20 ms

14
15 Clock input rise time t
16 Clock input fall time t
17 Clock input duty cycle DC
18 Capacitive load (OSC2) C

‡ Typical figures are at 25°C and are for desi gn aid only: not guarante ed and not subject to prod ucti on testin g.

*NOTES:

1. Used fo r g ua r d-t im e c a lc ul ation p urp os e s o nl y an d tes te d at - 4d Bm .

2. These, us er adju s tab le p ar a m ete r s, are no t d ev ic e sp ec if ic ations . T he a djustable sett in gs o f t hese min im um s a nd m ax im u ms

3. With va li d ton e pr e se nt at input, t

Crystal/clock frequency f

C
L

O

C
K

are recommendations based upon network requirements.

equal s tim e fr o m PD WN go in g l ow un til ES t go in g hi gh.

PU

3.5759 3.5795 3.5831 MHz

C

LHCL

HLCL

40 50 60 % Ext. clock

CL

LO

110 ns Ext. clock
110 ns Ext. clock

15 pF

4-30

EVENTS

D

ABC

EFG

MT88L70

V

in

ESt

St/GT

Q

1-Q4

StD

TOE

t

REC

DECODED TONE # (n-1)

t

REC

TONE #n

t

DP

t

GTP

t

PQ

t

QStD

t

ID

TONE
#n + 1

t

DA

t

GTA

# n # (n + 1)

t

PSrD

t

DO

TONE
#n + 1

HIGH IMPEDANCE

t

PTD

t

PTE

V

TSt

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED .
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS.
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID

TONE.
D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURR ENTLY

HIGH IMPEDANCE).
F) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G) END OF TONE #n+1 DETECTED, TONE ABSEN T DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT

VALID TONE.

EXPLANATION OF SYMBOLS

V

DTMF COMP O SITE INPU T SI GN AL.

in

ESt EARLY S TEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING I NPUT/G UARD TIM E OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
Q

4-BIT DECODED TONE OUTPUT.

1-Q4

StD DELAYED STEERING OUTPUT. INDICATES THAT VA LID FREQ UE NC IES HAVE BEEN PRESENT/ABSENT FOR THE

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE TONE O UTP U T ENA BLE (INPUT). A L OW L EVEL SHI FTS Q
t

REC

t

REC

t

ID

t

DO

t

DP

t

DA

t

GTP

t

GTA

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.

MINIMUM DTMF SIGNAL DURATIO N REQUIRED FOR VALID RECOGNITION.

MINIMUM TI ME BETWEEN VALID DTMF SIGNALS.

MAXIMUM ALLOWABLE DROP OUT DURING VALID DT MF SIGNAL.

TIME TO DETECT TH E PRES EN CE OF VALID DTMF SIGNAL S.

TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.

GUARD TIME, TONE PRESENT.

GUARD TIME, TONE ABSENT.

TO ITS HIGH IMPEDANCE S TATE.

1-Q4

Figure 7 - Timing Diagram

4-31

MT88L70

NOTE S:

4-32