Datasheet M48Z512AY-85PM1, M48Z512A-85PM1, M48Z512AY-70PM1, M48Z512AY, M48Z512A-70PM1 Datasheet (SGS Thomson Microelectronics)

4 Mbit (512Kb x8) ZEROPOWERSRAM

■ INTEGRATED LOW POWER SRAM,

POWER-FAIL CONTROL CIRCUIT and
BATTERY

■ CONVENTIONAL SRAM OPERATION;

UNLIMITED WRITE CYCLES

■ 10 YEARS of DATA RETENTION in the

ABSENCE of POWER

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

(V

= Power-fail Deselect Voltage):

PFD

– M48Z512A: 4.50V ≤ V
– M48Z512AY: 4.20V ≤ V

■ BATTERY INTERNALLY ISOLATED UNTIL

POWER IS APPLIED

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 512K x 8 SRAMs

■ SURFACE MOUNT CHIP SET PACKAGING

INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY

■ SNAPHAT



HOUSING (BATTERY) IS

REPLACEABLE

PFD

PFD

≤ 4.75V

≤ 4.50V

32

1

PMDIP32 (PM)

Module

32

1

TSOP II 32

(10 x 20mm)

Surface Mount Chip Set Solution (CS)

Figure 1. Logic Diagram

V

CC

M48Z512A

M48Z512AY

SNAPHAT (SH)

Battery

SOH28

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs / Outputs

E Chip Enable

G Output Enable

W Write Enable
V

CC

V

SS

Supply Voltage

Ground

A0-A18

W

19

M48Z512A

M48Z512AY

E

G

V

SS

8

DQ0-DQ7

AI02043

1/17March 2000

M48Z512A, M48Z512AY

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

T

BIAS

(2)

T

SLD

V

IO

V

CC

Note: 1. Stresses greater thanthose listed under ”Absolute MaximumRatings” maycause permanent damage to the device. This is astress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

Ambient Operating Temperature 0 to 70 °C
Storage Temperature (VCCOff) –40 to 70 °C
Temperature Under Bias –40 to 70 °C

Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V

Supply Voltage –0.3 to 7 V

(1)

Table 3. Operating Modes

Mode

Deselect
Write V
Read
Read V

V

CC

4.75V to 5.5V
or

4.5V to 5.5V

E G W DQ0-DQ7 Power

V

IH

IL

V

IL

IL

X X High Z Standby
XVILD

V

IL

V

IH

V

IH

V

IH

IN

D

OUT

High Z Active

Active
Active

Deselect
Deselect ≤ V

Note: 1. X = VIHor VIL;VSO= Battery Back-up Switchover Voltage.

to V

V

SO

PFD

SO

(min)

X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode

Figure 2. DIP Connections

A18 V
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0

DQ2

SS

1
2

4
5
6
7

M48Z512A

8

M48Z512AY

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

AI02044

CC

A15
A173
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

DESCRIPTION

The M48Z512A/512AY ZEROPOWERRAM is a
non-volatile 4,194,304 bit Static RAM organized
as 524,288 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic 32 pin DIP Module.

For surface mount environments ST provides a
Chip Set solution consisting of a 28 pin 330mil
SOIC NVRAM Supervisor (M40Z300) and a 32 pin
TSOP Type II (10 x 20mm) LPSRAM (M68Z512)
packages.

The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack­age after the completion of the surface mount pro­cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface­mounting. The SNAPHAT housing is keyed topre­vent reverse insertion.

The SNAPHAT battery package is shipped sepa­rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Zxx-BR00SH1”.

2/17

Figure 3. Block Diagram

M48Z512A, M48Z512AY

V

CC

A0-A18

POWER

VOLTAGE SENSE

E

AND

SWITCHING

CIRCUITRY

INTERNAL
BATTERY

The M48Z512A/512AY also has itsown Power-fail
Detect circuit.The controlcircuitry constantlymon­itors the single 5V supply for an out of tolerance
condition. When VCCis out oftolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys­tem operation brought on by low VCC.AsVCCfalls
below approximately 3V, the control circuitry con­nects the battery which maintains data until valid
power returns.

The ZEROPOWER RAM replaces industry stan­dard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special write

512K x

SRAM ARRAY

E

8

V

SS

DQ0-DQ7

W

G

AI02045

timing or limitations on the number of writes that
can be performed.

The M48Z512A/512AY has its own Power-fail De­tect Circuit. The control circuitry constantly moni­tors the single 5V supply for an out of tolerance
condition. When VCCis out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys­tem operations brought on by low VCC.AsV
falls below approximately 3V, the control circuitry
connectsthe battery whichsustains data untilvalid
power returns.

CC

3/17

M48Z512A, M48Z512AY

Figure 4. Hardware Hookup for SMT Chip Set

(2)

M40Z300

E1
E2
E3
E4

V

SS

V

CON
CON
CON
CON

OUT

RST

BL

SNAPHAT
BATTERY

THS

(3)

E

A

B

(1)

V

CC

E2

M68Z512

E

A0-A18

W

DQ0-DQ7

V

SS

AI03631

Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z512 at www.st.com.

2. Connect THS pin to V

3. SNAPHAT top ordered separately.

Table 4. AC Measurement Conditions

OUT

if 4.2V ≤ V

≤ 4.5V (M48Z512AY) or connect THS pin to VSSif 4.5V ≤ V

PFD

Figure 5. AC Testing Load Circuit

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where dataisno longer
driven.

DEVICE
UNDER

TEST

1kΩ

CLincludes JIG capacitance

≤ 4.75V (M48Z512A).

PFD

5V

1.9kΩ

CL= 100pF or

OUT

5pF

AI01030

4/17

M48Z512A, M48Z512AY

Table 5. Capacitance

(1, 2)

(TA=25°C, f = 1MHz)

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IO

Note: 1. Effective capacitance measured with power supply at 5V.

2. Sampled only, not 100% tested.

3. Outputs deselected.

Input Capacitance

(3)

Input / Output Capacitance

V

V

OUT

IN

=0V

=0V

10 pF
10 pF

Table 6. DC Characteristics

(TA= 0 to 70 °C; VCC= 4.75V to 5.5V or 4.5V to 5.5V)

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

I

LO

I

CC

I

CC1

I

CC2

V

IL

V

IH

V

OL

V

OH

Note: 1. Outputs deselected.

Input Leakage Current

(1)

Output Leakage Current
Supply Current E = VIL, Outputs open 115 mA
Supply Current (Standby) TTL

Supply Current (Standby) CMOS
Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2 VCC+ 0.3 V
Output Low Voltage

Output High Voltage IOH= –1mA 2.4 V

0V ≤ V

0V ≤ V

E ≥ V

I

OL

IN

OUT

E=V

– 0.2V

CC

= 2.1mA

≤ V

≤ V

IH

CC

CC

±1 µA
±1 µA

10 mA

5mA

0.4 V

Table 7. Power Down/Up TripPoints DC Characteristics

(1)

(TA= 0 to 70 °C)

Symbol Parameter Min Typ Max Unit

V

PFD

V

SO

t

DR

Note: 1. All voltages referenced to VSS.

2. At 25 °C.

Power-fail Deselect Voltage

Battery Back-up Switchover Voltage 3 V

(2)

Data Retention Time 10 YEARS

M48Z512A 4.5 4.6 4.75 V
M48Z512AY 4.2 4.3 4.5 V

5/17

M48Z512A, M48Z512AY

Table 8. Power Down/Up AC Characteristics

(TA= 0 to 70 °C)

Symbol Parameter Min Max Unit

(1)

t

F

t

FB

t

WP

t

R

V

(max) to V

(2)

PFD

V

(min) to VSOVCCFallTime

PFD

PFD

Write Protect Time from VCC=V
VSOto V

(max) VCCRise Time

PFD

(min) VCCFall Time

PFD

300 µs

10 µs
40 150 µs

0 µs

t

ER

Note: 1. V

2. V

E Recovery Time 40 120 ms

(max) to V

PFD

(min).

es V

PFD

(min) to VSOfall time of less than tFBmay cause corruption of RAM data.

PFD

(min) fall time of less than tFmay result indeselection/write protection not occurring until 200µs after VCCpass-

PFD

Figure 6. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

V

SO

tF

tFB

tWP

E

OUTPUTS

VALID VALID

(PER CONTROL INPUT)

tDR

DON’T CARE

HIGH-Z

tR

tER

RECOGNIZEDRECOGNIZED

(PER CONTROL INPUT)

6/17

AI01031

Table 9. Read Mode AC Characteristics

(TA= 0 to 70 °C; VCC= 4.75V to 5.5V or 4.5V to 5.5V)

Symbol Parameter

t

AVAV

t

AVQV

t

ELQV

t

GLQV

t

ELQX

t

GLQX

t

EHQZ

t

GHQZ

t

AXQX

Note: 1. CL= 100pF.

2. C

Read Cycle Time 70 85 ns

(1)

Address Valid to Output Valid 70 85 ns

(1)

Chip Enable Low to Output Valid 70 85 ns

(1)

Output Enable Low to Output Valid 35 45 ns

(2)

Chip Enable Low to Output Transition 5 5 ns

(2)

Output Enable Low to Output Transition 5 5 ns

(2)

Chip Enable High to Output Hi-Z 30 35 ns

(2)

Output Enable High to Output Hi-Z 20 25 ns

(1)

Address Transition to Output Transition 5 5 ns

= 5pF.

L

M48Z512A, M48Z512AY

M48Z512A/M48Z512AY

Unit-70 -85

Min Max Min Max

Figure 7. Address Controlled, Read Mode AC Waveforms

A0-A18

tAVAV

tAVQV

DQ0-DQ7

Note: Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.

tAXQX

DATA VALID

AI01220

7/17

M48Z512A, M48Z512AY

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

tAVAV

A0-A18

tAVQV tAXQX

tELQV

E

tELQX

tGLQV

G

tGLQX

DQ0-DQ7

Note: Write Enable (W) = High.

READ MODE

The M48Z512A/512AY is in theRead Mode when­ever W (Write Enable) is high and E (Chip Enable)
is low. The device architecture allows ripple­through access of data from eight of 4,194,304 lo­cations in the static storage array. Thus, the
unique address specified by the 19 Address Inputs
defines which one of the 524,288 bytes of data is
to be accessed. Valid data will be available at the
Data I/O pins within Address Access time (t

AVQV

after the last address inputsignal is stable, provid­ing that the E (Chip Enable) and G (Output En­able) access times are also satisfied. If the E and
G access times are not met, valid data will be

VALID

tEHQZ

tGHQZ

DATA OUT

AI01221

available after the later of Chip Enable Access
time (t
(t

GLQV

) or Output Enable Access Time

ELQV

). The state of the eight three-state Data I/O
signals is controlled by E and G.If the outputs are
activatedbefore t
to an indeterminate state until t

, the data lines will be driven

AVQV

AVQV

dress Inputs are changed while E and G remain
low, output data will remain valid for Output Data
Hold time (t
next Address Access.

)

)but will go indeterminate until the

AXQX

. If the Ad-

8/17

Table 10. Write Mode AC Characteristics

(TA= 0 to 70 °C; VCC= 4.75V to 5.5V or 4.5V to 5.5V)

M48Z512A/M48Z512AY

Symbol Parameter

Min Max Min Max

t

AVAV

t

AVWL

t

AVEL

t

WLWH

t

ELEH

t

WHAX

t

EHAX

t

DVWH

t

DVEH

t

WHDX

t

EHDX

(1, 2)

t

WLQZ

t

AVWH

t

AVEH

(1, 2)

t

WHQX

Note: 1. CL= 5pF.

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Write Cycle Time 70 85 ns
Address Valid to Write Enable Low 0 0 ns
Address Valid to Chip Enable Low 0 0 ns
Write Enable Pulse Width 55 65 ns
Chip Enable Low to Chip Enable High 55 75 ns
Write Enable High to Address Transition 5 5 ns
Chip Enable High to Address Transition 15 15 ns
Input Valid to Write Enable High 30 35 ns
Input Valid to Chip Enable High 30 35 ns
Write Enable High to Input Transition 0 0 ns
Chip Enable High to Input Transition 10 10 ns

Write Enable Low to Output Hi-Z 25 30 ns
Address Valid to Write Enable High 65 75 ns

Address Valid to Chip Enable High 65 75 ns
Write Enable High to Output Transition 5 5 ns

M48Z512A, M48Z512AY

Unit-70 -85

WRITE MODE

The M48Z512A/512AY is in the WriteMode when­ever W and E are active. The start of a write is ref­erenced from the latter occurring falling edge of W
or E. Awrite is terminatedby the earlier rising edge
of W or E.

The addresses must be held valid throughout the
cycle. E or W must return high for a minimum of t

E-

from E or t

HAX

from W prior to the initiation

WHAX

of another read or writecycle. Data-in must be val­id t
main valid for t

DVEH

or t

prior to the end of write and re-

DVWH

EHDX

or t

afterward. G should

WHDX

be kept high during write cycles to avoid bus con­tention; although, if the output bus has been acti­vated by a low on E and G, a low on W will disable
the outputs t

WLQZ

after W falls.

9/17

M48Z512A, M48Z512AY

Figure 9. Write Enable Controlled, Write AC Waveforms

A0-A18

tAVEL

E

tAVWL

W

tWLQZ

DQ0-DQ7

Note: Output Enable (G) = High.

tAVAV
VALID

tAVWH

tWLWH

Figure 10. Chip Enable Controlled, Write AC Waveforms

DATA INPUT

tDVWH

tWHAX

tWHQX

tWHDX

AI01222

A0-A18

E

W

DQ0-DQ7

Note: Output Enable (G) = High.

10/17

tAVEL

tAVWL

tAVAV
VALID

tAVEH

tELEH

DATA INPUT

tDVEH

tEHAX

tEHDX

AI01223

M48Z512A, M48Z512AY

Figure 11. Supply Voltage Protection

V

CC

V

CC

0.1µF DEVICE

V

SS

AI02169

DATA RETENTION MODE

With valid VCCapplied,the M48Z512A/512AY op­erates as a conventional BYTEWIDE static
RAM. Should the supply voltage decay, the RAM
will automatically power-fail deselect, write pro­tecting itself tWPafter VCCfalls below V

PFD

.All
outputs become high impedance, and all inputs
are treated as ”don’t care.”

If power fail detection occurs during a valid ac­cess, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
tWP, write protection takes place. When VCCdrops
below VSO, the control circuit switches power to
the internal energy source which preserves data.

The internal coin cell will maintain data in the
M48Z512A/512AY after the initial application of
VCCforan accumulated period of at least 10years
when VCCis less than VSO. As system power re­turns and VCCrises above VSO, the battery is dis­connected, and the power supply is switched to
external VCC. Writeprotection continues for tERaf­ter VCCreaches V

to allow forprocessor stabi-

PFD

lization. After tER, normal RAM operation can
resume.

For more information on Battery Storage Liferefer
to the Application Note AN1012.

POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION

ICCtransients, including those produced by output
switching, can produce voltage fluctuations, re­sulting in spikes on the VCCbus. These transients
can be reduced if capacitors are used to store en­ergy, which stabilizes the VCCbus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by­pass capacitor value of 0.1µF (as shown in Figure

11) is recommended in order to provide the need­ed filtering.

In addition to transients that are caused by normal
SRAM operation,power cycling cangenerate neg­ative voltage spikes on VCCthat drive it to values
below VSSby as much as one Volt. These nega­tive spikes can cause data corruptionin the SRAM
while in battery backup mode. To protect from
these voltage spikes, itis recommeded to connect
a schottky diode from VCCto VSS(cathode con­nected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.

11/17

M48Z512A, M48Z512AY

Table 11. Ordering Information Scheme

Example: M48Z512AY -85 PM 1

Device Type

M48Z

Supply Voltage and Write Protect Voltage

512A = V
512AY = V

Speed

-70 = 70ns

-85 = 85ns

Package

PM = PMDIP32

(1)

CS

Temperature Range

1=0to70°C

(2)

= Extended Temperature

9

= 4.75V to 5.5V; V

CC

= 4.5V to 5.5V; V

CC

= 4.5V to 4.75V

PFD

= 4.2V to 4.5V

PFD

= Surface Mount Chip Set solution M40Z300 (SOH28) + M68Z512 (TSOP II 32)

Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number

”M4Zxx-BR00SH1” in plastic tube or ”M4Zxx-BR00SH1TR” in Tape & Reel form.

2. Contact Sales Offices for availability of Extended Temperature.
Caution: Donot place the SNAPHATbattery package ”M4Zxx-BR00SH1” inconductive foam since thiswilldrain the lithium button-cell

battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de­vice, please contact the STMicroelectronics Sales Office nearest to you.

12/17

M48Z512A, M48Z512AY

Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041

b 0.30 0.52 0.012 0.020

C 0.12 0.21 0.005 0.008

CP 0.10 0.004

D 20.82 21.08 0.820 0.830

e 1.27 – – 0.050 – –

E 11.56 11.96 0.455 0.471
E1 10.03 10.29 0.395 0.405

L 0.40 0.60 0.016 0.024

α 0° 5° 0° 5°

N32 32

mm inches

Figure 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline

D

16

17

A

CP

1

E1 E

32

eb

A2

C

A1

α

L

Drawing is not to scale.

TSOP-d

13/17

M48Z512A, M48Z512AY

Table 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α 0° 8° 0° 8°

N28 28

CP 0.10 0.004

mm inches

Figure 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline

A2

A

C

Be

CP

eB

D

N

E

H

LA1 α

1

SOH-A

Drawing is not to scale.

14/17

M48Z512A, M48Z512AY

Table14.M4Z32-BR00SH SNAPHAT Housing for120 mAh Battery, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 10.54 0.415
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Figure 14. M4Z32-BR00SH SNAPHAT Housing for 120mAh Battery, Package Outline

A1

A

eA

D

B

eB

E

SHZP-A

Drawing is not to scale.

A2

A3

L

15/17

M48Z512A, M48Z512AY

Table 15. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 9.27 9.52 0.365 0.375
A1 0.38 – 0.015 –

B 0.43 0.59 0.017 0.023

C 0.20 0.33 0.008 0.013
D 42.42 43.18 1.670 1.700

E 18.03 18.80 0.710 0.740
e1 2.29 2.79 0.090 0.110
e3 34.29 41.91 1.350 1.650
eA 14.99 16.00 0.590 0.630

L 3.05 3.81 0.120 0.150

S 1.91 2.79 0.075 0.110

N32 32

mm inches

Figure 15. PMDIP32 - 32 pin Plastic Module DIP, Package Outline

A1AL

S

Be1

e3

D

N

E

1

Drawing is not to scale.

C

eA

PMDIP

16/17

M48Z512A, M48Z512AY

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useofsuch information norfor any infringement of patents orother rights of third parties which may result from itsuse. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

2000 STMicroelectronics - All Rights Reserved



All other names are the property of their respective owners.

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

STMicroelectronics GROUP OF COMPANIES

http://www.st.com

17/17