Page 1
5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER® SRAM
Features
■ Integrated, ultra low power SRAM, power-fail
control circuit, and batteries
■ Conventional SRAM operation; unlimited
WRITE cycles
■ 10 years of data retention in the absence of
power
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
(V
= power-fail deselect voltage):
PFD
–M48Z2M1Y: V
4.2 V ≤ V
PFD
–M48Z2M1V: V
2.8 V ≤ V
■ Batteries are internally isolated until power is
PFD
applied
■ Pin and function compatible with JEDEC
standard 2 Mb x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
= 4.5 to 5.5 V;
CC
≤ 4.5 V
= 3.0 to 3.6 V;
CC
≤ 3.0 V
M48Z2M1Y
M48Z2M1V
Not recommended for new design
36
1
PLDIP36 module
June 2011 Doc ID 5135 Rev 6 1/20
This is information on a product still in production but not recommended for new designs.
www.st.com
1
Page 2
Contents M48Z2M1Y, M48Z2M1V
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 V
noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20 Doc ID 5135 Rev 6
Page 3
M48Z2M1Y, M48Z2M1V List of tables
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. PLDIP36 – 36-pin plastic DIP long module, package mechanical data . . . . . . . . . . . . . . . 16
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 5135 Rev 6 3/20
Page 4
List of figures M48Z2M1Y, M48Z2M1V
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Figure 6. WRITE enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. PLDIP36 – 36-pin plastic DIP long module, package outline . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20 Doc ID 5135 Rev 6
Page 5
M48Z2M1Y, M48Z2M1V Description
1 Description
The M48Z2M1Y/V ZEROPOWER® RAM is a non-volatile 16,777,216-bit, static RAM
organized as 2,097,152 words by 8 bits. The device combines two internal lithium batteries,
CMOS SRAMs and a control circuit in a plastic 36-pin DIP, long module.
The ZEROPOWER RAM replaces industry standard SRAMs. It provides the non-volatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 1. Logic diagram
V
CC
Table 1. Signal names
A0-A20 Address inputs
DQ0-DQ7 Data inputs / outputs
E Chip enable
G Output enable
W WRITE enable
V
CC
V
SS
NC Not connected internally
21
A0-A20
W
E
G
Supply voltage
Ground
M48Z2M1Y
M48Z2M1V
V
SS
8
DQ0-DQ7
AI02048
Doc ID 5135 Rev 6 5/20
Page 6
Description M48Z2M1Y, M48Z2M1V
Figure 2. DIP connections
Figure 3. Block diagram
E
VOLTAGE SENSE
SWITCHING
CIRCUITRY
V
CC
AND
NC
A20
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ2
V
SS
INTERNAL
BATTERIES
1
2
3
4
5
6
7
8
M48Z2M1Y
9
M48Z2M1V
10
11
12
13
14
15
16
17
18
POWER
E
V
36
CC
A19
35
34
NC
A15
33
A17
32
W
31
A13
30
A8
29
A9
28
27
A11
G
26
A10
25
E
24
DQ7
23
DQ6
22
DQ5DQ1
21
DQ4
20
DQ3
19
2048K x 8
SRAM ARRAY
AI02049
A0-A20
DQ0-DQ7
W
G
6/20 Doc ID 5135 Rev 6
V
SS
AI02050
Page 7
M48Z2M1Y, M48Z2M1V Operation modes
2 Operation modes
The M48Z2M1Y/V has its own power-fail detect circuit. The control circuitry constantly
monitors the single 5 V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operations brought on by low V
. As VCC falls below
CC
approximately 3 V, the control circuitry connects the batteries which sustain data until valid
power returns.
Table 2. Operating modes
Mode V
CC
E G W
DQ0-
DQ7
is out of
CC
Power
Deselect
WRITE V
READ V
3.0 to 3.6 V
4.5 to 5.5 V
READ V
Deselect VSO to V
Deselect ≤ V
1. See Table 10 on page 15 for details.
Note: X = V
or VIL; VSO = battery backup switchover voltage.
IH
2.1 READ mode
The M48Z2M1Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
16,777,216 locations in the static storage array. Thus, the unique address specified by the
21 address inputs defines which one of the 2,097,152 bytes of data is to be accessed. Valid
data will be available at the data I/O pins within address access time (t
address input signal is stable, providing that the E
access times are also satisfied. If the E
available after the later of chip enable access time (t
(t
). The state of the eight three-state data I/O signals is controlled by E and G. If the
GLQV
outputs are activated before t
until t
remain valid for output data hold time (t
access.
. If the address inputs are changed while E and G remain low, output data will
AVQ V
or
PFD
SO
(min)
(1)
X X High Z Standby
XVILD
V
IL
V
IH
V
IH
V
IH
IN
D
OUT
High Z Active
(1)
V
IH
IL
IL
IL
X X X High Z CMOS standby
X X X High Z Battery backup mode
) after the last
AVQ V
(chip enable) and G (output enable)
and G access times are not met, valid data will be
) or output enable access time
ELQV
, the data lines will be driven to an indeterminate state
AVQ V
) but will go indeterminate until the next address
AXQX
Active
Active
Figure 4. Address controlled, READ mode AC waveforms
A0-A20
DQ0-DQ7
Note: Chip enable (E
tAVAV
tAVQV
DATA VALID
) and output enable (G) = low, WRITE enable (W) = high.
Doc ID 5135 Rev 6 7/20
tAXQX
AI02051
Page 8
Operation modes M48Z2M1Y, M48Z2M1V
Figure 5. Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
tGLQV
VALID
tEHQZ
tGHQZ
DATA OUT
AI02052
A0-A20
tAVQV tAXQX
tELQV
E
tELQX
G
tGLQX
DQ0-DQ7
Note: WRITE enable (W
Table 3. READ mode AC characteristics
Symbol Parameter
t
AVAV
t
AVQ V
t
AXQX
t
EHQZ
t
ELQV
t
ELQX
t
GHQZ
t
GLQV
t
GLQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 100 pF or 50 pF (see Figure 9 on page 13).
3. CL = 5 pF (see Figure 9 on page 13).
READ cycle time 70 85 ns
(2)
Address valid to output valid 70 85 ns
(2)
Address transition to output transition 5 5 ns
(3)
Chip enable high to output Hi-Z 30 35 ns
(2)
Chip enable low to output valid 70 85 ns
(3)
Chip enable low to output transition 5 5 ns
(3)
Output enable high to output Hi-Z 25 35 ns
(2)
Output enable low to output valid 35 45 ns
(3)
Output enable low to output transition 5 5 ns
) = high.
(1)
M48Z2M1Y M48Z2M1V
Unit–70 –85
Min Max Min Max
8/20 Doc ID 5135 Rev 6
Page 9
M48Z2M1Y, M48Z2M1V Operation modes
2.2 WRITE mode
The M48Z2M1Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W
by the earlier rising edge of W
or E.
or E. A WRITE is terminated
The addresses must be held valid throughout the cycle. E
minimum of t
EHAX
cycle. Data-in must be valid t
t
EHDX
or t
afterward. G should be kept high during WRITE cycles to avoid bus
WHDX
contention; although, if the output bus has been activated by a low on E
will disable the outputs t
Figure 6. WRITE enable controlled, WRITE mode AC waveforms
A0-A20
E
W
DQ0-DQ7
Note: Output enable (G
from E or t
WLQZ
) = high.
or W must return high for
from W prior to the initiation of another READ or WRITE
WHAX
DVE H
or t
prior to the end of WRITE and remain valid for
DVW H
and G, a low on W
after W falls.
tAVAV
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
DATA INPUT
tDVWH
tWHAX
tWHQX
AI02053
Figure 7. Chip enable controlled, WRITE mode AC waveforms
A0-A20
E
W
DQ0-DQ7
Note: Output enable (G
) = high.
tAVAV
VALID
tAVEH
tAVEL
tELEH
tAVWL
DATA INPUT
tDVEH
tEHAX
tEHDX
Doc ID 5135 Rev 6 9/20
AI02054
Page 10
Operation modes M48Z2M1Y, M48Z2M1V
Table 4. WRITE mode AC characteristics
M48Z2M1Y M48Z2M1V
Symbol Parameter
(1)
Unit–70 –85
Min Max Min Max
t
AVAV
t
AVEH
t
AVEL
t
AVW H
t
AVW L
t
DVEH
t
DVW H
t
EHAX
t
EHDX
t
ELEH
t
WHAX
t
WHDX
t
WHQX
t
WLQZ
t
WLWH
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6V (except where
noted).
2. CL = 5 pF (see Figure 9 on page 13).
goes low simultaneously with W going low, the outputs remain in the high impedance state.
3. If E
WRITE cycle time 70 85 ns
Address valid to chip enable high 65 75 ns
Address valid to chip enable low 0 0 ns
Address valid to WRITE enable high 65 75 ns
Address valid to WRITE enable low 0 0 ns
Input valid to chip enable high 30 35 ns
Input valid to WRITE enable high 30 35 ns
Chip enable high to address transition 15 15 ns
Chip enable high to input transition 10 15 ns
Chip enable low to chip enable high 55 75 ns
WRITE enable high to address transition 5 5 ns
WRITE enable high to input transition 0 0 ns
(2)(3)
WRITE enable high to output transition 5 5 ns
(2)(3)
WRITE enable low to output Hi-Z 25 30 ns
WRITE enable pulse width 55 65 ns
2.3 Data retention mode
With valid VCC applied, the M48Z2M1Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself t
inputs are treated as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time t
place. When V
source which preserves data.
The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of
V
for an accumulated period of at least 10 years when VCC is less than VSO. As system
CC
power returns and V
supply is switched to external V
V
to allow for processor stabilization. After tER, normal RAM operation can resume.
PFD
For more information on battery storage life refer to the application note AN1012.
10/20 Doc ID 5135 Rev 6
after VCC falls below V
WP
drops below VSO, the control circuit switches power to the internal energy
CC
rises above VSO, the batteries are disconnected, and the power
CC
. Write protection continues for t
CC
. All outputs become high impedance, and all
PFD
, write protection takes
WP
after VCC reaches
ER
Page 11
M48Z2M1Y, M48Z2M1V Operation modes
2.4 VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 8) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from V
to VSS (cathode connected to VCC, anode to VSS). Schottky diode
CC
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 8. Supply voltage protection
V
CC
bus. These transients can be reduced if
CC
that drive it to values below VSS by as much as
CC
V
CC
bus. The energy stored in the
CC
0.1µF DEVICE
V
SS
AI02169
Doc ID 5135 Rev 6 11/20
Page 12
Maximum ratings M48Z2M1Y, M48Z2M1V
3 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
T
A
T
STG
T
BIAS
T
SLD
V
IO
V
CC
I
O
P
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. Furthermore, the devices
shall not be exposed to IR reflow nor preheat cycles (as performed as part of wave soldering). ST
recommends the devices be hand-soldered or placed in sockets to avoid heat damage to the batteries.
Ambient operating temperature 0 to 70 °C
Storage temperature (VCC off) –40 to 85 °C
Temperature under bias –40 to 85 °C
(1)
Lead solder temperature for 10 seconds 260 °C
Input or output voltages
Supply voltage
M48Z2M1Y –0.3 to 7 V
M48Z2M1V –0.3 to 4.6 V
M48Z2M1Y –0.3 to 7 V
M48Z2M1V –0.3 to 4.6 V
Output current 20 mA
Power dissipation 1 W
D
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
12/20 Doc ID 5135 Rev 6
Page 13
M48Z2M1Y, M48Z2M1V DC and AC parameters
4 DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 6. Operating and AC measurement conditions
Parameter M48Z2M1Y M48Z2M1V Unit
Supply voltage (VCC) 4.5 to 5.5 3.0 to 3.6 V
Ambient operating temperature (T
Load capacitance (CL) 100 50 pF
Input rise and fall times ≤ 5 ≤ 5ns
Input pulse voltages 0 to 3 0 to 3 V
Input and output timing ref. voltages 1.5 1.5 V
Note: Output Hi-Z is defined as the point where data is no longer driven.
) 0 to 70 0 to 70 °C
A
Figure 9. AC testing load circuit
DEVICE
UNDER
TEST
1kΩ
CL includes JIG capacitance
5V
1.9kΩ
CL = 100pF or 5pF (Y)
OUT
50pF or 5pF (V)
AI07816
Doc ID 5135 Rev 6 13/20
Page 14
DC and AC parameters M48Z2M1Y, M48Z2M1V
Table 7. Capacitance
Symbol Parameter
(1)(2)
Min Max Unit
C
IN
C
IO
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested.
2. Outputs deselected.
3. At 25 °C.
Input capacitance - 40 pF
(3)
Input / output capacitance - 40 pF
Table 8. DC characteristics
M48Z2M1Y M48Z2M1V
Min Max Min Max
±4 ±4 µA
±4 ±4 µA
140 70 mA
10 2 mA
≤ V
IH
(1)
CC
CC
Sym Parameter Test condition
(2)
Input leakage current 0 V ≤ VIN ≤ V
I
LI
(2)
I
Output leakage current 0 V ≤ V
LO
Supply current
I
CC
Supply current (standby) TTL E = V
I
CC1
Supply current (standby) CMOS E ≥ VCC – 0.2 V 8 1 mA
I
CC2
OUT
E
= VIL,
Outputs open
VILInput low voltage –0.3 0.8 –0.3 0.6 V
VIHInput high voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
Output low voltage IOL = 2.1 mA 0.4 0.4 V
V
OL
V
Output high voltage IOH = –1 mA 2.4 2.2 V
OH
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. Outputs deselected.
Unit
14/20 Doc ID 5135 Rev 6
Page 15
M48Z2M1Y, M48Z2M1V DC and AC parameters
Figure 10. Power down/up mode AC waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
tF
tFB
tWP
E
tDR
DON'T CARE
tR
tRB
tER
RECOGNIZEDRECOGNIZED
OUTPUTS
VAL ID VALID
(PER CONTROL INPUT)
HIGH-Z
(PER CONTROL INPUT)
AI01031
Table 9. Power down/up AC characteristics
Symbol Parameter
t
ER
(2)
t
F
(3)
t
FB
t
R
t
WP
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. V
3. V
(max) to V
PFD
until 200 µs after V
PFD
E recovery time 40 120 ms
V
(max) to V
PFD
V
(min) to VSO VCC fall time
PFD
V
(min) to V
PFD
(min) VCC fall time 300 µs
PFD
(max) VCC rise time 10 µs
PFD
Write protect time from VCC = V
(min) fall time of less than tF may result in deselection/write protection not occurring
PFD
passes V
CC
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
(min).
(1)
PFD
Min Max Unit
M48Z2M1Y 10 µs
M48Z2M1V 150 µs
M48Z2M1Y 40 150 µs
M48Z2M1V 40 250 µs
Table 10. Power down/up trip points DC characteristics
Symbol Parameter
(1)(2)
Min Typ Max Unit
V
t
V
DR
Power-fail deselect voltage
PFD
Battery backup switchover voltage
SO
(3)
Expected data retention time 10 YEARS
1. All voltages referenced to VSS.
2. Valid for ambient operating temperature: T
noted).
3. At 25 °C; VCC = 0 V.
Doc ID 5135 Rev 6 15/20
M48Z2M1Y 4.2 4.3 4.5 V
M48Z2M1V 2.8 2.9 3.0 V
M48Z2M1Y 3.0 V
M48Z2M1V 2.45 V
= 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
A
Page 16
Package mechanical data M48Z2M1Y, M48Z2M1V
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 11. PLDIP36 – 36-pin plastic DIP long module, package outline
S
Note: Drawing is not to scale.
A1AL
B
e3
D
N
1
e1
E
eA
C
PMDIP
Table 11. PLDIP36 – 36-pin plastic DIP long module, package mechanical data
Symb
Typ Mi n M ax Typ Mi n Max
A 9.27 9.52 0.3650 0.3748
A1 0.38 0.0150
B 0.43 0.59 0.0169 0.0232
C 0.20 0.33 0.0079 0.0130
D 52.58 53.34 2.0701 2.1000
E 18.03 18.80 0.7098 0.7402
e1 2.30 2.81 0.0906 0.1106
e3 43.18 1.7
eA 14.99 16.00 0.5902 0.6299
L 3.05 3.81 0.1201 0.1500
S 4.45 5.33 0.1752 0.2098
N36 36
mm inches
16/20 Doc ID 5135 Rev 6
Page 17
M48Z2M1Y, M48Z2M1V Part numbering
6 Part numbering
Table 12. Ordering information scheme
Example: M48Z 2M1Y –70 PL 1
Device type
M48Z
Supply voltage and write protect voltage
(1)
2M1Y
2M1V
Speed
–70 = 70 ns (Y)
–85 = 85 ns (V)
= VCC = 4.5 to 5.5 V; V
(1)
= VCC = 3.0 to 3.6 V; V
= 4.2 to 4.5 V
PFD
= 2.8 to 3.0 V
PFD
Package
PL = PLDIP36
Temperature range
1 = 0 to 70°C
9 = extended temperature
Shipping method
®
blank = ECOPACK
1. Not recommended for new design. Contact ST sales office for availability.
package, tubes
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 5135 Rev 6 17/20
Page 18
Environmental information M48Z2M1Y, M48Z2M1V
7 Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
18/20 Doc ID 5135 Rev 6
Page 19
M48Z2M1Y, M48Z2M1V Revision history
8 Revision history
Table 13. Document revision history
Date Revision Changes
Jul-1999 1 First issue
31-Aug-2000 2 From preliminary data to datasheet
20-Mar-2002 3
29-May-2002 3.1 Modified “V
28-Mar-2003 3.2
02-Jul-2003 3.3 Changed characteristic (Ta bl e 8 )
18-Feb-2005 4 Reformatted; IR reflow update (Ta bl e 5 )
02-Aug-2010 5
24-Jun-2011 6
Reformatted; temperature information added to tables (Ta ble 7 , 8, 3, 4,
9, 10)
noise and negative going transients” text
CC
Remove 5 V/5%, add 3 V part (Figure 1, 2, 9; Ta b le 5 , 6, 8, 2, 3, 4, 9,
10, 12)
®
Updated Features, Section 3, Tab l e 1 2 ; added ECOPACK
text to
Section 5; added Section 7: Environmental information.
Devices are not recommended for new design (updated cover page,
Ta bl e 1 2 ); updated footnote of Table 5: Absolute maximum ratings;
updated Section 7: Environmental information.
Doc ID 5135 Rev 6 19/20
Page 20
M48Z2M1Y, M48Z2M1V
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20/20 Doc ID 5135 Rev 6
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