Page 1
1/23June 2000
M48T513Y
M48T513V
3.3V-5V 4 Mbit (512Kb x8) TIMEKEEPERSRAM
■ INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY, andCRYSTAL
■ YEAR 2000 COMPLIANT
■ BCD CODED CENTURY, YEAR, MONTH,
DAY, DATE, HOURS, MINUTES, and
SECONDS
■ BATTERY LOW WARNING FLAG
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■ TWO WRITE PROTECT VOLTAGES:
(V
PFD
= Power-fail Deselect Voltage)
– M48T513Y: 4.2V ≤ V
PFD
≤ 4.5V
– M48T513V: 2.7V ≤ V
PFD
≤ 3.0V
■ CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION for HIGH ACCURACY
APPLICATIONS
■ 10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE of POWER
■ SELF CONTAINED BATTERY and CRYSTAL
in DIP PACKAGE
■ MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
■ PROGRAMMABLE ALARM OUTPUT ACTIVE
in BATTERY BACK-UP MODE
■ SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 44-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY and CRYSTAL
■ SNAPHAT
HOUSING (BATTERY/CRYSTAL)
IS REPLACEABLE
Figure 1. Logic Diagram
AI02308
19
A0-A18 DQ0-DQ7
V
CC
M48T513Y
M48T513V
G
V
SS
8
E
W RST
IRQ/FT
RSTIN
WDI
32
1
SOH44
Surface Mount Chip Set Solution (CS)
SNAPHAT (SH)
Battery
PMDIP32(PM)
Module
32
1
TSOP II 32
(10 x 20mm)
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M48T513Y, M48T513V
2/23
Figure 2. DIP Connections
V
SS
V
CC
AI02307
M48T513Y
M48T513V
10
1
2
5
6
7
8
9
11
12
13
16
17
18
30
29
26
25
24
23
22
21
20
19
3
4
28
27
32
31
14
15
34
33
36
35
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5DQ1
DQ2
DQ3
DQ4
DQ6
A16
A18
A12
A14
W
A17
RSTIN
RST
IRQ/FT
WDI
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. Thisis a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature 0 to 70 °C
T
STG
Storage Temperature (VCCOff, Oscillator Off)
–40 to 85 °C
V
IO
Input or Output Voltages –0.3 to VCC+0.3 V
V
CC
Supply Voltage
M48T513Y –0.3 to 7.0 V
M48T513V –0.3 to 4.6 V
I
O
Output Current 20 mA
P
D
Power Dissipation 1 W
DESCRIPTION
The M48T513Y/VTIMEKEEPER RAM is a 512Kb
x 8 non-volatile static RAM and real time clock,
with programmable alarms and a watchdog timer.
The special DIP package provides a fully integrated battery back-up memoryand real time clock solution. TheM48T513Y/V directly replaces industry
standard 512Kb x 8 SRAM. It also provides the
non-volatility of Flash without any requirement for
special write timing or limitations on the number of
writes that can be performed.
Table 1. Signal Names
A0-A18 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
E Chip Enable Input
G Output Enable Input
W Write Enable Input
WDI Watchdog input
RST Reset Output (open drain)
RSTIN Reset Input
IRQ/FT
Interrupt / Frequency Test
Output (open drain)
V
CC
Supply Voltage
V
SS
Ground
For surface mount environments ST provides a
Chip Set solution consisting of a 44 pin 330mil
SOIC TIMEKEEPER Supervisor (M48T201V/Y)
and a 32 pin TSOP Type II (10 x 20mm) LPSRAM
(M68Z512/W) packages.
The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery.
Page 3
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M48T513Y, M48T513V
Figure 3. Block Diagram
AI02584
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
V
PFD
V
CC
V
SS
32,768
Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
16 x
8
TIMEKEEPER
REGISTERS
524,272 x
8
SRAM ARRAY
A0-A18
DQ0-DQ7
E
W
G
POWER
RST
IRQ/FT
WDI
RSTIN
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the hightemperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Txx-BR12SH1”.
Figure 3 illustratesthestaticmemoryarray andthe
quartz controlled clock oscillator. The clock locations contain the century, year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year), 30, and 31 day
months are made automatically. The nine clock
bytes (7FFFFh-7FFF9h and 7FFF1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT read/write memory cells
within the static RAM array.
The M48T513Y/V includes a clock control circuit
which updates the clock bytes with current information once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
7FFF8his the clock control register.Thisbyte controls user access to the clock information and also
stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the WatchdogSteering bit(WDS).Bytes 7FFF6h-7FFF2h include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century information.Byte 7FFF0h contains additionalflaginformation pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T513Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
VCCis out of tolerance, the circuit write protects
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of unpredictable system operation. As VCCfalls, the
control circuitry automatically switches to the battery, maintaining data and clock operation until
valid power is restored.
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M48T513Y, M48T513V
4/23
Figure 4. Hardware Hookup for SMT Chip Set
(1)
Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z512/W atwww.st.com.
2. For 5V, M48T129Y (M48T201Y + M68Z512). For 3.3V, M48T129V (M48T201V + M68Z512W).
3. SNAPHAT Top ordered separately.
AI03633
32,768
Hz
CRYSTAL
LITHIUM
CELL
A0-A18
DQ0-DQ7
E
V
CC
W
G
WDI
RSTIN1
RSTIN2
V
SS
E
W
G
V
CC
V
SS
A0-A18
DQ0-DQ7
0.1µF
0.1µF
5V
ECON
GCON
RST
IRQ/FT
SQW
M48T201Y/V
(2)
M68Z512/W
(2)
V
OUT
SNAPHAT
(3)
BATTERY/CRYSTAL
READ MODE
The M48T513Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Address Inputs defines which one of the 524,272
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within t
AVQV
(Address Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latterof the Chip Enable Access Times (t
ELQV
)
or Output Enable Access Time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address Inputs are changed while E and G remain active,
output data will remain valid for t
AXQX
(Output
Data Hold Time) but will go indeterminate until the
next Address Access.
WRITE MODE
The M48T513Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a write is referencedfrom the latter occurring falling edgeof W orE. A write is terminated
by the earlierrisingedge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of t
EHAX
fromChip
Enable or t
WHAX
from Write Enable prior to the initiation of another read or write cycle. Data-in must
be valid t
DVWH
prior to the end of write and remain
valid for t
WHDX
afterward. G should be kept high
during write cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G a low on Wwill disable the outputs
t
WLQZ
after W falls.
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M48T513Y, M48T513V
Table 3. Operating Modes
(1)
Note: 1. X = VIHor V
IL;VSO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Mode V
CC
E G W DQ0-DQ7 Power
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
V
IH
X X High Z Standby
Write V
IL
XVILD
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z Active
Deselect
V
SO
to V
PFD
(min)
(2)
X X X High Z CMOS Standby
Deselect
≤ V
SO
(2)
X X X High Z Battery Back-up Mode
Table 4. AC Measurement Conditions
Note thatOutput Hi-Z is defined as the point wheredata is no longer
driven.
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
referred to as BiPORT TIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD.
DATA RETENTION MODE
With valid VCCapplied, the M48T513Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automatically deselect, write protecting itself when V
CC
falls between V
PFD
(max), V
PFD
(min) window. All
outputs become high impedance and all inputsare
treated as ”don’t care”.
Note: Apower failureduring a write cycle may corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V
PFD
(min), the memory will be
in a write protected state, provided the VCCfall
time is not less than tF. The M48T513Y/V may respond to transient noise spikes on VCCthat cross
into the deselect window during the time the device issampling VCC. Therefore, decouplingof the
power supply lines is recommended.
When VCCdrops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T513Y/V for
an accumulated period of at least 10 years atroom
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
t
REC
after VCCreaches V
PFD
(max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
TIMEKEEPER REGISTERS
The M48T513Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations which contain external (user
accessible) andinternal copies ofthe data (usually
Figure 5. AC Testing Load Circuit
Note: Excluding open drain output pins.
AI01803C
CL= 100pF
CLincludes JIG capacitance
650Ω
DEVICE
UNDER
TEST
1.75V
Page 6
M48T513Y, M48T513V
6/23
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted beforeclock data is read to prevent reading
data in transition. Because the BiPORT TIMEKEEPER cellsin the RAM array are only data registers, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register (7FFF8h). As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count;thatis,the day,date, and time that were
current at the moment the halt command was issued. All ofthe TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second after the READ bit is reset to a’0’.
Setting the Clock
Bit D7 of the Control Register (7FFF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD
format (see Table 11).
Resetting the WRITE bit to a ’0’then transfers the
values of all time registers (7FFFFh-7FFF9h,
7FFF1h) to theactual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE bit isreset, thenextclockupdate willoccur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within 7FFF9h. Setting it to
a ’1’ stops the oscillator. When reset to a ’0’, the
M48T513Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE bit
when setting orresetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
SETTING ALARM CLOCK
Registers 7FFF6h-7FFF2h contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every month, day,
hour, minute, or second. It can also be programmed to go off while the M48T513Y/V is in the
battery back-upto serveasa systemwake-upcall.
Bits RPT5-RPT1 putthe alarm in the repeat mode
of operation. Table 12 shows the possible configurations.Codes not listedin the tabledefaultto the
once per second mode toquickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggleChip
Enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag)is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date register and RPT1-4.
The IRQ/FT output is cleared by a read to the
Flags register as shown in Figure 12. A subsequent read of the Flags register will reset the
Alarm Flag (D6; Register 7FFF0h).
The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable)and AFE areset. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. Theuser can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T513Y/V was in the deselect mode
during power-up. Figure 13 illustratesthe back-up
mode alarm timing.
WATCHDOG TIMER
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
7FFF7h. BitsBMB4-BMB0 store abinarymultiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
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7/23
M48T513Y, M48T513V
Table 5. Capacitance
(1)
(TA=25°C, f = 1 MHz)
Note: 1. Effective capacitance measured with power supply at 5V (M48T513Y) or 3.3V (M48T513V). Sampled only, not 100% tested.
2. Outputs deselected.
Table 6A. DC Characteristics - M48T513Y
(TA= 0 to 70 °C; VCC= 4.5V to 5.5V)
Note: 1. Outputs deselected.
Table 6B. DC Characteristics - M48T513V
(TA= 0 to 70 °C; VCC= 3.0V to 3.6V)
Note: 1. Outputs deselected.
Symbol Parameter Test Condition Min Max Unit
C
IN
Input Capacitance
V
IN
=0V
20 pF
C
IO
(2)
Input / Output Capacitance
V
OUT
=0V
20 pF
Symbol Parameter Test Condition Min Max Unit
I
LI
(1)
Input Leakage Current 0V ≤ VIN≤ V
CC
±2 µA
I
LO
(1)
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
±2 µA
I
CC
Supply Current Outputs open 115 mA
I
CC1
Supply Current (Standby) TTL
E=V
IH
8mA
I
CC2
Supply Current (Standby) CMOS
E=V
CC
– 0.2V
4mA
V
IL
Input Low Voltage –0.3 0.8 V
V
IH
Input High Voltage 2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4 V
V
OH
Output High Voltage
I
OH
= –1mA
2.4 V
Symbol Parameter Test Condition Min Max Unit
I
LI
(1)
Input Leakage Current
0V ≤ V
IN
≤ V
CC
±2 µA
I
LO
(1)
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
±2 µA
I
CC
Supply Current Outputs open 60 mA
I
CC1
Supply Current (Standby) TTL E = V
IH
4mA
I
CC2
Supply Current (Standby) CMOS
E=V
CC
– 0.2V
3mA
V
IL
Input Low Voltage –0.3 0.4 V
V
IH
Input High Voltage 2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage IOL= 2.1mA 0.4 V
V
OH
Output High Voltage
I
OH
= –1mA
2.2 V
Page 8
M48T513Y, M48T513V
8/23
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(TA= 0 to 70 °C)
Note: 1. All voltages referenced to VSS.
2. At 25°C.
Table 8. Power Down/Up AC Characteristics
(TA= 0 to 70 °C)
Note: 1. V
PFD
(max) to V
PFD
(min)fall time ofless than tFmayresult in deselection/write protection not occurringuntil 200ms after VCCpass-
es V
PFD
(min).
2. V
PFD
(min) to VSSfall time of less than tFBmay cause corruption of RAM data.
Symbol Parameter Min Typ Max Unit
V
PFD
Power-fail Deselect Voltage
M48T513Y 4.2 4.35 4.5 V
M48T513V 2.7 2.9 3.0 V
V
SO
Battery Back-up Switchover Voltage
M48T513Y 3.0 V
M48T513V
V
PFD
–100mV
t
DR
(2)
Expected Data Retention Time 10 YEARS
Symbol Parameter Min Max Unit
t
F
(1)
V
PFD
(max) to V
PFD
(min) VCCFall Time
300 µs
t
FB
(2)
V
PFD
(min) to VSSVCCFall Time
M48T513Y 10 µs
M48T513V 150 µs
t
R
V
PFD
(min) to V
PFD
(max) VCCRise Time
0 µs
t
RB
VSSto V
PFD
(min) VCCRise Time
1 µs
t
REC
V
PFD
(max) to RST High
40 200 ms
Figure 6. Power Down/Up Mode AC Waveforms
AI01805
V
CC
INPUTS
OUTPUTS
DON’T CARE
HIGH-Z
tF
tFB
tR
tRB
VALID VALID
RECOGNIZEDRECOGNIZED
V
PFD
(max)
V
PFD
(min)
V
SO
tREC
RST
Page 9
9/23
M48T513Y, M48T513V
Table 9. Read Mode AC Characteristics
(TA= 0 to 70 °C)
Note: 1. CL= 100pF.
2. C
L
= 5pF.
Symbol Parameter
M48T513Y M48T513V
Unit-70 -85
Min Max Min Max
t
AVAV
Read Cycle Time 70 85 ns
t
AVQV
(1)
Address Valid to Output Valid 70 85 ns
t
ELQV
(1)
Chip Enable Low to Output Valid 70 85 ns
t
GLQV
(1)
Output Enable Low to Output Valid 40 55 ns
t
ELQX
(2)
Chip Enable Low to Output Transition 5 5 ns
t
GLQX
(2)
Output Enable Low to Output Transition 5 5 ns
t
EHQZ
(2)
Chip Enable High to Output Hi-Z 25 30 ns
t
GHQZ
(2)
Output Enable High to Output Hi-Z 25 30 ns
t
AXQX
(1)
Address Transition to Output Transition 10 5 ns
Figure 7. Address Controlled, Read Mode AC Waveforms
AI02324
tAVAV
tAVQV
tAXQX
DATA VALID
A0-A16
DQ0-DQ7
VALID
DATA VALID
Page 10
M48T513Y, M48T513V
10/23
Table 10. Write Mode AC Characteristics
(TA= 0 to 70 °C)
Note: 1. CL= 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol Parameter
M48T513Y M48T513V
Unit-70 -85
Min Max Min Max
t
AVAV
Write Cycle Time 70 85 ns
t
AVWL
Address Valid to Write Enable Low 0 0 ns
t
AVEL
Address Valid to Chip Enable Low 0 0 ns
t
WLWH
Write Enable Pulse Width 50 60 ns
t
ELEH
Chip Enable Low to Chip Enable High 55 65 ns
t
WHAX
Write Enable High to Address Transition 5 5 ns
t
EHAX
Chip Enable High to Address Transition 10 15 ns
t
DVWH
Input Valid to WriteEnable High 30 35 ns
t
DVEH
Input Valid to Chip Enable High 30 35 ns
t
WHDX
Write Enable High to Input Transition 5 5 ns
t
EHDX
Chip Enable High to Input Transition 10 15 ns
t
WLQZ
(1, 2)
Write Enable Low to Output Hi-Z 25 30 ns
t
AVWH
Address Valid to Write Enable High 60 70 ns
t
AVEH
Address Valid to Chip Enable High 60 70 ns
t
WHQX
(1, 2)
Write Enable High to Output Transition 5 5 ns
If theprocessor does not reset the timer withinthe
specified period, the M48T513Y/V sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by
reading the FlagsRegister (Address7FFF0h). The
most significant bitof the Watchdog Register is the
Watchdog Steering Bit (WDS). When set to a ’0’,
the watchdog will activate the IRQ/FT pin when
timed-out. WhenWDS is set to a ’1’, the watchdog
will output a negative pulse on the RST pin for 40
to 200 ms. The Watchdog register and the FT bit
will reset to a ’0’at the end of a Watchdog time-out
when the WDS bit is set toa ’1’. The watchdog timer can be reset by two methods: 1) a transition
(high-to-low or low-to-high) can be applied to the
Watchdog Input pin (WDI) or 2) the microprocessor can perform a write of the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSSif not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effectively restarting the count-down cycle.
Should the watchdog timer time-out,and theWDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
7FFF0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
POWER-ON RESET
The M48T513Y/V continuously monitors VCC.
When VCCfalls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for 40 to 200ms after VCCpasses V
PFD
.
The RSTpin is anopen drain output andan appropriate pull-up resistor to VCCshould be chosen to
control the rise time.
Page 11
11/23
M48T513Y, M48T513V
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
Figure 9. Write Enable Controlled, Write AC Waveforms
AI01197
tAVAV
tAVQV tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
AI02382
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A16
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
Page 12
M48T513Y, M48T513V
12/23
RESET INPUT (RSTIN)
The M48T513Y/V provides an independent input
which can generate an output reset. The duration
and function of thisreset is identical to a reset generated by a power cycle. Table 13 and Figure 14
illustrate the AC reset characteristics of this function. Pulses shorter than tRwill not generate a reset condition. RSTIN is internally pulled up to V
CC
through a 100KΩ resistor.
CALIBRATING THE CLOCK
The M48T513Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about * 1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than 4ppmat 25°C. The oscillation rate of crystals
changes with temperature. The M48T513Y/V design employs periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage,
as shown in Figure 11.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded intothefive Calibrationbits found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bitsoccupythe fivelower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; ’1’indicates positive
calibration, ’0’ indicates negative calibration. Calibration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles.
If a binary ’1’ is loaded into the register, only the
first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration
register. Assuming that the oscillator is running at
exactly32,768Hz,each of the31increments inthe
Calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month. Figure
11 illustrates a TIMEKEEPER calibration waveform.
Two methods are available for ascertaining how
much calibration a given M48T513Y/V may require. The first involves setting the clock, letting it
run for a month and comparing it to a known accurate reference and recording deviation over a fixed
period of time.
Calibration values, including the number of seconds lost or gained in a given period, canbe found
in Application Note: TIMEKEEPER CALIBRATION.
Figure 10. Chip Enable Controlled, Write AC Waveforms
AI02582
tAVAV
tEHAX
tDVWH
A0-A16
E
W
DQ0-DQ7
VALID
tAVEL
tAVWL
tELEH
tWHDX
DATA INPUT
Page 13
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M48T513Y, M48T513V
Figure 11. CalibrationWaveform
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
Table 11. TIMEKEEPER Register Map
Address
Data
Function/Range
BCD Format
D7 D6 D5 D4 D3 D2 D1 D0
7FFFFh 10 Years Year Year 00-99
7FFFEh 0 0 0 10 M Month Month 01-12
7FFFDh 0 0 10 Date Date Date 01-31
7FFFCh 0 FT 0 0 0 Day of Week Day 01-07
7FFFBh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23
7FFFAh 0 10 Minutes Minutes Minutes 00-59
7FFF9h ST 10 Seconds Seconds Seconds 00-59
7FFF8h W R S Calibration Control
7FFF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
7FFF6h AFE 0 ABE Al 10M Alarm Month A Month 01-12
7FFF5h RPT4 RPT5 Al 10 Date Alarm Date AlDate 01-31
7FFF4h RPT3 0 Al 10 Hours Alarm Hours A Hours 00-23
7FFF3h RPT2 Al 10Minutes Alarm Minutes A Min 00-59
7FFF2h RPT1 Al 10 Seconds Alarm Seconds A Sec 00-59
7FFF1h 1000 Year 100 Year Century 00-99
7FFF0h WDF AF 0 BL Y Y Y Y Flag
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITEBit
ST = STOP Bit
0 = Must be set to ’0’
Y = ’1’or ’0’
BL = Battery Low
AF = Alarm Flag
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm FlagEnable
ABE = Alarm in BatteryBack-up Mode Enable
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF =Watchdog Flag
Page 14
M48T513Y, M48T513V
14/23
Figure 12. Alarm Interrupt Reset Waveform
Figure 13. Back-up Mode Alarm Waveforms
AI02581
AD0-AD7
ACTIVE FLAG BIT
ADDRESS 1FF0h
IRQ/FT
HIGH-Z
15ns Min
AI01678C
V
CC
IRQ/FT
HIGH-Z
V
PFD
(max)
V
PFD
(min)
AFE bit in InterruptRegister
AF bit in Flags Register
HIGH-Z
V
SO
tREC
Page 15
15/23
M48T513Y, M48T513V
Table 12. Alarm Repeat Mode
RPT4 RPT3 RPT2 RPT1 Alarm Activated
1111Once perSecond
1110Once perMinute
1100Once perHour
1000Once perDay
1000Once perMonth
This allows the designer to give the end user the
ability tocalibrate the clock as the environment requires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop bit (ST, D7 of 7FFF9h) is ’0’, the Frequency
Test bit (FT, D6 of 7FFFCh) is ’1’, the Alarm Flag
Enable bit (AFE, D7 of 7FFF6h) is ’0’, and the
Watchdog Steering bit (WDS, D7 of 7FFF7h) is ’1’
or the WatchdogRegister (7FFF7h = 0) is reset.
Note: A 4 second settling time must be allowed
before reading the 512Hz output.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequencyshift atthe test
temperature. For example, a reading of
512.010124Hz would indicatea +20ppm oscillator
frequency error, requiringa–10(WR001010)to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency testoutput frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control therise time.The FT bit is cleared on power-up.
BATTERY LOW WARNING
The M48T513Y/V automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 7FFF0h, will be asserted if the battery
voltage is found to be less than approximately
2.5V.
If a battery low is generated during apower-up se-
quence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCCis
supplied.
The M48T513Y/V only monitors the battery when
a nominal VCCisapplied to the device. Thus applications which require extensive durations in the
battery back-up modeshould be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
POWER-ON DEFAULTS
Upon application of power to the device, the following register bits are set to a ’0’ state: WDS,
BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.
Page 16
M48T513Y, M48T513V
16/23
Table 13. Reset AC Characteristics
(TA= 0 to 70 °C, VCC= 3.0V to 3.6V or VCC= 4.5V to 5.5V)
Note: 1. CL= 5pF (see Figure 5)
Symbol Parameter Min Max Unit
t
R
RSTIN Low to RST Low 20 100 ms
t
RHRZ
(1)
RSTIN High to RST Hi-Z 40 200 ms
Figure 14. RSTIN Timing Waveform
AI02585
tRHRZ
RSTIN
RST
tR
Hi-Z Hi-Z
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
ICCtransients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCCbus. These transients
can be reduced if capacitors are used to store energy, which stabilizes the VCCbus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 15) is
recommended in order to provide the needed filtering. In addition to transients that are caused by
normal SRAMoperation, powercyclingcangenerate negative voltage spikes on VCCthat drive it to
values below VSSby as much as one volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, ST recommends connecting a schottky diode from VCCtoVSS(cathode
connected to VCC, anode to VSS). (Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).
Figure 15. Supply Voltage Protection
AI02169
V
CC
0.1µF DEVICE
V
CC
V
SS
Page 17
17/23
M48T513Y, M48T513V
Table 14. Ordering Information Scheme
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which isordered separately under the part number
”M4Txx-BR12SH1” in plastic tube or ”M4Txx-BR12SH1TR” in Tape & Reel form.
Caution: Do not place theSNAPHATbatterypackage ”M4Txx-BR12SH1” inconductive foam since thiswilldrain the lithiumbutton-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Example: M48T513Y -70 PM 1
Device Type
M48T
SupplyVoltage and Write Protect Voltage
513Y = V
CC
= 4.5V to 5.5V; V
PFD
= 4.2V to 4.5V
513V = V
CC
= 3.0V to 3.6V; V
PFD
= 2.7V to 3.0V
Speed
-70 = 70ns
-85 = 85 ns
Package
PM = PMDIP32
CS
(1)
=SurfaceMountChipSetsolution M48T201Y/V (SOH44)+ M68Z512/W (TSOP32)
Temperature Range
1=0to70°C
Table 15. Revision History
Date Revision Details
April 2000 Chipset datasheet First Issue
06/20/00 From Preliminary Data to data Sheet
Page 18
M48T513Y, M48T513V
18/23
Table 16. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 9.27 9.52 0.365 0.375
A1 0.38 – 0.015 –
B 0.43 0.59 0.017 0.023
C 0.20 0.33 0.008 0.013
D 42.42 43.18 1.670 1.700
E 18.03 18.80 0.710 0.740
e1 2.29 2.79 0.090 0.110
e3 34.29 41.91 1.350 1.650
eA 14.99 16.00 0.590 0.630
L 3.05 3.81 0.120 0.150
S 1.91 2.79 0.075 0.110
N32 32
Figure 16. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
Drawing is not to scale.
PMDIP
A1AL
Be1
D
E
N
1
eA
e3
S
C
Page 19
19/23
M48T513Y, M48T513V
Table 17. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data
Symbol
mm inch
Typ Min Max Typ Min Max
A 1.20 0.047
A1 0.05 0.15 0.002 0.006
A2 0.95 1.05 0.037 0.041
b 0.30 0.52 0.012 0.020
C 0.12 0.21 0.005 0.008
CP 0.10 0.004
D 20.82 21.08 0.820 0.830
e 1.27 – – 0.050 – –
E 11.56 11.96 0.455 0.471
E1 10.03 10.29 0.395 0.405
L 0.40 0.60 0.016 0.024
α 0° 5° 0° 5°
N32 32
Figure 17. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline
Drawing is not to scale.
TSOP-d
16
17
CP
A
1
L
A1
α
32
D
eb
E1 E
C
A2
Page 20
M48T513Y, M48T513V
20/23
Table18. SH - 4-pinSNAPHAT Housing for48mAhBattery & Crystal, Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
Figure 18. SH- 4-pin SNAPHATHousing for 48 mAhBattery & Crystal, Package Outline
Drawing is not to scale.
SHTK-A
A1
A
D
E
eA
eB
A2
B
L
A3
Page 21
21/23
M48T513Y, M48T513V
Table19. SH - 4-pinSNAPHAT Housing for120 mAhBattery & Crystal, Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 .0335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 .0710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
Figure 19. SH- 4-pin SNAPHATHousing for 120mAhBattery & Crystal, Package Outline
Drawing is not to scale.
SHTK-A
A1
A
D
E
eA
eB
A2
B
L
A3
Page 22
M48T513Y, M48T513V
22/23
Table 20. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT,
Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.46 0.014 0.018
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 0.81 – – 0.032 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N44 44
CP 0.10 0.004
Figure 20. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Outline
Drawing is not to scale.
SOH-A
E
N
D
C
LA1 α
1
H
A
CP
Be
A2
eB
Page 23
23/23
M48T513Y, M48T513V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information norfor anyinfringement of patents orother rights ofthird parties whichmay result from itsuse. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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