Page 1
1/23November 2002
M41T56
512 bit (64 bit x 8) SERIAL ACCESS TIMEKEEPER® SRAM
FEATURES SUMMARY
■ 5V ±10% SUPPL Y VO L TAG E
■ COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONT H , YEAR S, and
CENTURY
■ YEAR 2000 COMPLIANT
■ SOFTWARE CLOCK CALIBRATION
■ AUTOMATIC POWER-FAIL DETECT and
SWITCH CIRCUITRY
■ I
2
C BUS C O MPATI BLE
■ 56 BYTES OF GENERAL PURPOSE RAM
■ ULTRA-LOW BATTER Y SUPPLY CURRENT
OF 450nA
■ LOW OPERATING CURRENT OF 300µA
■ OPERATING TEMPER ATURE OF –40 to 85°C
■ AUTOMATIC LEAP YEAR COMPENSATION
■ SPECIAL SOFT WARE PROGRAM MABLE
OUTPUT
■ PACKA GING OP TIONS IN CLUDE :
– 28-LEAD SOIC and SNAPHA T
®
TOP
(to be Ordered Separately)
–SO8
Figure 1. 8-pi n S OI C Package
Figure 2. 28-pi n S O I C Package
8
1
SO8 (M)
150mil Width
28
1
SOH28 (MH)
SNAPHAT (SH)
Battery & Crystal
Page 2
M41T56
2/23
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram ( Fig u r e 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
8-pin SOIC Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
28-pin SOIC Connection s (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram (Fi g ure 6 .) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Rati ng s (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
AC Measurement I/O Waveform (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Characteristi cs (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Crystal Electrical Characteristics (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Bus Data Transfer Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Acknowledge Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Timing Requirements Sequence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Slave Address Location (Figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
READ Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Alternative READ Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Mode Sequence (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up Mode AC Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up Trip Points DC Char ac te r i stics (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Register Map (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Calibratio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Initial Power- o n Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Crystal Accuracy Across Temperature (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Calibratio n (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SNAPHAT Battery/Crystal Table (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Page 3
3/23
M41T56
SUMMARY DESCRIPTION
The M41T56 TIMEKEEPER
®
is a low power, 512bit static CMOS RAM organized as 64 words by 8
bits. A built-in 32,768 Hz oscillator (external crystal
controlled) and the first 8 bytes of the RAM are
used for the clock/calendar function and are configured in binary coded decimal (BCD) format. Addresses and data are transferred serially via a twoline, bi-directional bus. The built-in address register is incremented automatically after each WRITE
or READ data byte.
The M41T56 clock has a built-in power sense circuit which detects power failures and automatically switches to the battery supply during power
failures. The energy needed to sustain the RAM
and clock operations can be supplied from a small
lithium co in cel l.
Typical data retention time is in excess of 10 years
with a 50mAh, 3V lithium cell. The M41T56 is supplied in an 8-lead P lastic SOIC package or a 28lead SNAPHAT
®
package.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT housing cont aining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and c rystal dam age d ue t o
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic antistatic tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package
(e.g., SNAPHAT) part number is “M4TxxBR12SH” (see Table 12, page 17).
Caution: Do not place the SNAPHAT battery/crystal package “M4Txx-BR12SH” i n condu ctive foam
as this will drain the lithium button-cell battery.
Figure 3. Logic Diagram Table 1. Signal Names
AI02304B
OSCI
V
CC
M41T56
V
SS
SCL
OSCO
SDA
FT/OUT
V
BAT
OSCI Oscillator Input
OCSO Oscillator Output
FT/OUT
Frequency Test / Output Driver
(Open Drain)
SDA Serial Data Address Input / Output
SCL Serial Clock
V
BAT
Battery Supply Voltage
V
CC
Supply Voltage
V
SS
Ground
Page 4
M41T56
4/23
Figure 4. 8-pi n S OI C Co nn e ct io ns Figure 5. 28-pi n S O I C C onnections
Figure 6. Block Diagram
1
SDAV
SS
SCL
FT/OUTOSCO
OSCI V
CC
V
BAT
AI02306B
M41T56
2
3
4
8
7
6
5
AI03607
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
NC
V
SS
NC
NC
NC V
CC
M41T56
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SDA
NC
SCL
NC
NC
NC
NC
NC
FT/OUT
NC
NC
AI02566
SECONDS
OSCILLATOR
32.768 kHz
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
SERIAL
BUS
INTERFACE
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
MINUTES
CENTURY/HOURS
DAY
DATE
MONTH
YEAR
CONTROL
RAM
(56 x 8)
OSCI
OSCO
FT/OUT
V
CC
V
SS
V
BAT
SCL
SDA
1 Hz
Page 5
5/23
M41T56
MAXIMUM RATING
Stressing the device above the rating listed in t he
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the dev ice at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absol ute Maxim um Rating conditions for extended periods may affect device reliability. Refer also to the
STMicroelectronics SURE Program and oth er relevant quality documents.
Table 2. Absolute Maximum Ratings
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 and 120
seconds).
CAUTION: Nega tive undershoot s below –0.3V are not allowed on any pi n while in the Bat tery Back-up mode.
CAUTION: Do NOT wav e s older SOI C t o avoid da m ag i ng SNAP HAT so c kets.
Symbol Parameter Value Unit
T
A
Ambient Operating Temperature –40 to 85 °C
T
STG
Storage Temperature (VCC Off, Oscillator Off)
SNAPHAT –40 to 85
°C
SOIC –55 to 125
T
SLD
(1)
Lead Solder Temperature for 10 seconds 260 °C
V
IO
Input or Output Voltages –0.3 to 7 V
V
CC
Supply Voltage –0.3 to 7 V
I
O
Output Current 20 mA
P
D
Power Dissipation 0.25 W
Page 6
M41T56
6/23
DC AND AC PARAMETERS
This section summarizes the operat ing and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the M easure-
ment Conditions listed i n the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Note: Output Hi-Z is def i ned as the point where data is no longer driven.
Figure 7. AC Measurement I/O Waveform
Table 4. Capacitance
Note: 1. Eff ective capacitance measured with powe r supply at 5V; sam p l ed, not 100% tested.
2. At 25°C, f = 1M Hz.
3. Outputs desele ct ed.
Parameter Value Unit
Supply Voltage (V
CC
)
4.5 to 5.5 V
Ambient Operating Temperature (T
A
)
–40 to 85 °C
Load Capacitance (C
L
)
100 pF
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3 V
Input and Output Timing Ref. Voltages 1.5 V
AI02568
0.8V
CC
0.2V
CC
0.7V
CC
0.3V
CC
Symbol
Parameter
(1,2)
Min Max Unit
C
IN
Input Capacitance (SCL) 7 pF
C
OUT
(3)
Output Capacitance (SDA, FT/OUT) 10 pF
t
LP
Low-pass filter input time constant (SDA and SCL) 0.25 1 µs
Page 7
7/23
M41T56
Table 5. DC Characteristics
Note: 1. Val i d for Ambient Operating Temperature: TA = –40 to 85°C ; VCC = 4.5 to 5.5V (except where noted).
2. STMicroelectronics rec ommends the R AYOVAC BR1225 or BR1632 (or eq ui valent) as the ba tt ery supply.
Table 6. Crystal Electrical Characteristics
Note: 1. These values are externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/
1TC252E1 27, Tunin g Fo rk T ype (thr u- hole ) or t he D MX- 26 S: 1T JS1 25FH2A 2 12, ( SMD) qu artz cry stal for i ndus tri al temper at ure
operation s. KDS can be contacted at kouhou@kdsj.co.jp or htt p://www.kdsj.co.jp for furt her informat i on on this crystal ty pe.
2. Load capacitors are integrated within the M41T56. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths an d i solation from RF generating sig nal s should be taken into accoun t.
3. All SNAPHAT battery/cry stal tops meet these specifica tions.
Symbol Parameter
Test Condition
(1)
Min Typ Max Unit
I
LI
Input Leakage Current
0V ≤ V
IN
≤ V
CC
±1 µA
I
LO
Output Leakage Current
0V ≤ V
OUT
≤ V
CC
±1 µA
I
CC1
Supply Current Switch Frequency = 100kHz 300 µA
I
CC2
Supply Current (Standby)
SCL, SDA = V
CC
– 0.3V
100 µA
V
IL
Input Low Voltage –0.3 1.5 V
V
IH
Input High Voltage 3
V
CC
+ 0.8
V
V
OL
Output Low Voltage
I
OL
= 5mA, VCC = 4.5V
0.4 V
V
BAT
(2)
Battery Supply Voltage 2.5 3 3.5 V
I
BAT
Battery Supply Current
T
A
= 25°C, VCC = 0V,
Oscillator ON, V
BAT
= 3V
450 550 nA
Symbol
Parameter
(1,2,3)
Min Typ Max Unit
f
O
Resonant Frequency 32.768 kHz
R
S
Series Resistance 60 kΩ
C
L
Load Capacitance 12.5 pF
Page 8
M41T56
8/23
OPERATION
The M41T56 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slav e address (D0h). The 64 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Seconds Register
2. Minutes Register
3. Century/Hours Register
4. Day Register
5. Date Register
6. Month Register
7. Years Register
8. Control Register
9 to 64.RAM
The clock continually monitors V
CC
for an out of
tolerance condition. Should V
CC
fall below V
PFD
,
the device terminates a n access in progress and
resets the device address counter. Inputs to the
device will not be recognized at this time to prevent erroneous data f rom being writ ten to the device from an out of tolerance system. W hen V
CC
falls below V
BAT
, the device automatically switches over to the battery and powers down into an ultra low current mode of operation to conserve
battery life. Upon power-up, the device switches
from battery to V
CC
at V
BAT
and recognizes inputs
when V
CC
goes above V
PFD
volts.
2-Wire Bus Characteristics
This bus is intended for communication between
different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one f or clock signals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data trans fer, the dat a line mus t remain
stable whenever the clock line is High.
– Changes in the dat a line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A c hange in the st ate of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, whil e the c lock is Hi gh,
defines the STOP condition.
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are cal led
“slaves.”
Acknowledge. Eac h byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver, whereas
the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge a fter the reception of e ach byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end-of-data to the slave transm itter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Page 9
9/23
M41T56
Figure 8. Serial Bus Data Transfer Sequence
Figure 9. Acknowledge Sequence
Figure 10. Bus Timing Requirements Sequence
AI00587
DATA
CLOCK
DATA LINE
STABLE
DATA VALID
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00601
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCLK FROM
MASTER
START
CLOCK PULSE FOR
ACKNOWLEDGEMENT
12 89
MSB LSB
AI00589
SDA
P
tSU:STOtSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STAtBUF
SP
Page 10
M41T56
10/23
Table 7. AC Characteristics
Note: 1. Val i d for Ambient Operating Temperature: TA = –40 to 85°C ; VCC = 4.5 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
READ Mode
In this mode, the master reads the M41T56 s lave
after setting the slave address (see Figure 11 and
Figure 12, page 11). Following the WRITE Mode
Control Bit ( R/W
= 0) and the Acknowledge Bit, the
word address A
n
is written to the on-chip address
pointer. Next the START condition and slave address are repeated, followed by the READ Mode
Control Bit (R/W
= 1). At this point, the master
transmitter becomes the master receiver. The data
byte which was addressed will be transmitted and
the master receiver will send an Acknow ledge Bit
to the slave transmitter. The address pointer is
only incremented on reception of an Acknowledge
Bit. The M41T56 slave transmitter will now place
the data byte at address A
n
+ 1 on the bus. The
master receiver reads and acknowledges the new
byte and the address pointer is incremented to A
n
+ 2. This cycle of reading consecutive addresses
will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ Mode may also be implemented, whereby the master reads the M41T56 slave
without first writing to the (volatile) a ddress pointer. The first address that is read is the last one
stored in the pointer, see Figure 13, page 11.
Figure 11. Slave Address Location
Symbol
Parameter
(1)
Min Max Unit
f
SCL
SCL Clock Frequency 0 100 kHz
t
LOW
Clock Low Period 4.7 µs
t
HIGH
Clock High Period 4 µs
t
R
SDA and SCL Rise Time 1 µs
t
F
SDA and SCL Fall Time 300 ns
t
HD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
4µs
t
SU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
4.7 µs
t
SU:DAT
Data Setup Time 250 ns
t
HD:DAT
(2)
Data Hold Time 0 µs
t
SU:STO
STOP Condition Setup Time 4.7 µs
t
BUF
Time the bus must be free before a new transmission can start 4.7 µs
AI00602
R/W
SLAVE ADDRESS
START A
0100011
MSB
LSB
Page 11
11/23
M41T56
Figure 12. READ Mode Sequence
Figure 13. Alternative READ Mode Sequence
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS
Page 12
M41T56
12/23
WRITE Mode
In this mode the master transmitter transmits to
the M41T56 slave receiver. Bus protocol is shown
in Figure 14, page 12. Following the ST ART condition and slave address, a logic '0' (R/W
= 0) is
placed on the bus and indicates to the addressed
device that word address A
n
will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next memory location within the RAM on the
reception of an acknowledge clock. The M41T 56
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address and again after it has rec eived the
word address and each data byte (see Figure 11).
Figure 14. WRITE Mode Sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (n)
SLAVE
ADDRESS
Page 13
13/23
M41T56
Data Retention Mode
With valid V
CC
applied, the M41T56 can be accessed as described above with REA D or WRI TE
cycles. Should the supply voltage decay, the
M41T56 will aut oma tical ly de sele ct, write pro tec ting itself when V
CC
falls between V
PFD
(max) and
V
PFD
(min). This is accomplished by internally inhibiting access to the clock registers and S RAM.
When V
CC
falls below the Battery Back-up
Switchover Voltage (V
SO
), power input is switched
from the V
CC
pin to the battery and the clock reg-
isters and SRAM are maintained from the attached
battery supply.
All outputs become high impedance. On power up,
when V
CC
returns to a nominal value, write protec-
ti on con t inues for t
REC
.
For a further more detailed review of battery lifetime calculations, please see Application Note
AN1012.
Figure 15. Power Down/Up Mode AC Waveforms
Table 8. Power Down/Up Mode AC Characteristics
Note: 1. Val i d for Ambient Operating Temperature: TA = –40 to 85°C ; VCC = 4.5 to 5.5V (except where noted).
Table 9. Power Down/Up Trip Points DC Characteristics
Note: 1. All voltages referenced to VSS.
2. Valid for Am bi ent Operating Temperature : T
A
= –40 to 85°C ; VCC = 4.5 to 5.5V (except where noted).
Symbol
Parameter
(1)
Min Max Unit
t
PD
SCL and SDA at VIH before Power Down
0ns
t
FB
V
PFD
(min) to VSS VCC Fall Time
300 µs
t
RB
VSS to V
PFD
(min) VCC Rise Time
100 µs
t
REC
SCL and SDA at VIH after Power Up
10 µs
Symbol
Parameter
(1,2)
Min Typ Max Unit
V
PFD
Power-fail Deselect Voltage
1.2 V
BAT
1.25 V
BAT
1.285 V
BAT
V
V
SO
Battery Back-up Switchover Voltage
V
BAT
V
AI00595
V
CC
tFB
tREC
tPD
tRB
V
PFD
V
SO
DATA RETENTION TIME
SDA
SCL
I
BAT
Page 14
M41T56
14/23
CLOCK OPERATION
The eight byte clock register (see Table 10) is
used to both set the clock and to read the date and
time from the clock, in a binary coded decimal format. Seconds, Minutes, and Hours are contained
within the first three registers. Bits D6 and D7 of
Clock Register 2 (Hours Register) contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle. Bits D0
through D2 of Register 3 contain the Day (day of
week). Registers 4, 5, and 6 contain the Date (day
of month), Month, and Years. The f inal register is
the Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 0 contains
the STOP Bit (ST). Setting this bit to a '1' will cause
the oscillator to stop. If the device is expected to
spend a significant amount of time on the shelf, the
oscillator may be stopped to reduce current drain.
When reset to a '0' the oscillator restarts within one
second.
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Control
Register (Address location 7) may be accessed independently. Provision has been made to assure
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock registers will be delayed by 250ms to allow the READ
to be completed before the update occurs. This
will preven t a tr an s it ion o f data du r ing t he R EA D .
Note: This 250ms delay affects only the clock register update and does not alter the actual clock
time.
Table 10. Register Map
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
ST = STOP Bit
OUT = Output level
X = Don't care
CEB = Century Enable Bit
CB = Centu ry Bit
Note: 1. When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle.
Address
Data
Function/Ra nge
BCD Format
D7 D6 D5 D4 D3 D2 D1 D0
0 ST 10 Seconds Seconds Seconds 00-59
1 X 10 Minutes Minutes Minutes 00-59
2
CEB
(1)
CB 10 Hours Hours Century/Hours 0-1/00-23
3 X X X X X Day Day 01-07
4 X X 10 Date Date Date 01-31
5 X X X 10 M. Month Month 01-12
6 10 Years Years Year 00-99
7 OUT FT S Calibration Control
Page 15
15/23
M41T56
Clock Calibration
The M41T56 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The
devices are tested not to exceed 35ppm (parts per
million) oscillator frequency error at 25°C, which
equates to about ±1.53 minu tes per month. With
the calibration bits properly set, the accuracy of
each M41T56 im proves to better than +1/–2 ppm
at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 16, page 16). M ost clock
chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M41T56 design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Figure 16, page 16. The num ber of times pulses are
blanked (subtracted, n egative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration Byte
found in the Control Register. Adding counts
speeds the clock up, subtracting counts slows the
clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register (Addr 7). This
byte can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negat ive
calibration. Calibration occurs within a 64 m inute
cycle. The first 62 m inutes i n t he c ycle m ay , onc e
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minutes cycle will be modified; if
a binary 6 is loaded, t he first 12 will be affected,
and so on.
Therefore, each cal ibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the cal ibration registe r. Assuming that
the oscillator is in fact running at exactly 32,768
Hz, each of the 31 increm ents in the Calibration
Byte would represent +10.7 or –5. 35 seconds per
month which corresponds to a total ra nge of +5.5
or –2.75 minutes per month.
Two methods are availab le for ascertaining how
much calibration a given M41T56 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his environment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accessed the Calibration Byte.
The second approach is better suited t o a manufacturing environment, and involves the use of
some test equipment. When the F requency Test
(FT) Bit, the seventh-most significant bit in the
Control Register, is set to a '1,' and the oscillator is
running at 32,768 Hz, the FT/OUT pin of the device will toggle at 512 Hz. Any deviation from 512
Hz indicates the degr ee and direction of osc illat or
frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would indicate a +20ppm oscillator frequency error, requiring a –10(XX001010) to be loaded into the
Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
Output Driver Pin
When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the contents of
D7 of the Control Reg ister. In other words, when
D6 of location 7 is a '0' and D7 of location 7 is a '0'
and then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which requires an external pull-up resistor.
Initial Power-on Defaults
Upon initial application of power to the device, the
FT Bit will be set to a '0' and the OUT Bit will be set
to a '1.' All other Register bits will initially power-on
in a random state.
Page 16
M41T56
16/23
Figure 16. Crystal Accuracy Across Temp eratur e
Figure 17. Cl ock C al ib ra ti on
AI00999
–160
0 10203040506070
Frequency (ppm)
Temperature °C
80–10–20–30–40
–100
–120
–140
–40
–60
–80
20
0
–20
∆F
= -0.038 (T - T
0
)2± 10%
F
ppm
C
2
T0= 25 °C
AI00594B
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
Page 17
17/23
M41T56
PART NUMBERING
Table 11. Ordering Information Scheme
Note: 1. The S OIC package (SOH28) requir es the battery package (SNAPHAT®) which is ordered separately under the part number
“M4Txx-B R12SHx” in pl astic tube or “M4Txx-BR12SHxTR” in Tape & Reel form.
Caution : D o not place the SNAPHAT battery package “M4Txx-BR12SHx” in conductive foam as this will drain the lithium button-cell
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 12. SNAPHAT Battery/Crystal Table
Example: M41T 56 M 6 TR
Device Type
M41T
Supply Voltage and Write Protect Voltage
56 = V
CC
= 4.5 to 5.5V
Package
M = SO8
MH
(1)
= SOH28
Temperature Rang e
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Part Number Description Package
M4T28-BR12SH Lithium Battery (48mAh)/Crystal SNAPHAT SH
M4T32-BR12SH Lithium Battery (120mAh)/Crystal SNAPHAT SH
Page 18
M41T56
18/23
PACKAGE MECHANICAL INFORMATION
Figure 18. SO8 – 8-pin Plastic Small Package Outline
Note: Drawing is not to scale.
Table 13. SO8 – 8-pin Plastic Small Outline, Package Mechanical Data
Symb
mm inches
T yp Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N8 8
CP 0.10 0.004
SO-a
E
N
CP
B
e
A
D
C
LA1 α
1
H
h x 45˚
Page 19
19/23
M41T56
Figure 19. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
Note: Drawing is not to scale.
Table 14. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mech. Data
Symb
mm inches
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.4 9 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28
CP 0.10 0.004
SOH-A
E
N
D
C
LA1 α
1
H
A
CP
Be
A2
eB
Page 20
M41T56
20/23
Figure 20. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.3 8 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.8 4 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 .6122 .6280
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
SHTK-A
A1
A
D
E
eA
eB
A2
B
L
A3
Page 21
21/23
M41T56
Figure 21. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 10.5 4 0.415
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.3 8 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.8 4 0.835 0.860
E 17.27 18.03 0.680 0.710
eA 15.55 15.95 .6122 .6280
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
SHTK-B
A1
A
D
E
eA
eB
A2
B
L
A3
Page 22
M41T56
22/23
REVISION HIST ORY
Table 17. Document Revision History
Date Rev. # Revision Details
March 1999 1.0 First Issue
12/23/99 1.1 SOH28 package added
03/21/00 1.2 Series Resistance Max Value Changed (Table 6)
11/30/00 1.3 Added PSDIP8 package
01/25/01 1.4 Corrected graphic, measurements of PSDIP8 (Figure 20, Table 14)
02/16/01 2.0 Reformatted, table added (Table 12)
04/06/01 2.1
Add temp./voltage information to characteristics (Tables 5, 7); correct Series Resistance
(Table 6)
07/17/01 2.2 Basic formatting changes
08/02/02 2.3
Modify reflow time and temperature footnote (Table 2); modify Crystal Electrical
Characteristics table footnotes (Table 6); removed PSDIP8 package
11/07/02 2.4 Correct figure name (Figure 1)
Page 23
23/23
M41T56
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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