Datasheet K9F1G16Q0M-YCB0, K9F1G16Q0M-PCB0, K9F1G08U0M-YIB0, K9F1G08U0M-YCB0, K9F1G08U0M-VIB0 Datasheet (Samsung)

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Page 1

March. 2003

ELECTRONICS

San 16 Banwol-Ri

Taean-Eup Hwasung- City

Kyungki Do, Korea

Tel.) 82 - 31 - 208 - 6463

Fax.) 82 - 31 -208 - 6799

11Gb

1.8V NAND Flash Errata

Description : Some of AC characteristics are not meeting the specification.

> AC characteristics : Refer to Table

Affected Products : K9F1G08Q0M-YCB0/YIB0, K9F1G16Q0M-YCB0/YIB0

K9K2G08Q0M-YCB0/YIB0, K9K2G16Q0M-YCB0/YIB0

Improvement schedule : The components targeted to meet the specification

is scheduled to be av ailable by workweek 25 along

with the final specification values.

Workaround : Relax the relevant timing parameters according to the table.

Table

Parameters

Specification

Relaxed Condition

Sincerely, chwoosun@sec.samsung.com Product Planning & Application Eng.

Memory Division Samsung Electronics Co.

tWC

45 80

tWH

15 20

tWP

25 60

tRC

50 80

tREH

15 20

tRP

25 60

UNIT : ns

tREA

30 60

tCEA

45 75

Page 2

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

Document Title

128M x 8 Bit / 64M x 16 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No

0.0

0.1

0.2

0.3

History

1. Initial issue

1. Iol(R/B) of 1.8V is changed.

- min. value : 7mA --> 3mA

- Typ. value : 8mA --> 4mA

2. AC parameter is changed. tRP(min.) : 30ns --> 25ns

3. A recovery time of minimum 1µs is required before internal circuit gets ready for any command sequences as shown in Figure 17.

---> A recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 17.

1. ALE status fault in ’Random data out in a page’ timing diagram(page 19) is fixed.

1. tAR1, tAR2 are merged to tAR.(Page11) (Before revision) min. tAR1 = 10ns , min. tAR2 = 50ns (After revision) min. tAR = 10ns

2. min. tCLR is changed from 50ns to 10ns.(Page11)

3. min. tREA is changed from 35ns to 30ns.(Page11)

4. min. tWC is changed from 50ns to 45ns.(Page11)

5. tRHZ is devided into tRHZ and tOH.(Page11)

- tRHZ : RE High to Output Hi-Z

- tOH : RE High to Output Hold

6. tCHZ is devided into tCHZ and tOH.(Page11)

- tCHZ : CE High to Output Hi-Z

- tOH : CE High to Output Hold

Draft Date

July. 5. 2001

Nov. 5. 2001

Dec. 4. 2001

Apr. 25. 2002

Remark

Advance

0.4

0.5

0.6

1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 35)

2. Add the data protection Vcc guidence for 1.8V device - below about

1.1V. (Page 36)

The min. Vcc value 1.8V devices is changed. K9F1GXXQ0M : Vcc 1.65V~1.95V --> 1.70V~1.95V

Pb-free Package is added. K9F1G08U0M-FCB0,FIB0 K9F1G08Q0M-PCB0,PIB0 K9F1G08U0M-PCB0,PIB0 K9F1G16U0M-PCB0,PIB0 K9F1G16Q0M-PCB0,PIB0

Nov. 22.2002

Mar. 6.2003

Mar. 13.2003

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.

SAMSUNG

Page 3

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

Document Title

128M x 8 Bit / 64M x 16 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No

0.7

0.8

Errata is added.(Front Page)-K9F1GXXQ0M tWC tWP tWH tRC tREH tRP tREA tCEA

Specification 45 25 15 50 15 25 30 45 Relaxed value 80 60 20 60 80 60 60 75

1. The 3rd Byte ID after 90h ID read command is don’t cared. The 5th Byte ID after 90h ID read command is deleted.

Draft Date

Mar.17. 2003

Apr. 9. 2003

RemarkHistory

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

SAMSUNG

Page 4

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

128M x 8 Bit / 64M x 16 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F1G08Q0M-Y,P K9F1G16Q0M-Y,P X16 K9F1G08U0M-Y,P K9F1G16U0M-Y,P X16 K9F1G08U0M-V,F X8 WSOP1

1.70 ~ 1.95V

2.7 ~ 3.6V

FEATURES

TSOP1

• Voltage Supply

-1.8V device(K9F1GXXQ0M): 1.70V~1.95V

-3.3V device(K9F1GXXU0M): 2.7 V ~3.6 V

• Organization

- Memory Cell Array

-X8 device(K9F1G08X0M) : (128M + 4,096K)bit x 8bit

-X16 device(K9F1G16X0M) : (64M + 2,048K)bit x 16bit

- Data Register

-X8 device(K9F1G08X0M): (2K + 64)bit x8bit

-X16 device(K9F1G16X0M): (1K + 32)bit x16bit

- Cache Register

-X8 device(K9F1G08X0M): (2K + 64)bit x8bit

-X16 device(K9F1G16X0M): (1K + 32)bit x16bit

• Automatic Program and Erase

- Page Program

-X8 device(K9F1G08X0M): (2K + 64)Byte

-X16 device(K9F1G16X0M): (1K + 32)Word

- Block Erase

-X8 device(K9F1G08X0M): (128K + 4K)Byte

-X16 device(K9F1G16X0M): (64K + 2K)Word

• Page Read Operation

- Page Size

- X8 device(K9F1G08X0M): 2K-Byte

- X16 device(K9F1G16X0M) : 1K-Word

- Random Read : 25µs(Max.)

- Serial Access : 50ns(Min.)

• Fast Write Cycle Time

- Program time : 300µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Cache Program Operation for High Performance Program

• Power-On Auto-Read Operation

• Intelligent Copy-Back Operation

• Unique ID for Copyright Protection

• Package :

- K9F1GXXX0M-YCB0/YIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F1G08U0M-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm)

- K9F1GXXX0M-PCB0/PIB0 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package

- K9F1G08U0M-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F1G08U0M-V,F(WSOPI ) is the same device as K9F1G08U0M-Y,P(TSOP1) except package type.

GENERAL DESCRIPTION

Offered in 128Mx8bit or 64Mx16bit, the K9F1GXXX0M is 1G bit with spare 32M bit capacity. Its NAND cell provides the most costeffective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112byte(X8 device) or 1056-word(X16 device) page and an erase operation can be performed in typical 2ms on a 128K-byte(X8 device) or 64K-word(X16 device) block. Data in the data page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1GXXX0M′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1GXXX0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

SAMSUNG

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K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

PIN CONFIGURATION (TSOP1)

K9F1GXXX0M-YCB0,PCB0/YIB0,PIB0

X8X16 X16X8

N.C

N.C N.C N.C N.C N.C N.C R/B RE

N.C N.C Vcc Vss N.C N.C

CLE

ALE

WE WP N.C N.C N.C N.C N.C

N.C N.C N.C N.C N.C N.C R/B RE

CE N.C N.C Vcc Vss N.C N.C

CLE ALE

WP N.C N.C N.C N.C N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48-pin TSOP1

Standard Type 12mm x 20mm

N.C

I/O7

I/O6

I/O5

I/O4

N.C

PRE

Vcc

Vss

N.C

I/O3

I/O2

I/O1

I/O0

N.C

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

FLASH MEMORY

Vss I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 N.C PRE Vcc N.C N.C N.C I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 Vss

48 - TSOP1 - 1220F

+0.003

-0.001

+0.07

-0.03

0.20

0.008

0.50

0.0197

#24

TYP

0.25

0.010

0~8¡Æ

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

#48

#25

Unit :mm/Inch

MAX

0.10

0.004

0.25

0.010

( )

MAX

12.00

0.472

0.488

12.40

1.00±0.05

0.039±0.002

1.20 MAX

+0.075

0.035 +0.003

-0.001

0.125

0.005

0.047

0.05

0.002

MIN

0.45~0.75

0.018~0.030

0.50

( )

0.020

SAMSUNG

Page 6

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

PIN CONFIGURATION (WSOP1)

K9F1G08U0M-VCB0,FCB0/VIB0,FIB0

N.C

N.C N.C

DNU

N.C N.C N.C R/B RE

DNU

N.C Vcc Vss N.C

DNU

CLE ALE

WP N.C N.C

DNU

N.C N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

N.C

DNU

N.C

I/O7

I/O6

I/O5

I/O4

N.C

DNU

N.C

Vcc

Vss

N.C

DNU

N.C

I/O3

I/O2

I/O1

I/O0

N.C

DNU

N.C

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48 - WSOP1 - 1217F

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP

(0.50±0.06)

#24

15.40±0.10

Unit :mm

0.70 MAX

0.58±0.04

#48

12.00±0.10

#25

(0.1Min)

17.00±0.20

+0.075

-0.035

0.10

0.45~0.75

SAMSUNG

Page 7

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

PIN DESCRIPTION

Pin Name Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

(K9F1G08X0M)

I/O0 ~ I/O15

(K9F1G16X0M)

The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 operation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and output.

FLASH MEMORY

CLE

ALE

R/B

PRE

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode.

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

POWER-ON READ ENABLE

The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when PRE pin is tied to Vcc.

Vcc

Vss GROUND

N.C

POWER

VCC is the power supply for device.

NO CONNECTION

Lead is not internally connected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.

SAMSUNG

Page 8

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

Figure 1-1. K9F1G08X0M (X8) Functional Block Diagram

VCC VSS

FLASH MEMORY

A12 - A27

A0 - A11

Command

CE RE WE

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

Command

Control Logic

& High Voltage

Generator

CLE

ALE PRE

Figure 2-1. K9F1G08X0M (X8) Array Organization

1024M + 32M Bit

NAND Flash

ARRAY

(1024 + 32)Byte x 65536

Data Register & S/A

Cache Register

Y-Gating

I/O Buffers & Latches

Global Buffers

1 Block = 64 Pages (128K + 4k) Byte

Output

Driver

VCC VSS

I/0 0

I/0 7

64K Pages (=1,024 Blocks)

2K Bytes 64 Bytes

Page Register

2K Bytes

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A8 A9 A10 A11 *L *L *L *L

3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19 4th Cycle A20 A21 A22 A23 A24 A25 A26 A27

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low". * The device ignores any additional input of address cycles than reguired.

1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 64 Pages = (128K + 4K) Bytes 1 Device = (2K+64)B x 64Pages x 1024 Blocks = 1056 Mbits

8 bit

I/O 0 ~ I/O 7

64 Bytes

Column Address Column Address

Row Address Row Address

SAMSUNG

Page 9

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

Figure 1-2. K9F1G16X0M (X16) Functional Block Diagram

VCC VSS

FLASH MEMORY

A11 - A26

A0 - A10

Command

CE RE WE

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

Command

Control Logic

& High Voltage

Generator

CLE

ALE PRE

Figure 2-2. K9F1G16X0M (X16) Array Organization

1024M + 32M Bit

NAND Flash

ARRAY

(512 + 64)Word x 65536

Data Register & S/A

Cache Register

Y-Gating

I/O Buffers & Latches

Global Buffers

1 Block = 64 Pages (64K + 2k) Word

Output

Driver

VCC VSS

I/0 0

I/0 15

1 Page = (1K + 32)Words

64K Pages (=1,024 Blocks)

1K Words 32 Words

Page Register

1K Words

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O8 ~ 15

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 *L

2nd Cycle A8 A9 A10 *L *L *L *L *L *L

3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18 *L 4th Cycle A19 A20 A21 A22 A23 A24 A25 A26 *L

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

32 Words

I/O 0 ~ I/O 15

1 Block = (1K + 32)Word x 64 Pages = (64K + 2K) Words 1 Device = (1K+32)Word x 64Pages x 1024 Blocks = 1056 Mbits

16 bit

Column Address Column Address

Row Address Row Address

SAMSUNG

Page 10

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

Product Introduction

The K9F1GXXX0M is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8(X8 device) or 1056x16(X16 device) columns. Spare 64(X8) or 32(X16) columns are located from column address of 2048~2111(X8 device) or 1024~1055(X16 device). A 2112-byte(X8 device) or 1056-word(X16 device) data register and a 2112-byte(X8 device) or 1056word(X16 device) cache register are serially connected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of the 64 pages formed by two NAND structures, totaling 33792 NAND structures of 32 cells. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 separately erasable 128K-byte(X8 device) or 64K-word(X16 device) blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1GXXX0M.

The K9F1GXXX0M has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 128M byte(X8 device) or 64M word(X16 device) physical space requires 28(X8) or 27(X16) addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1GXXX0M.

The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache program when there are lots of pages of data to be programmed.

The device embodies power-on auto-read feature which enables serial access of data of the 1st page without command and address input after power-on.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 00h 30h Read for Copy Back 00h 35h Read ID 90h Reset FFh - O Page Program 80h 10h Cache Program 80h 15h Copy-Back Program 85h 10h Block Erase 60h D0h Random Data Input Random Data Output Read Status 70h O

85h 05h E0h

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Command not specified in command sets table is not permitted to be entered to the device, which can raise erroneous operation.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

SAMSUNG

Page 11

K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Voltage on any pin relative to VSS

Temperature Under Bias

Storage Temperature

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

K9F1GXXX0M-XCB0 K9F1GXXX0M-XIB0 -40 to +125 K9F1GXXX0M-XCB0 K9F1GXXX0M-XIB0

VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6

VCC -0.2 to + 2.45 -0.6 to + 4.6

TBIAS

TSTG -65 to +150 °C

K9F1GXXQ0M(1.8V) K9F1GXXU0M(3.3V)

Rating

-10 to +125

Unit

°C

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F1GXXX0M-XCB0 :TA=0 to 70°C, K9F1GXXX0M-XIB0:TA=-40 to 85°C)

Parameter Symbol

Supply Voltage VCC 1.70 1.8 1.95 2.7 3.3 3.6 V Supply Voltage VSS 0 0 0 0 0 0 V

K9F1GXXQ0M(1.8V)

Min Typ. Max Min Typ. Max

K9F1GXXU0M(3.3V)

Unit

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

Operat-

Current

Stand-by Current(TTL) ISB1 CE=VIH, WP=PRE=0V/VCC - - 1 - - 1

Stand-by Current(CMOS) ISB2

Input Leakage Current ILI VIN=0 to Vcc(max) - - ±20 - - ±20 Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±20 - - ±20

Input High Voltage VIH - VCC-0.4 -

Input Low Voltage, All inputs VIL - -0.3 - 0.4 -0.3 - 0.8

Output High Voltage Level VOH

Output Low Voltage Level

Output Low Current(R/B) IOL(R/B)

Page Read with Serial Access

ing

Program ICC2 - - 5 15 - 10 20 Erase ICC3 - - 5 15 - 10 20

tRC=50ns, CE=VIL

ICC1

IOUT=0mA

CE=VCC-0.2, WP=PRE=0V/VCC

K9F1GXXQ0M :IOH=-100µA K9F1GXXU0M :IOH=-400µA

K9F1GXXQ0M :IOL=100uA

VOL

K9F1GXXU0M :IOL=2.1mA K9F1GXXQ0M :VOL=0.1V

K9F1GXXU0M :VOL=0.4V

K9F1GXXQ0M(1.8V) K9F1GXXU0M(3.3V) Unit

Min Typ Max Min Typ Max

- 5 15 - 10 20

- 20 100 - 20 100

VCC+

Vcc-0.1 - - 2.4 - -

- - 0.1 - - 0.4

3 4 - 8 10 - mA

2.0 - VCC+0.3

0.3

µA

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FLASH MEMORY

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

Valid Block Number NVB 1004 - 1024 Blocks

NOTE :

1. The K9F1GXXX0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction.

AC TEST CONDITION

(K9F1GXXX0M-XCB0 :TA=0 to 70°C, K9F1GXXX0M-XIB0:TA=-40 to 85°C K9F1GXXQ0M : Vcc=1.70V~1.95V, K9F1GXXU0M : Vcc=2.7V~3.6V unless otherwise noted)

Parameter K9F1GXXQ0M K9F1GXXU0M

Input Pulse Levels 0V to Vcc 0.4V to 2.4V Input Rise and Fall Times 5ns 5ns Input and Output Timing Levels Vcc/2 1.5V K9F1GXXQ0M:Output Load (Vcc:1.8V +/-10%)

K9F1GXXU0M:Output Load (Vcc:3.0V +/-10%) K9F1GXXU0M:Output Load (Vcc:3.3V +/-10%) - 1 TTL GATE and CL=100pF

1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE ALE CE WE RE WP PRE Mode

H L L H X X L H L H X X Address Input(4clock) H L L H H X L H L H H X Address Input(4clock) L L L H H X Data Input L L L H X X Data Output X X X X H X X During Read(Busy) X X X X X H X During Program(Busy) X X X X X H X During Erase(Busy) X X X H X X

NOTE : 1. X can be VIL or VIH.

2. WP and PRE should be biased to CMOS high or CMOS low for standby.

(1)

X X X L X Write Protect

(2)

0V/VCC

Read Mode

Write Mode

(2)

Stand-by

Command Input

Program / Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 300 700 µs Dummy Busy Time for Cache Program tCBSY 3 700

Number of Partial Program Cycles in the Same Page

Block Erase Time tBERS - 2 3 ms

NOTE : 1. Max. time of tCBSY depends on timing between internal program completion and data in

Main Array

Spare Array - - 4 cycles

Nop

- - 4 cycles

µs

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FLASH MEMORY

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol Min Max Unit

CLE setup Time tCLS 0 - ns CLE Hold Time tCLH 10 - ns CE setup Time tCS 0 - ns CE Hold Time WE Pulse Width tWP ALE setup Time tALS 0 - ns ALE Hold Time Data setup Time tDS 20 - ns Data Hold Time Write Cycle Time tWC 45 - ns WE High Hold Time

NOTE :

1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.

tCH 10 - ns

(1)

tALH 10 -

tDH 10 - ns

tWH 15 - ns

- ns

AC Characteristics for Operation

Parameter Symbol Min Max Unit

Data Transfer from Cell to Register tR - 25 µs ALE to RE Delay tAR 10 - ns CLE to RE Delay tCLR 10 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 25 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 50 - ns RE Access Time tREA - 30 ns CE Access Time tCEA - 45 ns RE High to Output Hi-Z tRHZ - 30 ns CE High to Output Hi-Z RE or CE High to Output hold tOH 15 - ns RE High Hold Time tREH 15 - ns Output Hi-Z to RE Low tIR 0 - ns WE High to RE Low tWHR 60 - ns Device Resetting Time(Read/Program/Erase) tRST -

NOTE :

1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

tCHZ - 20 ns

5/10/500

(1)

µs

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FLASH MEMORY

NAND Flash Technical Notes

Invalid Block(s)

Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.

Identifying Invalid Block(s)

All device locations are erased(FFh for X8, FFFFh for X16) except locations where the invalid block(s) information is written prior to shipping. The invalid block(s) status is defined by the 1st byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFh(X8) or non-FFFFh(X16) data at the column address of 2048(X8 device) or 1024(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the original invalid block information is prohibited.

Increment Block Address

Create (or update)

Invalid Block(s) Table

Start

Set Block Address = 0

Check "FFh

or FFFFh" ?

Yes

Last Block ?

Yes

End

Check "FFh( or FFFFh)" at the column address

2048(X8 device) or 1024(X16 device)

of the 1st and 2nd page in the block

Figure 3. Flow chart to create invalid block table.

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FLASH MEMORY

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block.To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks.

Failure Mode Detection and Countermeasure sequence

Erase Failure Status Read after Erase --> Block Replacement

Write

Read Single Bit Failure Verify ECC -> ECC Correction

Program Failure

Status Read after Program --> Block Replacement Read back ( Verify after Program) --> Block Replacement

or ECC Correction

ECC

Program Flow Chart

Program Error

: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

Yes

I/O 0 = 0 ?

Yes

: If program operation results in an error, map out

the block including the page in error and copy the target data to another block.

If ECC is used, this verification operation is not needed.

Write 00h

Write Address

Write 30h

Wait for tR Time

Verify Data

Program Completed

Pass

Fail

Program Error

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NAND Flash Technical Notes (Continued)

FLASH MEMORY

Erase Flow Chart

Erase Error

Start

Write 60h

Write Block Address

Write D0h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

Yes

I/O 0 = 0 ?

Yes

Read Flow Chart

Reclaim the Error

Start

Write 00h

Write Address

Write 30h

Read Data

ECC Generation

Verify ECC

Yes

Page Read Completed

Erase Completed

: If erase operation results in an error, map out

the failing block and replace it with another block.

Block Replacement

Block A

1st

∼

{

(n-1)th nth

(page)

1st

∼

(n-1)th nth

(page)

* Step1 When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2 Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’) * Step3 Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’. * Step4 Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

an error occurs.

Block B

{

Buffer memory of the controller.

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System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte(X8 device) or 1056word(X16 device) data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE don’t-care

FLASH MEMORY

ALE

I/Ox

tCS

Figure 5. Read Operation with CE don’t-care.

CLE

Address(4Cycles)80h Data Input

tCH

tWP

≈

I/O0~7

tCEA

tREA

Data Input

CE don’t-care

≈

10h

out

ALE

R/B

I/Ox

≈

Address(4Cycle)00h

30h

Data Output(serial access)

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NOTE

Device

K9F1G08X0B(X8 device) I/O 0 ~ I/O 7 ~2112byte A0~A7 A8~A11 A12~A19 A20~A27 K9F1G16X0B(X16 device) I/O 0 ~ I/O 15 ~1056word A0~A7 A8~A10 A11~A18 A19~A26

I/O DATA ADDRESS

I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2

FLASH MEMORY

* Command Latch Cycle

CLE

tCLS

tALS

ALE

I/Ox

K9F1G16X0M : I/O8~15 must be set to "0"

* Address Latch Cycle

tCLS

CLE

tCS

tWP

tDS

Command

tCLH

tCH

tALH

tDH

tCS

tWP

tALS

ALE

I/Ox

K9F1G16X0M : I/O8~15 must be set to "0"

Col. Add1

tWC

tDS

tWH

tALH tALS

tDH

tWP

tDS

Col. Add2

tWC

tWH

tALH tALS

tDH

tWP

tDS

Row Add1

tWC

tWH

tALH tALS

tDH

tWP

tALH

tDH

tDS

Row Add2

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* Input Data Latch Cycle

tCLH

CLE

≈

tCH

≈

FLASH MEMORY

tWP

tWC

tWP

tWH

tDH

tDS

DIN 0

NOTES : DIN final means 2112(X8) or 1056(X16)

tDS

DIN 1

≈

tDH

tALS

ALE

I/Ox

* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

tCEA

tREA

tRP

tREH

tREA

≈

tWP

≈

tDH

tDS

DIN final*

≈≈≈≈

tREA

tCHZ*

tOH

I/Ox

R/B

tRHZ*

Dout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

tRC

Dout

tRHZ*

tOH

Dout

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* Status Read Cycle

tCLR

CLE

I/Ox

K9F1G16X0M : I/O8~15 must be set to "0"

tCLS

tCS

tCLH

tCH

tWP

tWHR

tDH tREA

tDS

70h

tCEA

tIR*

FLASH MEMORY

tCHZ*

tOH

tRHZ*

tOH

Status Output

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Read Operation

tCLR

CLE

tWC

tWB

tAR

ALE

FLASH MEMORY

tRC

tRHZ

tOH

I/Ox

00h Col. Add1

Column Address

Col. Add2 Row Add1

R/B

Read Operation(Intercepted by CE)

CLE

ALE

Row Add2

Row Address

30h

tRR

Busy

tWB

Dout N Dout N+1

tAR

≈

≈≈

Dout M

tCHZ

tOH

I/Ox

R/B

00h

Col. Add1

Column Address

Col. Add2

Row Add1 Row Add2

Row Address

30h

tRR

Busy

Dout N

tRC

Dout N+1

Dout N+2

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FLASH MEMORY

tREA

tCLR

tWHR

tRC

Dout M Dout M+1

E0h

Col Add2

Col Add1

Column Address

Dout N+1

Dout N

tAR

tRR

Busy

tWB

30h 05h

Row Add2

Row Address

Col. Add2 Row Add1

Col. Add1

Column Address

00h

Random Data Output In a Page

CLE

ALE

I/Ox

R/B

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Page Program Operation

CLE

tWC

≈

tWB

ALE

≈≈

I/Ox

R/B

80h 70h I/O0

SerialData

Input Command

Co.l Add1

Col. Add2 Row Add1

Column Address Row Address

Row Add2

Din

1 up to m Byte

Serial Input

X8 device : m = 2112byte X16 device : m = 1056word

Din

10h

Program Command

FLASH MEMORY

tPROG

Read Status Command

≈

I/O0=0 Successful Program I/O0=1 Error in Program

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tPROG

tWB

10h

≈

Din

≈≈

Din

FLASH MEMORY

Read Status

Command

≈

Program

Command

Serial Input

Col. Add2

Column Address

Col. Add1

tWC

85h

Random Data

Input Command

Din

≈≈

≈

Serial Input

Din

Row Add2

tWC

Col. Add2 Row Add1

Column Address Row Address

Col. Add1

tWC

Page Program Operation with Random Data Input

CLE

ALE

80h 70h I/O0

Serial Data

Input Command

I/Ox

R/B

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Read Status

tPROG

tWB

10h

Data N

≈ ≈

Data 1

Row Add2

FLASH MEMORY

Command

≈

I/O0=0 Successful Program

I/O0=1 Error in Program

Busy

Row Address

Col Add2 Row Add1

Col Add1

Column Address

85h

≈

Copy-Back Data

Input Command

Busy

tWB

35h

Row Add2

Row Address

Col Add2 Row Add1

Col Add1

Column Address

tWC

00h 70h I/O0

Copy-Back Program Operation with Random Data Input

CLE

ALE

I/Ox

R/B

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I/O

70h

≈

tPROG

FLASH MEMORY

70h

tPROG

10h

tWB

10h

(True)

Command

Program Confirm

Din

≈

Din

Col Add2 Row Add1 Row Add2

Col Add1

Last Page Input & Program

tCBSY

Address &

Data Input

80h

15h

Address &

Data Input

80h

tCBSY

80h

15h

≈

Address &

tCBSY

tWB

15h

Program

Command

(Dummy)

Din

≈

≈≈

Din

Serial Input

CBSY :

max. 700us

tCBSY

Data Input

80h

15h

Row Add2

Row Address

Col Add2 Row Add1

Col Add1

Column Address

tWC

Cache Program Operation(available only within a block)

CLE

ALE

80h

Serial Data

I/Ox

Max. 63 times repeatable

Ex.) Cache Program

Input Command

R/B

Data

Address &

Data Input

Col Add1,2 & Row Add1,2

80h

I/Ox

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BLOCK ERASE OPERATION

CLE

tWC

tWB

ALE

tBERS

FLASH MEMORY

I/Ox

R/B

Row Add1 Row Add2

60h

Auto Block Erase Setup Command

Row Address

D0h 70h I/O 0

Busy

Erase Command

≈

Read Status Command

I/O0=0 Successful Erase I/O0=1 Error in Erase

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Read ID Operation

CLE

FLASH MEMORY

ALE

I/Ox

Read ID Command Maker Code

90h

Address. 1cycle

K9F1G08Q0M A1h 15h

K9F1G08U0M F1h 15h

K9F1G16Q0M B1h 55h

K9F1G16U0M C1h 55h

ID Defintition Table 90 ID : Access command = 90H

tAR

tREA

00h ECh

Device Device Code*(2nd Cycle) 4th Cycle*

Device Code*

Device Code

XXh

4th cyc.*

Byte

2nd Byte 3rd Byte

Byte

Description

Maker Code Device Code Don’t care Page Size, Block Size, Spare Size, Organization,Serial access minimum

SAMSUNG

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K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

4th ID Data

Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Page Size (w/o redundant area )

Blcok Size (w/o redundant area )

Redundant Area Size ( byte/512byte)

Organization

Serial Access minimum

1KB 2KB Reserved Reserved

64KB 128KB 256KB Reserved

8 16

x8 x16

50ns 30ns Reserved Reserved

0 0 0 1 1 0 1 1

0 1

0 0 1 1

FLASH MEMORY

0 0 0 1 1 0 1 1

0 1

0 1 0 1

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K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

Device Operation

PAGE READ

Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with four address cycles. In two consecutive read operations, the second one doesn’t need 00h command, which five address cycles and 30h command initiates that operation.Two types of operations are available : random read, serial page read The random read mode is enabled when the page address is changed. The 2112 bytes(X8 device) or 1056 words(X16 device) of data within the selected page are transferred to the data registers in less than 25µs(tR). The system controller can detect the com- pletion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 50ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

CLE

ALE

R/B

I/Ox

Address(4Cycle)00h

Col Add1,2 & Row Add1,2

30h

Data Output(Serial Access)

Data Field Spare Field

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K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

Figure 7. Random Data Output In a Page

FLASH MEMORY

R/B

I/Ox

00h

PAGE PROGRAM

Address 4Cycles

Col Add1,2 & Row Add1,2

30h

Data Field

Data Output

Spare Field

05h

Address 2Cycles

E0h

Data Field

Data Output

Spare Field

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112(X8 device) or words up to 1056(X16 device), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(X8 device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte ,X16 device:1time/ 8word). The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes(X8 device) or 1056words(X16 device) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.

Figure 8. Program & Read Status Operation

tPROG

R/B

"0"

I/Ox

80h

Address & Data Input I/O0

Col Add1,2 & Row Add1,2

Data

10h 70h

"1"

Fail

Pass

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K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

Figure 9. Random Data Input In a Page

FLASH MEMORY

R/B

tPROG

"0"

I/Ox

80h

Address & Data Input

Col Add1,2 & Row Add1,2

Data

85h

Address & Data Input

Col Add1,2

Data

10h 70h

I/O0

"1"

Fail

Cache Program

Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell.

After writing the first set of data up to 2112byte(X8 device) or 1056word(X16 device) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be progammed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/ O5) must be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/ O 1 may be read together when I/O 0 is checked.

Figure 10. Cache Program(available only within a block)

R/B

tCBSY

tPROG

Pass

R/B

I/Ox

Address &

80h

Data Input*

Col Add1,2 & Row Add1,2 Col Add1,2 & Row Add1,2

Data Data

15h

80h

Address & Data Input

tCBSY

Address &

80h

Data Input

Col Add1,2 & Row Add1,2

Data

15h

70h

Status

output

80h

Col Add1,2 & Row Add1,2

tCBSY

70h

Status

output

Address &

80h

Data Input

Col Add1,2 & Row Add1,2

Data

15h

80h

15h

Col Add1,2 & Row Add1,2

Address &

Data Input

Data

70h

Check I/O1 for pass/fail

Address & Data Input

Data

tCBSY

15h

Status

output

70h

15h

Status

output

Status

output

Check I/O5 for internal ready/busy Check I/O0,1 for pass/fail

Data Input

Col Add1,2 & Row Add1,2

Data

Address &

80h

Data Input

Col Add1,2 & Row Add1,2

Data

Address &

80h

SAMSUNG

10h

70h

tCBSY

15h

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K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if

the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula.

tPROG= Program time for the last page+ Program time for the ( last -1 )th page

- (Program command cycle time + Last page data loading time)

FLASH MEMORY

Copy-Back Program

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2112byte(X8 device) or 1056word(X16 device) data into the internal data buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (85h) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 12. "When there is a program-failure at Copy-Back operation,

error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."

Figure 11. Page Copy-Back program Operation

tPROG

R/B

I/Ox

Add.(4Cycles)

00h

Col. Add1,2 & Row Add1,2

Source Address

35h

Add.(4Cycles)

85h 70h

Col. Add1,2 & Row Add1,2

Destination Address

10h

Figure 12. Page Copy-Back program Operation with Random Data Input

R/B

I/Ox

Add.(4Cycles)

00h

Col. Add1,2 & Row Add1,2

Source Address

35h

Add.(4Cycles)

85h

Col. Add1,2 & Row Add1,2

Destination Address

Data

85h

There is no limitation for the number of repetition.

Add.(2Cycles)

Col Add1,2

Data

I/O0

Fail

10h

Pass

tPROG

70h

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K9F1G08U0M-VCB0,VIB0,FCB0,FIB0 K9F1G08Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G16Q0M-YCB0,YIB0,PCB0,PIB0 K9F1G08U0M-YCB0,YIB0,PCB0,PIB0 K9F1G16U0M-YCB0,YIB0,PCB0,PIB0

FLASH MEMORY

BLOCK ERASE

The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A18 to A27(X8) or A17 to A26(X16) is valid while A12 to A17(X8) or A11 to A16(X16) is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.

Figure 13. Block Erase Operation

R/B

tBERS

"0"

I/Ox

60h

Address Input(2Cycle)

Block Add. : A12 ~ A27 (X8)

or A11 ~ A26 (X16)

D0h

70h

I/O0

"1"

Fail

Pass

READ STATUS

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.

Table2. Read Staus Register Definition

I/O No. Page Program Block Erase Cache Prorgam Read Definition

I/O 0 Pass/Fail Pass/Fail Pass/Fail(N) Not use Pass : "0" Fail : "1" I/O 1 Not use Not use Pass/Fail(N-1) Not use Pass : "0" Fail : "1" I/O 2 Not use Not use Not use Not use "0" I/O 3 Not Use Not Use Not Use Not Use "0" I/O 4 Not Use Not Use Not Use Not Use "0" I/O 5 Ready/Busy Ready/Busy True Ready/Busy Ready/Busy Busy : "0" Ready : "1" I/O 6 Ready/Busy Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "1" I/O 7 Write Protect Write Protect Write Protect Write Protect Protected:"0" Not Protected:"1"

I/O 8~15

(X16 device

only)

Not use Not use Not use Not use Don’t -care

NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.

2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.

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FLASH MEMORY

Read ID

The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.

Figure 14. Read ID Operation

CLE

tCLR

tCEA

tAR

ALE

I/OX

90h

00h

Address. 1cycle

K9F1G08Q0M A1h 15h K9F1G08U0M F1h 15h K9F1G16Q0M B1h 55h K9F1G16U0M C1h 55h

tWHR

Device Device Code*(2nd Cycle) 4th Cycle*

tREA

ECh

Maker code

Device

Code*

Device code

XXh 4th Cyc.*

RESET

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 15 below.

Figure 15. RESET Operation

tRST

R/B

I/OX

FFh

Table3. Device Status

After Power-up After Reset

PRE status High Low

Operation Mode First page data access is ready 00h command is latched

Waiting for next command

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Power-On Auto-Read

The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of autopage read function. Auto-page read function is enabled only when PRE pin is tied to Vcc. Serial access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device(K9F1GXXU0M).

Figure 15. Power-On Auto-Read (3.3V device only)

FLASH MEMORY

VCC

CLE

ALE

PRE

R/B

I/OX

~ 1.8V

≈

≈≈ ≈ ≈ ≈≈ ≈

1st

2nd 3rd .... n th

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FLASH MEMORY

READY/BUSY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 16). Its value can be determined by the following guidance.

VCC

R/B

open drain output

ibusy

Ready Vcc

1.8V device - VOL : 0.1V, VOH : VCCq-0.1V

3.3V device - VOL : 0.4V, VOH : 2.4V

VOH

GND

Device

Fig 16 Rp vs tr ,tf & Rp vs ibusy

@ Vcc = 1.8V, Ta = 25

1.7

Ibusy

0.85

1.7

300n 3m

tr,tf [s]

200n

100n

1K 2K 3K

C , CL = 30pF

1.7

Rp(ohm)

0.57

120

0.43

1.7

Rp value guidance

VOL

Busy

@ Vcc = 3.3V, Ta = 25

2.4

300n 3m

tr,tf [s]

200n

Ibusy [A]

Ibusy

1.2

200

C , CL = 100pF

400

300

0.8

100n

100

3.6

1K 2K 3K

0.6

3.6

Rp(ohm)

Ibusy [A]

Rp(min, 1.8V part) =

Rp(min, 3.3V part) =

VCC(Max.) - VOL(Max.)

IOL + ΣIL

VCC(Max.) - VOL(Max.)

IOL + ΣIL

where IL is the sum of the input currents of all devices tied to the R/B pin.

Rp(max) is determined by maximum permissible limit of tr

1.85V

3mA + ΣIL

3.2V

8mA + ΣIL

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Data Protection & Power up sequence

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 17. The two step command sequence for program/erase provides additional software protection.

Figure 17. AC Waveforms for Power Transition

FLASH MEMORY

VCC

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

10µs

High

≈

1.8V device : ~ 1.5V

3.3V device : ~ 2.5V

≈

≈≈

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