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© 2015 International Rectifier
April 14, 2015
Features
Floating channel designed for bootstrap operation
Fully operational to 200V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground +/-5V offset
CMOS Schmitt-triggered inputs with pull-down
Shut down input turns off both channels
Cross-conduction prevention logic
Matched propagation delay for both channels
Outputs in phase with inputs
Description
The IR2010 is a high power, high voltage, high speed power
MOSFET and IGBT driver with independent high and low
side referenced output channels. Logic inputs are compatible
with standard CMOS or LSTTL output, down to 3.0V logic.
The output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. Propagation
delays are matched to simplify use in high frequency
applications. The floating channel can be used to drive an Nchannel power MOSFET or IGBT in the high side
configuration which operates up to 200 volts. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction.
Applications
Converters
DC motor drive
Product Summary
V
OFFSET
(max)
200V
I
O+/-
(typ)
3.0A / 3.0A
V
OUT
10 – 20V
t
on/off
(typ)
Delay Matching (max)
95ns & 65ns
15ns
Package Options
14-Lead PDIP 16-Lead SOIC
Wide Body
Base Part Number
Package Type
Standard Pack
Orderable Part Number
Form
Quantity
IR2010PBF
PDIP14
Tube
25
IR2010PBF
IR2010SPBF
SO16W
Tube
45
IR2010SPBF
IR2010SPBF
SO16W
Tape and Reel
1000
IR2010STRPBF
High and Low Side Driver
Ordering Information
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© 2015 International Rectifier
April 14, 2015
SD
LIN
V
SS
V
CC
LO
V
SS
HIN
V
DD
To Load
COM
200V
V
B
HO
V
S
HIN
V
DD
SD
LIN
V
CC
Typical Connection Diagram
(Refer to Lead Assignments for correct configuration.) This diagram shows electrical connections only. Please refer to our Application Notes
and Design Tips for proper circuit board layout
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April 14, 2015
Symbol
Definition
Min.
Max.
Units
VB
High side floating supply voltage
-0.3
225
V
VS
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low side fixed supply voltage
-0.3
25
VLO
Low side output voltage
-0.3
VCC + 0.3
VDD
Logic supply voltage
-0.3
VSS + 25
VSS
Logic supply offset voltage
VCC - 25
VCC + 0.3
VIN
Logic input voltage (HIN, LIN & SD)
VSS - 0.3
VDD + 0.3
dVs/dt
Allowable offset supply voltage transient (figure 2)
—
50
V/ns
PD
Package power dissipation
@ TA ≤ +25°C
14-Lead PDIP
—
1.6
W
16-Lead SOIC
—
1.25
RthJA
Thermal resistance, junction to
ambient
14-Lead PDIP
—
75
°C/W
16-Lead SOIC
—
100
TJ
Junction temperature
—
150
°C
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within
the recommended conditions. The VS and VSS offset rating is tested with all supplies biased at 15V differential.
Typical ratings at other bias conditions are shown in figures 24 and 25.
Symbol
Definition
Min.
Max.
Units
VB
High side floating supply absolute voltage
VS + 10
VS + 20
V
VS
High side floating supply offset voltage
†
200
V
HO
High side floating output voltage
VS
VB
VCC
Low side fixed supply voltage
10
20
V
LO
Low side output voltage
0
V
CC
VDD
Logic supply voltage
VSS + 3
VSS + 20
VSS
Logic supply offset voltage
-5††
5
V
IN
Logic input voltage (HIN, LIN, & SD)
VSS
VDD
TA
Ambient temperature
-40
125
°C
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
† Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS.
†† When VDD < 5V, the minimum VSS offset is limited to -V
(Please refer to the Design Tip DT97-3 for more details).
DD
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April 14, 2015
Dynamic Electrical Characteristics
V
BIAS
(VCC, VBS, VDD) = 15V, CL = 1000pF and TA = 25°C and VSS = COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in figure 3.
Symbol
Definition
Figure
Min.
Typ.
Max.
Units
Test Conditions
t
on
Turn-on propagation delay
7
50
95
135
ns
VS = 0V
t
off
Turn-off propagation delay
8
30
65
105
VS = 200V
tsd
Shutdown propagation delay
9
35
70
105
tr
Turn-on rise time
10
—
10
20 tf
Turn-off fall time
11
—
15
25
MT
Delay matching, HS & LS turn-on/off
6
— — 15
Static Electrical Characteristics
V
BIAS
(VCC, VBS, VDD) = 15V and TA = 25°C and V
SS
= COM unless otherwise specified. The VIN, VTH and IIN
parameters are referenced to V
SS
and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO
parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
Definition
Figure
Min.
Typ.
Max.
Units
Test Conditions
VIH
Logic “1” input voltage
12
9.5
—
—
V
VDD = 15V
V
IL
Logic “0” input voltage
13
—
—
6.0
VIH
Logic “1” input voltage
12 2 —
—
VDD = 3.3V
V
IL
Logic “0” input voltage
13 — —
1
VOH
High level output voltage, V
BIAS
- VO
14
— — 1.0
IO = 0A
V
OL
Low level output voltage, VO
15
— — 0.1
ILK
Offset supply leakage current
16
—
—
50
μA
VB = VS = 200V
I
QBS
Quiescent VBS supply current
17 — 70
210
VIN = 0V or VDD
I
QCC
Quiescent VCC supply current
18
—
100
230
I
QDD
Quiescent VDD supply current
19 — 1
5
I
IN+
Logic “1” input bias current
20
—
20
40
VIN = VDD
I
IN-
Logic “0” input bias current
21
— — 1.0
VIN = 0V
V
BSUV+
VBS supply undervoltage positive
going threshold
22
7.5
8.6
9.7
V
V
BSUV-
VBS supply undervoltage negative
going threshold
23
7.0
8.2
9.4
V
CCUV+
VCC supply undervoltage positive
going threshold
24
7.5
8.6
9.7
V
CCUV-
V
CC
supply undervoltage negative
going threshold
25
7.0
8.2
9.4
I
O+
Output high short circuit pulsed
current
26
2.5
3.0
—
A
VO = 0V, VIN = VDD
PW ≤ 10 μs
IO-
Output low short circuit pulsed
current
27
2.5
3.0
—
VO = 15V, VIN = 0V
PW ≤ 10 μs
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Functional Block Diagram
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Symbol
Description
VDD
Logic Supply
HIN
Logic input for high side gate driver outputs (HO), in phase
SD
Logic input for shutdown
LIN
Logic input for low side gate driver outputs (LO), in phase
VSS
Logic ground
VB
High side floating supply
HO
High side gate drive output
VS
High side floating supply return
V
CC
Low side supply
LO
Low side gate drive output
COM
Low side return
14-Lead PDIP
16-Lead SOIC (Wide Body)
Lead Definitions
Lead Assignments
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April 14, 2015
HIN
LIN
SD
HO
LO
HO
10KF6
0.1µF
HIN
LIN
V
SS
LO
V
DD
HO
V
CC
= 15V
10µF
VCCV
B
V
S
OUTPUT
MONITOR
SD
COM
100µF
HV = 10 to 200V
0.1µF
+
10KF6
200µH
10KF6 dV
S
dt
<50 V/ns
IRF820
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test
Circuit
C
L
V
B
HIN HO
LIN
0.1µF
0.1µF
HIN
LIN
V
SS
LO
V
DD
HO
V
CC
= 15V
C
L
10µF
VCCV
B
10µF
V
S
V
S
+
-
15V
LO
SD
SD
COM
10µF
(0 to 200V)
HO
LO
50%
50%
10% 10%
90%
90%
t
on
t
r
t
off
t
f
HIN
LIN
Figure 3. Switching Time Test Circuit
Figure 4. Switching Time Waveform Definition
HO
LO
SD
50%
t
sd
90%
50%
50%
10%
90%
HIN
LIN
MT
LO HO
MT
LO
HO
Figure 5. Shutdown Waveform Definitions
Figure 6. Delay Matching Waveform Definitions
Application Information and Additional Details
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April 14, 2015
Figure 7A. Turn-on Time vs. Temperature
Figure 7B. Turn-on Time vs. VCC/VBS Voltage
Figure 7C. Turn-on Time vs. VDD Voltage
Figure 8A. Turn-off Time vs. Temperature
Figure 8B. Turn-off Time vs. VCC/VBS Voltage
Figure 8C. Turn-off Time vs. V
DD
Voltage
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April 14, 2015
Figure 9A. Shutdown Time vs. Temperature
Figure 9B. Shutdown Time vs. VCC/VBS Voltage
Figure 9C. Shutdown Time vs. VDD Voltage
Figure 10A. Turn-on Rise Time vs. Temperature
Figure 10B. Turn-on Rise Time vs. V
BIAS
(VCC=VBS=VDD) Voltage
Figure 11A. Turn-off Fall Time vs. Temperature
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April 14, 2015
Figure 11B. Turn-Off Fall Time vs. V
BIAS
(VCC=VBS=VDD) Voltage
Figure 12A. Logic “1” Input Threshold vs.
Temperature
Figure 12B. Logic “1” Input Threshold vs. V
DD
Voltage
Figure 13A. Logic “0” Input Threshold vs.
Temperature
Figure 13B. Logic “0” Input Threshold vs. V
DD
Voltage
Figure 14A. High Level Output vs. Temperature
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April 14, 2015
Figure 14B. High Level Output vs. V
BIAS
Voltage
Figure 15A. Low Level Output vs. Temperature
Figure 15B. Low Level Output vs. V
BIAS
Voltage
Figure 16A. Offset Supply Current vs. Temperature
Figure 16B. Offset Supply Current vs. Offset
Voltage
Figure 17A. VBS Supply Current vs. Temperature
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April 14, 2015
Figure 17B. VBS Supply Current vs. VBS Voltage
Figure 18A. VCC Supply Current vs. Temperature
Figure 18B. VCC Supply Current vs. VCC Voltage
Figure 19A. VDD Supply Current vs. Temperature
Figure 19B. V
DD
Supply Current vs. V
DD
Voltage
Figure 20A. Logic “1”Input Current vs. Temperature
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April 14, 2015
Figure 20B. Logic “1” Input Current vs. V
DD
Voltage
Figure 21A. Logic “0” Input Current vs.
Temperature
Figure 21B. Logic “0” Input Current vs. V
DD
Voltage
Figure 22. V
BS
Undervoltage (+) vs. Temperature
Figure 23. VBS Undervoltage (-) vs. Temperature
Figure 24. VCC Undervoltage (+) vs. Temperature
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Figure 25. VCC Undervoltage (-) vs. Temperature
Figure 26A. Output Source Current vs. Temperature
Figure 26B. Output Source Current vs. V
BIAS
Voltage
Figure 27A. Output Sink Current vs. Temperature
Figure 27B. Output Sink Current vs. V
BIAS
Voltage
Figure 28. IR2010 Tj vs. Frequency
R
GATE
= 10Ω, VCC = 15V with IRFPE50
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April 14, 2015
Figure 29. IR2010 Tj vs. Frequency
R
GATE
= 16Ω, VCC = 15V with IRFBC40
Figure 30. IR2010 Tj vs. Frequency
R
GATE
= 22Ω, VCC = 15V with IRFBC30
Figure 31. IR2010 Tj vs. Frequency
R
GATE
= 33Ω, VCC = 15V with IRFBC20
Figure 32. IR2010 Tj vs. Frequency
R
GATE
= 10Ω, VCC = 15V with IRFBE50
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April 14, 2015
Figure 33. IR2010S Tj vs. Frequency
R
GATE
= 16Ω, VCC = 15V with IRFBC40
Figure 34. IR2010S Tj vs. Frequency
R
GATE
= 22Ω, VCC = 15V with IRFBC30
Figure 35. IR2010S Tj vs. Frequency
R
GATE
= 33Ω, VCC = 15V with IRFBC20
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Package Details
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April 14, 2015
E
F
ACDGA
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
GDB
C
CARRIER TAPE DIMENSION FOR 16SOICW
Code Min Max Min Max
A 11.90 12.10 0.468 0.476
B 3.90 4.10 0.153 0.161
C 15.70 16.30 0.618 0.641
D 7.40 7.60 0.291 0.299
E 10.80 11.00 0.425 0.433
F 10.60 10.80 0.417 0.425
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062
Metric
Imperial
REEL DIMENSIONS FOR 16SOICW
Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 22.40 n/a 0.881
G 18.50 21.10 0.728 0.830
H 16.40 18.40 0.645 0.724
Metric
Imperial
Tape and Reel Details
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April 14, 2015
IRxxxxx
IR logo
YWW ?
Part number
Date code
Pin 1
Identifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
? XXXX
MARKING CODE
Lead Free Released
Non-Lead Free Released
?
P
Part Marking Information
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April 14, 2015
Qualification Level
Industrial††
(per JEDEC JESD 47)
Comments: This family of ICs has passed JEDEC’s
Industrial qualification. IR’s Consumer qualification level is
granted by extension of the higher Industrial level.
Moisture Sensitivity Level
16-Lead SOIC WB
MSL3
†††
(per IPC/JEDEC J-STD-020)
RoHS Compliant
Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
††
Higher qualification ratings may be available should the user have such requirements. Please contact your
International Rectifier sales representative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of
other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any
patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This
document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
Qualification Information†
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