Page 1
Integrated
Circuit
Systems, Inc.
ICS9250-22
Third party brands and names are the property of their respective owners.
9250-22 Rev B 12/08/00
Pin Configuration
56-Pin 300mil SSOP & TSSOP
Recommended Application:
P IV Chipset Support
Output Features:
• 4 Differential CPU Clock Pairs @ 3.3V
• 2 - 3V MREF clocks for memory reference seeds,
(separate single ended but 180 degrees out of phase)
• 4 - 66MHz reference output
• 10 - 3V 33MHz PCI clocks
• 2 - 48MHz clocks
• 2 - 14.318 reference output
Features:
• Support power management: Power Down Mode
• Supports Spread Spectrum modulation: 0 to -0.5% down
spread.
• Uses external 14.318MHz crystal
• Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum, limited
frequency select, selective clock enable.
• External resistor for current reference
• FS pins for frequency select
Key Specifications:
• 3V66 Output jitter <300ps
• CPU Output Jitter <200ps
• MREF Output jitter <250ps
Frequency Generator for P IV™
GND
REF
VDDREF
X1
X2
GNDREF
PCICLK0
PCICLK1
VDDPCI
PCICLK2
PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
VDDPCI
SEL100/133
GND48
48MHz
48MHz
VDD48
PD#
MULTSEL0/
MULTSEL1/REF
FS0/
FS1/
VDDMREF
3VMREF
3VMREF_B
GNDMREF
SPREAD#
CPUCLKST3
CPUCLKSC3
VDDCPU
CPUCLKST2
CPUCLKSC2
GNDCPU
CPUCLKST1
CPUCLKSC1
VDDCPU
CPUCLKST0
CPUCLKSC0
GNDCPU
I REF
VDDA
GNDA
VDD3V66
3V66-3
3V66-2
GND3V66
GND3V66
3V66-1
3V66-0
VDD3V66
ICS9250-22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Functionality
PLL2
PLL1
Spread
Spectrum
48MHz
3VMREF
PCICLK (9:0)
3VMREF_B
3V66 (3:0)
4
10
2
2
X1
X2
XTAL
OSC
CPU
DIVDER
3VMREF
DIVDER
PCI
DIVDER
3V66
DIVDER
PD#
SPREAD#
MULTSEL (1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
REF
4
4
CPUCLKST (3:0)
CPUCLKSC (3:0)
/331LES
001
0SF1SFnoitcnuF
000 zHM001evitcA
001 )devreseR(
010 )devreseR(
011 stuptuollaetatsirT
100 zHM331evitcA
101 )devreseR(
110 )devreseR(
111 edoMtseT
Block Diagram
Po wer Groups
VDDREF , GNDREF= REF, X1, X2
VDDPCI, GNDPCI = PCICLK
VDD48, GND48 = 48MHz, PLL2
VDD3V66, GND3V66=3V66
VDDCPU, GNDCPU = CPUCLK
VDDMREF , GNDMREF=3VMREF, 3VMREF_B
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Page 2
2
ICS9250-22
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
The ICS9250-22 is a single chip clock solution.
Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-22 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and temperature variations.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,23,42,91,31,7,1
35,64,04,73,33
DNGRWPylppusV3.3rofsnipdnuorG
2,3)0:1(LESTLUM/FERNI
dnapu-rewopnodesneserastupni1LESTLUMdna0LESTLUM
V3notuptuorofdesugniebnipehtotroirpdehctalyllanretnineht
.skcolczHM813.41
,92,72,22,61,01,4
65,94,34,83,63
DDVRWPylppusrewopV3.3
51XtupnIlatsyrC2XtupnilatsyrCzHM813.41
62XtuptuOlatsyrC1XtuptuolatsyrCzHM813.41
,51,71,81,02,12
8,9,11,21,41
)0:9(KLCICPTUOstuptuokcolcICP
32331/001LESNIzHM331=hgiH,zHM001=woL.tceleSycneuqerFUPC
52,62
)0:1(SFNIsniptcelesycneuqerF
zHM84TUOtuptuokcolczHM84
82#DPNI.woLevitcA.edomnwod-rewopsekovnI
03,13,43,53)0:3(66V3TUOskcolcecnereferzHM66
93FERITUO
.sriapKLCUPCehtroftnerrucecnereferehtsehsilbatsenipsihT
otredronidnuorgotdeitrotsisernoisicerpdexifasekatnipsihT
.tnerrucetairporppaehthsilbatse
24,54,84,15)0:3(TSKLCUPCTUO
dehctiwseraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT"
.saibegatlovrofderiuqererasrotsiserlanretxednastuptuotnerruc
14,44,74,05)0:3(CSKLCUPCTUO
esehT.stuptuoUPCriaplaitnereffidfoskcolc"yrotnemelpmoC"
rofderiuqererasrotsiserlanretxednastuptuotnerrucdehctiwsera
.saibegatlov
25#DAERPSNI
tsohlaitnereffiDehtnoytilanoitcnufmurtcepSdaerpSsekovnI
ICPzHM33dna,skcolczHM66,skcolcb_feRM/feRM,skcolc
woLevitcA.skcolc
45B_FERMV3TUO
revirdkcolcyromemotecnereferV3
)fermV3htiwesahpfotuo(
55FERMV3TUOrevirdkcolcyromemotecnereferV3
Page 3
3
ICS92 50-22
Third party brands and names are the property of their respective owners.
Truth Table
Group Offset Limits
puorGtesffO
sdaoLtnemerusaeM
)depmul(
stnioPerusaeM
66V3otUPCtnemeriuqeRoN
ICPotUPC
ICPot66V3
sn5.3-5.1
sdael66V3
Fp03V5.1
LES
001/331
0SF1SFUPCfeRM66V3ICPzHM84FER
000 zHM001zHM05zHM66zHM33zHM84zHM813.41
001A/NA/NA/NA/NA/NA/N
010A/NA/NA/NA/NA/NA/N
011 etatsirTetatsirTetatsirTetatsirTetatsirTetatsirT
100 zHM331zHM66zHM66zHM33zHM84zHM813.41
101A/NA/NA/NA/NA/NA/N
110A/NA/NA/NA/NA/NA/N
111 2/KLCT4/KLCTKLCT6/KLCTKLCT
Page 4
4
ICS9250-22
Third party brands and names are the property of their respective owners.
CPUCLK Buffer Configuration
snoitidnoCnoitarugifnoCdaoLniMxaM
tuoI
)V03.3(lanimon=ddV
,0MfosnoitanibmocllA
ninwohsrRdna1M
wolebelbat
rofdaoltsetlanimoN
noitarugifnocnevig
%7- I lanimon%7+ I lanimon
tuoI
%5±03.3=ddV
,0MfosnoitanibmocllA
ninwohsrRdna1M
wolebelbat
rofdaoltsetlanimoN
noitarugifnocnevig
%21- I lanimon%21+ I lanimon
0LESTLUM1LESTLUM
tegraTdraoB
ZmreT/ecarT
,RecnerefeR
=ferI
)rR*3(/ddV
tuptuO
tnerruC
,Z@hoV
Am23.2=ferI
00 smho06
%1574=rR
Am23.2=ferI
ferI*5=hoI06@V17.0
00 smho05
%1574=rR
Am23.2=ferI
ferI*5=hoI05@V95.0
01 smho06
%1574=rR
Am23.2=ferI
ferI*6=hoI062/V58.0
01 smho05
%1574=rR
Am23.2=ferI
ferI*6=hoI05@V17.0
10 smho06
%1574=rR
Am23.2=ferI
ferI*4=hoI06@V65.0
10 smho05
%1574=rR
Am23.2=ferI
ferI*4=hoI05@V74.0
11 smho06
%1574=rR
Am23.2=ferI
ferI*7=hoI06@V99.0
11 smho05
%1574=rR
Am23.2=ferI
ferI*7=hoI05@V28.0
00 )viuqeCD(03
%1122=rR
Am5=ferI
ferI*5=hoI03@V57.0
00 )viuqeCD(52
%1122=rR
Am5=ferI
ferI*5=hoI02@V26.0
01 )viuqeCD(03
%1122=rR
Am5=ferI
ferI*6=hoI03@V09.0
01 )viuqeCD(52
%1122=rR
Am5=ferI
ferI*6=hoI02@V57.0
10 )viuqeCD(03
%1122=rR
Am5=ferI
ferI*4=hoI02@06.0
10 )viuqeCD(52
%1122=rR
Am5=ferI
ferI*4=hoI02@V5.0
11 )viuqeCD(03
%1122=rR
Am5=ferI
ferI*7=hoI03@V50.1
11 )viuqeCD(52
%1122=rR
Am5=ferI
ferI*7=hoI02@V48.0
CPUCLK Swing Select Functions
Page 5
5
ICS92 50-22
Third party brands and names are the property of their respective owners.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameter s
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
-5 5
µ
A
I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5
µ
A
I
IL2
VIN = 0 V; Inputs with pull-up resistors -200
Operating Supply
Current
I
DD3.3OP
CL = 0 pF; Select @ 100 MHz 130 250
mA
Powerdown Current
I
DD3.3PD
CL = 0 pF; Input address to VDD or GND
35 60
mA
Input Frequency F
i
VDD = 3.3 V 14.318 MHz
Pin Inductance L
pin
7nH
C
IN
Logic Inputs 5 pF
C
OUT
Output pin capacitance 6 pF
C
INX
X1 & X2 pins 27 45 pF
Transition time
1
T
trans
To 1st cr ossing of target frequency 3 ms
Settling time
1
T
s
From 1st crossing to 1% target frequency 3 ms
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target frequency 3 ms
t
PZH,tPZL
Output enable delay (all outputs) 1 10 ns
t
PHZ,tPLZ
Output disable delay (all outputs) 1 10 ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
Page 6
6
ICS9250-22
Third party brands and names are the property of their respective owners.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2B
1
VO = VDD*(0.5) 714 Ω
Output Impedance R
DSN2B
1
VO = VDD*(0.5) 714 Ω
Output High Voltage V
OH2B
IOH = -1 mA 2 V
Output Low Voltage V
OL2B
IOL = 1 mA 0.4 V
Output High Current
I
OH2B
2
V
OH@MIN
= 1.0 V, V
OH@MAX
= 2.375 V -27 -27
mA
Output Low Current
I
OL2B
2
V
OL @MIN
= 1.2 V, V
OL @MAX
= 0.3 V 2 7 30
mA
Rise Time t
r2B
1
VOL = 20%, VOH = 80% 175 500 700 ps
Fall Time t
f2B
1
VOH = 80%, VOL = 20% 175 500 700 ps
Duty Cycle
d
t2B
1
VT = 50% 45 51 55
%
Skew t
sk2B
1
VT = 50% 110 150 ps
Jitter
t
jcyc-cyc
1
VT = 50%
110 200 ps
1
Guaranteed by design, not 100% tested in production.
2
I
OWT
can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F
O1
MHz
Output Impedance R
DSP1
1
VO = VDD*(0.5) 12 33 55 Ω
Output High Volt age V
OH
1
IOH = -1 mA 2.4 V
Output Low Voltage V
OL
1
IOL = 1 mA 0.55 V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -33 -33
mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V 30 38
mA
Rise Time t
r1
1
VOL = 0.4 V, VOH = 2.4 V 0.5 1.4 2 ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 0.5 1.4 2 ns
Duty Cycle
d
t1
1
VT = 1.5 V 45 51 55
%
Skew t
sk1
1
VT = 1.5 V 270 500 ps
Jitter
t
jcyc-cyc
1
VT = 1.5 V
115 500 ps
1
Guaranteed by design, not 100% tested in production.
Page 7
7
ICS92 50-22
Third party brands and names are the property of their respective owners.
Electrical Characteristics - MREF/MREF_B
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F
O1
MHz
Output Impedance R
DSP1
1
VO = VDD*(0.5) 12 33 55 Ω
Output High Volt age V
OH
1
IOH = -1 mA 2.4 V
Output Low Voltage V
OL
1
IOL = 1 mA 0.55 V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -33 -33
mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V 30 38
mA
Rise Time t
r1
1
VOL = 0.4 V, VOH = 2.4 V 0.4 1.4 1.6 ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 0.4 1.4 1.6 ns
Duty Cycle
d
t1
1
VT = 1.5 V 45 51 55
%
Skew t
sk1
1
VT = 1.5 V 80 100 ps
Jitter
t
jcyc-cyc
1
VT = 1.5 V
105 250 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F
O1
MHz
Output Impedance R
DSP1
1
VO = VDD*(0.5) 20 48 60 Ω
Output High Volt age V
OH
1
IOH = -1 mA 2.4 V
Output Low Voltage V
OL
1
IOL = 1 mA 0.4 V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -29 -23
mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V 29 27
mA
Rise Time t
r1
1
VOL = 0.4 V, VOH = 2.4 V 124ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 124ns
Duty Cycle
d
t1
1
VT = 1.5 V 45 50 55
%
Skew t
sk1
1
VT = 1.5 V N/A ps
Jitter
t
jcyc-cyc
1
VT = 1.5 V
205 1000 ps
1
Guaranteed by design, not 100% tested in production.
Page 8
8
ICS9250-22
Third party brands and names are the property of their respective owners.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F
O1
MHz
Output Impedance R
DSP1
1
VO = VDD*(0.5) 20 48 60 Ω
Output High Volt age V
OH
1
IOH = -1 mA 2.4 V
Output Low Voltage V
OL
1
IOL = 1 mA 0.4 V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -29 -23
mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V 29 27
mA
Rise Time t
r1
1
VOL = 0.4 V, VOH = 2.4 V 124ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 124ns
Duty Cycle
d
t1
1
VT = 1.5 V 45 54 55
%
Skew t
sk1
1
VT = 1.5 V N/A ps
Jitter
t
jcyc-cyc
1
VT = 1.5 V
120 350 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F
O1
MHz
Output Impedance R
DSP1
1
VO = VDD*(0.5) 12 33 55 Ω
Output High Volt age V
OH
1
IOH = -1 mA 2.4 V
Output Low Voltage V
OL
1
IOL = 1 mA 0.55 V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MAX
= 3.135 V -33 -33
mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MAX
= 0.4 V 30 38
mA
Rise Time t
r1
1
VOL = 0.4 V, VOH = 2.4 V 0.5 1.3 2 ns
Fall Time t
f1
1
VOH = 2.4 V, VOL = 0.4 V 0.5 1.3 2 ns
Duty Cycle
d
t1
1
VT = 1.5 V 45 51 55
%
Skew t
sk1
1
VT = 1.5 V 85 250 ps
Jitter
t
jcyc-cyc
1
VT = 1.5 V
80 300 ps
1
Guaranteed by design, not 100% tested in production.
Page 9
9
ICS92 50-22
Third party brands and names are the property of their respective owners.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below.
Notes:
1. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
MREF
MREF_BAR
CPUCLKT
CPUCLKC
VCO
Crystal
PD#
Page 10
10
ICS9250-22
Third party brands and names are the property of their respective owners.
Ordering Information
ICS9250yF-22-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = S tandard Device
Example:
ICS XXXX y F - PPP - T
MIN MAX MIN MAX
A 2.413 2.794 .095 .110
A1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
56 18.288
18.542
.720 .730
JEDEC MO-118
DOC# 10-0034
6/1/00
REV B
N
D mm.
D (inch)
SEE VARIATIONS
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
Page 11
11
ICS92 50-22
Third party brands and names are the property of their respective owners.
Ordering Information
ICS9250yG-22-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = S tandard Device
Example:
ICS XXXX y G - PPP - T
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil)
(0.020 mil)
MIN MAX MIN MAX
A - 1.20 - .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e 0.50 BASIC 0.020 BASIC
L 0.45 0.75 .018 .30
N
α
0° 8° 0° 8°
aaa - 0.10 - .004
VARIATIONS
MIN MAX MIN MAX
56 13.90
14.10
.547 .555
MO-153 JEDEC
Doc.# 10-0039
7/6/00 Rev B
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
8.10 BASIC 0.319
N
D mm.
D (inch)
SEE VARIATIONS
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