Datasheet ICS9159CM-14 Datasheet (ICST)

Integrated

ICS9159C-14

Circuit
Systems, Inc.

Frequency Generator and Integrated Buffer f or PENTIUM™

General Description

The ICS9159C-14 generates all clocks required for high
speed RISC or CISC microprocessor systems such as 486,
Pentium, PowerPC, etc. Four different reference frequency
multiply-ing factors are externally selectable with smooth
frequency transitions. These multiplying factors can be
customized for specific applications. It has a TURBO pin
that can speed up the 60 and 66.6 MHz clocks by 2.5%.

High drive BCLK outputs provide typically greater than 1V/
ns slew rate into 30pF loads. PCLK outputs provide typically
better than 1V/ns slew rate into 20pF loads while maintaining
50±5% duty cycle.

Block Diagram

Features

• Generates up to four processor and six bus clocks,
plus disk, USB and reference clocks

• Synchronous clocks skew matched to 250ps window
on PCLKs and 500ps window on BCLKs

• TURBO input pin that can speed up the 60 and

66.6 MHz PCLKs by 2.5%.

• 2.5V or 3.3V output: PCLK (0:3)

• 3.0V - 5.5V supply range

• 28-pin SOIC package

Pin Cnfiguration

Functionality

TURBO FS1 FS0

1 0 0 14.318 50
1 0 1 14.318 66.8
1 1 0 14.318 60
1 1 1 14.318 55
0 0 0 14.318 83.3
0 0 1 14.318 68.4
0 1 0 14.318 61.6
0 1 1 14.318 75

ICS9159C-14RevC062397P

X1, REF

(MHz)

PCLK
(MHz)

28-Pin SOIC

PCLK(0:3) BCLK(0:5) USB DISK

VCO/2 PCLK/2 48 MHz 24 MHz

All frequencies in MHz, assuming 14.318 MHz input.

Pentium is a trademark of Intel Corporation.
PowerPC is a trademark of Motorola Corporation.

ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.

ICS9159C-14

Pin Descriptions

PIN

NUMBER

1, 26 V

PIN NAME TYPE DESCRIPTION

DD

PWR Power for logic and fixed frequency output buffers.

XTAL or external reference frequency input. This input includes

2X1IN

XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal,
nominally 14.31818 MHz.

3 X2 OUT XTAL output which includes XTAL load capacitance.

4, 11, 17, 23 V

5 TURBO IN

6, 7, 9, 10 PCLK(0:3) OUT

8V

13, 12 FS(0:1) IN
14, 20 V

15, 16, 18
19, 21, 22

24 DISK OUT

SS

PWR Ground

Speeds up the 60 and 66.6 MHz by 2.5% (see functionality table). It
has an internal pull-up resistor.

Processor clock outputs which are a multiple of the input reference
frequency as shown in the table above.

DD2

PWR

Power for PCLK output buffers only. This V
to 2.5V for PCLK (0:3) outputs.

DD

supply can be reduced

Frequency multiplier select pins. See table above. These inputs have
internal pull-up devices.

DD

PWR Power for BCLK output buffers.

BCLK(0:5) OUT Busclock outputs are fixed at one half the PCLK frequency.

The DISK controller clock is fixed at 24 MHz
(with 14.318 MHZ input)

25 USB OUT The USB clock is fixed at 48 MHz (with 14.318 MHz input).

28, 27 REF(0:1) OUT

REF is a buffered copy of the crystal oscillator or reference input
clock, nominally 14.31818 MHz.

2

ICS9159C-14

Absolute Maximum Ratings

Supply Voltage .......................................................................................................... 7.0 V

Logic Inputs ....................................................................... GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature ............................................................. 0°C to +70°C

Storage Temperature........................................................................... –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.

Electrical Characteristics at 3.3V

VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated

DC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I

Output Low Current
Output High Current

Output Low Current
Output High Current

Output Low Voltage
Output High Voltage

Output Low Voltage
Output High Voltage

1

1

1

1

1

1

1

1

V

V
V

V

Supply Current I

I
I

I
I

IL
IH

OL

OH

OL
OH

OL

OH

OL
OH

DD

IL
IH

VIN=0V -28.0 -10.5 - mA
VIN=V

DD

VOL=0.8V;
for PCLKs & BCLKs

VOH=2.0V;
for PCLKs & BCLKs

VOL=0.8V; for fixed CLKs 25.0 38.0 - mA
VOH=2.0V; for fixed CLKs - -47.0 -30.0 mA

IOL=15mA;
for PCLKs & BCLKs

IOH=-30mA;
for PCLKs & BCLKs

IOL=12.5mA; for fixed CLKs - 0.3 0.4 V
IOH=-20mA; for fixed CLKs 2.4 2.8 - V

@66.5 MHz; all outputs
unloaded

- - 0.2V

DD

0.7V

--V

-5.0 - 5.0 mA

30.0 47.0 - Ma

- -66.0 -42.0 mA

-0.30.4V

2.4 2.8 - V

-55110mA

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

DD

V

3

ICS9159C-14

Electrical Characteristics at 3.3V

VDD = 3.1 – 3.7 V, TA = 0 – 70°C

AC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Rise Time
Fall Time
Rise Time
Fall Time

Duty Cycle
Jitter, One Sigma

Jitter, Absolute
Jitter, One Sigma

Jitter, Absolute
Input Frequency

1

1

1

1

1

1

1

1

1

1

Logic Input Capacitance
Crystal Oscillator

Capacitance
Power-on Time

1

1

Frequency Settling Time
Clock Skew Window

Clock Skew Window
Clock Skew Window

1

1

1

r1

T

f1

T

r2

T

f2

T

D

j1s1

T

jab1

T

j1s2

T

jab2

T

Fi 12.0 14.318 16.0 MHz

1

1

IN

C

INX

C

on

t

s

t

sk1

T

sk2

T

sk3

T

20pF load, 0.8 to 2.0V
PCLK & BCLK

20pF load, 2.0 to 0.8V
PCLK & BCLK

20pF load, 20% to 80%
PCLK & BCLK

20pF load, 80% to 20%
PCLK & BCLK

t

20pF load @ V
PCLK & BCLK;

Load=20pF.
PCLK & BCLK;

Load=20pF.

OUT

=1.4V 48 50 58 %

- 0.9 1.5 ns

- 0.8 1.4 ns

- 1.5 2.5 ns

- 1.4 2.4 ns

- 50 150 ps

-250 - 250 ps

Fixed CLK; Load=20pF - 1 3 %
Fixed CLK; Load=20pF -5 2 5 %

Logic input pins - 5 - pF
X1, X2 pins - 18 - pF

From VDD=1.6V to 1st crossing of

66.5 MHz V

DD

supply ramp < 40ms

From 1st crossing of acquisition to
< 1% settling

-2.54.5ms

-2.04.0ms

PCLK to PCLK; Load=20pF; @1.4V - 150 250 ps
BCLK to BCLK; Load=20pF; @1.4V - 300 500 ps
PCLK to BCLK; Load=20pF; @1.4V 1 2.6 5 ns

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

4

ICS9159C-14

Electrical Characteristics at 5.0V

VDD = 4.5 – 5.5 V, TA = 0 – 70° C

DC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
Input High Voltage V
Input Low Current I
Input High Current I

Output Low Current
Output High Current

Output Low Current
Output High Current

Output Low Voltage
Output High Voltage

Output Low Voltage
Output High Voltage

1

1

1

1

1

1

1

1

Supply Current I

IL
IH

IL

IH

OL

I

OH

I

OL

I

OH

I

OL

V

OH

V

OL

V

OH

V

DD

VIN=0V -45 -15 - µ A
VIN=V

DD

VOL=0.8V;
for PCLKs & BCLKs

VOL=2.0V;
for PCLKs & BCLKs

VOL=0.8V; for fixed CLKs 30.0 50.0 - mA
VOL=2.0V; for fixed CLKs - -110.0 -65.0 mA

IOL=20mA;
for PCLKs & BCLKs

IOH=-70mA;
for PCLKs & BCLKs

IOL=15mA; for fixed CLKs - 0.2 0.4 V
IOH=-50mA; for fixed CLKs 2.4 4.7 - V

@66.5 MHz; all outputs
unloaded

--0.8V

2.4 - - V

-5.0 - 5.0 µ A

36.0 62.0 - mA

- -152 -90.0 mA

- 0.25 0.4 V

2.4 4.0 - V

- 80.0 160.0 mA

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

5

ICS9159C-14

Electrical Characteristics at 5.5V

VDD = 4.5 – 5.5 V, TA = 0 – 70° C

AC Characteristics

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Rise Time
Fall Time
Rise Time
Fall Time

Duty Cycle
Duty Cycle

Jitter, One Sigma
Jitter, Absolute

Jitter, One Sigma
Jitter, Absolute
Input Frequency

1

1

1

1

1

1

1

1

1

1

1

Logic Input Capacitance
Crystal

OscillatorCapacitance
Power-on Time

1

1

Frequency Settling Time
Clock Skew Window
Clock Skew Window
Clock Skew Window

1

1

1

r1

T

f1

T

r2

T

f2

T

t1

D

t2

D

j1s1

T

jab1

T

j1s2

T

jab2

T

i

F

1

1

IN

C

INX

C

on

t

s

t

sk1

T

sk2

T

sk3

T

20pF load, 0.8 to 2.0V
PCLK & BCLK

20pF load, 2.0 to 0.8V
PCLK & BCLK

20pF load, 20% to 80%
PCLK & BCLK

20pF load, 80% to 20%
PCLK & BCLK

20pF load @ V
20pF load @ V

OUT

=1.4V 50 57 60 %

OUT

=50% 45 50 55 %

PCLK & BCLK;
Load=20pF, Rs=33

Ω

PCLK & BCLK;
Load=20pF, Rs=33

Ω

REF CLKs; Load=20pF Rs=33
REF CLKs; Load=20pF Rs=33

Ω
Ω

- 0.55 0 .95 ns

- 0.52 0 .90 ns

- 1.2 2.1 ns

- 1.1 2.0 ns

- 50 150 ps

-250 - 250 ps

-13%

-5 2 5 %

12.0 14.318 16.0 MHz

Logic input pins - 5 - pF
X1, X2 pins - 18 - pF

From VDD=1.6V to 1st crossing
of 66.5 MHz V

DD

supply

- 2.5 4.5 ms

ramp < 40ms
From 1st crossing of acquisition

to < 1% settling
PCLK to PCLK;

Load=20pF; @1.4V
BCLK to BCLK;

Load=20pF; @1.4V
PCLK & BCLK;

Load=20pF; @1.4V

- 2.0 4.0 ms

- 150 250 ps

- 300 500 ps

12.65ns

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

6

ICS9159C-14

Ordering Information

ICS9159CM-14

Example:

ICS XXXX M-PPP

LEAD COUNT 28L

DIMENSIONL 0.704

SOIC Pac kage

Pattern Number(2 or 3 digit number for parts with ROM code patterns)

Package Type

M=SOIC

Device Type (consists of 3 or 4 digit numbers)
Prefix

ICS=Standard Device

ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all

7

device data to verify that any information being relied upon by the customer is current
and accurate.