6
ICS9158-03
VDD = +3.3V±10%, TA=0°C to 70°C unless otherwise stated
Electrical Characteristics at 3.3V
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
DC Characteristics
PARAM ETER SYMBO L TEST COND ITIONS MIN TY P MAX UNITS
Input Low Voltag e V
IL 0.2 VDD V
Input High Voltage V
IH 0.7 VDD V
Input Low Curren t I
IL VIN = 0V (P ull-up) -10 µA
Input High Current I
IH VIN=VDD -5 µA
Output Low Voltage V
OL IOL=10mA 0.1VDD V
Output High Voltage
1
VOH IOH=-5mA 0.85VDD V
Output Low Current
1
IOL VOL=0.2VDD 20 30 mA
Output High Current
1
IOH VOH=0.7VDD -15 -10 mA
Supply Current I
DD No load, 66 MHz 43 70 mA
Output Frequency Change
over Supply and
Temperature
1
FD
With respect to ty pical
frequency
0.002 0.01 %
Sho rt Cir cuit C urre nt
1
ISC Each output clock 25 56 mA
Pull- up R esisto r Value
1
RPU In put pin 9 00 kW
Input Cap acitance
1
Ci Except X1, X2 8 pF
Load Capacitance
1
CL Pins X1, X 2 20 pF
AC Characteristics
PARA METER
SYMBOL TEST CONDITIONS M IN TYP M AX UNITS
Output Rise time,
0.8 to 2.0V
1
tr 30pF load - 1 2.5 ns
Rise time, 20% to 80% V
DD
1
tr 30pF load - 2.5 4.0 ns
Output Fall time, 2.0 to 0.8V
1
tf 30pF load - 0.5 2.5 ns
Fall tim e, 80 % to 2 0% V
DD
1
tf 30pF load - 1.5 4.0 ns
Duty cycle
1
dt 30pF load 40/50 44/46 50/40 %
Jitter, one sigm a
1
tj1 s
As compared with clock
period
0.5 2.0 %
Jitter, absolute
1
tjab 25%
Jitter, absolute
1
tjab 25-66 MHz clocks 300 ps
Input Frequency f
i 14.318 MH z
Clock skew window between
CLK2A, CLK1(A-D)
CPU and CLK 12(A-C) outputs
1
Tsk 100 250 ps
Frequency Transition time
1
tft From 4 to 50 M Hz 13 20 m s