Datasheet HUF76413D3S Datasheet (Fairchild Semiconductor)

Data Sheet December 2001

20A, 60V, 0.056 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET

Packaging

JEDEC TO-251AA JEDEC TO-252AA

DRAIN

(FLANGE)

HUF76413D3

SOURCE

DRAIN

GATE

SOURCE

HUF76413D3S

DRAIN

(FLANGE)

Symbol

HUF76413D3, HUF76413D3S

Features

• Ultra Low On-Resistance

-r

• Simulation Models

- Temperature Compensated PSPICE® and SABER™ Electrical Models

- Spice and SABER Thermal Impedance Models

- www.fairchildsemi.com

• Peak Cu rrent vs Pulse Width Curve

• UIS Rating Curve

• Switching Time vs R

DS(ON) DS(ON)

= 0.049Ω, V = 0.056Ω, V

GS

= 10V

GS

= 5V

GS

Curves

D

G

S

Absolute Maximum Ratings

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain to Gate Voltage (R

Gate to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain Current

Continuous (T

Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 17, 18

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . T

NOTES:

= 25oC to 150oC.

1. T

J

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause per man ent dama ge to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

C

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . V

GS

TC = 25oC, Unless Otherwise Specified

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76413D3 TO-251AA 76413D HUF76413D3S TO-252AA 76413D

NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76413D3ST.

HUF76413D3, HUF76413D3S UNITS

DSS

DGR

GS

D D D D

DM

D

, T

J

STG

L

pkg

60 V 60 V

±16 V

20 20 15 15

Figure 4

60

0.4

-55 to 175

300 260

W/oC

A A A A

W

o

C

o

C

o

C

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

For severe environments, see our Automotive HUFA series.

HUF76413D3, HUF76413D3S

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R Thermal Resistance Junction to

Ambient SWITCHING SPECIFICATIONS (V

= 4.5V)

GS

Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t SWITCHING SPECIFICATIONS (V

GS

= 10V) Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q Gate Charge at 5V Q Threshold Gate Charge Q Gate to Source Gate Charge Q Gate to Drain “Miller” Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C

DSSID

I

D

DSS

VDS = 55V, VGS = 0V - - 1 µA V

GSS

GS(TH)VGS

DS(ON)ID

θJC

R

θJA

ON

d(ON)

d(OFF)

OFF

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

ISS OSS RSS

VGS = ±16V - - ±100 nA

I

D

I

D

TO-251 and TO-252 - - 2.5

VDD = 30V, ID = 15A V (Figures 15, 21, 22)

r

f

VDD = 30V, ID = 20A V R

r

(Figures 16, 21, 22)

f

VGS = 0V to 5V - 9 11 nC VGS = 0V to 1V - 0.6 0.7 nC

gs

gd

VDS = 25V, VGS = 0V, f = 1MHz (Figure 13)

= 250µA, VGS = 0V (Figure 12) 60 - - V = 250µA, VGS = 0V , TC = -40oC (Figure 12) 55 - - V

= 50V, VGS = 0V, TC = 150oC - - 250 µA

DS

= VDS, ID = 250µA (Figure 11) 1 - 3 V = 20A, VGS = 10V (Figures 9, 10) - 0.041 0.049 Ω = 15A, VGS = 5V (Figure 9) - 0.048 0.056 Ω = 15A, VGS = 4.5V (Figure 9) - 0.051 0.061 Ω

o

- - 100

o

- - 273 ns

= 4.5V, RGS = 16Ω

GS

-10-ns

- 172 - ns

-21-ns

-55-ns

- - 114 ns

- - 63 ns

= 10V,

GS GS

= 18Ω

-6-ns

-36-ns

-48-ns

-42-ns

- - 135 ns

= 0V to 10V VDD = 30V,

I

= 15A,

D

= 1.0mA

I

g(REF)

-1720nC

(Figures 14, 19, 20)

-2-nC

-5-nC

- 645 - pF

- 190 - pF

-40-pF

C/W C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

Reverse Recovery Time t Reverse Recovered Charge Q

SD

rr

RR

ISD = 15A - - 1.25 V

= 8A - - 1.0 V

I

SD

ISD = 15A, dISD/dt = 100A/µs--72ns ISD = 15A, dISD/dt = 100A/µs - - 185 nC

Typical Performance Curves

5

HUF76413D3, HUF76413D3S

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 17

125

150

TC, CASE TEMPERA TURE (oC)

FIGURE 1. NORMALIZED POWER DISSIP ATION vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

25

20

V

= 10V

GS

15

V

= 4.5V

10

, DRAIN CURRENT (A)

D

I

5

GS

0

25 50 75 100 125 150 17

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

NOTES: DUTY FACTOR: D = t PEAK TJ = PDM x Z

-2

10

-1

10

θJC

10

1/t2

x R

0

θJC

+ T

1

t

2

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

500

100

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

10

-5

10

VGS = 10V

VGS = 5V

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC

FOR TEMPERATURES ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

10

0

C

150

10

FIGURE 4. PEAK CURRENT CAPABILITY

1

0 0

5

4

0

HUF76413D3, HUF76413D3S

Typical Performance Curves

200

100

10

OPERATION IN THIS

, DRAIN CURRENT (A)

D

I

AREA MAY BE LIMITED BY r

1

110100

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

(Continued)

SINGLE PULSE TJ = MAX RATED

T

C

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

40

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

V

= 15V

DD

30

= 25oC

100µs

1ms

10ms

100

STARTING TJ = 25oC

10

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

20

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

1

0.001 0.01 0.1 1 1 tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

- VDD) +1]

NOTE: Refer to Fairchild Application Notes AN9321 and AN 9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

40

30

VGS = 10V VGS = 5V

VGS = 4V

20

DRAIN CURRENT (A)

10

D,

I

TJ = 25oC

0

1.5 2.0 2.5 3.0 3.5 4.0 4. VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = -55oC

20

, DRAIN CURRENT (A)

10

D

I

PULSE DURATION = 80µs

0

0123

DUTY CYCLE = 0.5% MAX

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SA TURATION CHARACTERISTICS

90

ID = 20A

75

60

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

DS(ON)

r

ID = 5A

45

30

24681

ID = 15A

, GATE TO SOURCE VOLTAGE (V)

V

GS

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

T

= 25oC

C

2.5

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

ON RESIST ANCE

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 20 TJ, JUNCTION TEMPERATURE (oC)

VGS = 3.5V

VGS = 3V

T

= 25oC

C

VGS = 10V, ID = 20A

FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

0

0 0

0

HUF76413D3, HUF76413D3S

Typical Performance Curves

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160 20 TJ, JUNCTION TEMPERATURE (oC)

(Continued)

VGS = VDS, ID = 250µA

FIGURE 11. NORMALIZED GA TE THRESHOLD V OLT AGE vs

JUNCTION TEMPERATURE

2000

= C

1000

C

ISS

OSS

≅ C

GS

DS

+ C

GD

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 20 , JUNCTION TEMPERATURE (oC)

T

J

FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

VDD = 30V

8

6

100

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

10

0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)

C

RSS

= C

GD

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

250

VGS = 4.5V, VDD = 30V, ID = 15A

200

t

r

150

100

t

SWITCHING TIME (ns)

50

0

0 102030405

RGS, GATE TO SOURCE RESISTANCE (Ω)

f

t

d(OFF)

t

d(ON)

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

6

0 5 10 15 2

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 20A I

= 15A

D

I

= 5A

D

NOTE: Refer to Fairchild Application Notes AN7254 and AN 7260.

FIGURE 14. GATE CHARGE W AVEFORMS FOR CONSTANT

GATE CURRENT

125

VGS = 10V, VDD = 30V, ID = 20A

100

75

50

SWITCHING TIME (ns)

25

0

0 102030405

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(OFF)

t

f

t

r

t

d(ON)

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

V

I

HUF76413D3, HUF76413D3S

Test Circuits and Waveforms

V

DS

BV

DSS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

0

g(REF)

0

V

= 1V

GS

Q

g(TH)

Q

gs

t

P

I

AS

t

AV

Q

g(TOT)

V

DS

Q

g(5)

VGS = 5V

Q

gd

V

DS

V

DD

V

= 10

GS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

DUT

R

GS

V

GS

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM

HUF76413D3, HUF76413D3S

PSPICE Electrical Model

.SUBCKT HUF76413D3 2 1 3 ; rev 31 August 1999

CA 12 8 8.5e-10 CB 15 14 8.5e-10 CIN 6 8 6.05e-10

DBODY 7 5 DBODYMOD DBREAK 5 11 D B REAK MOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 65.6 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1

IT 8 17 1 LDRAIN 2 5 1e-9

LGATE 1 9 5.1e-9 LSOURCE 3 7 4.8e-9

GATE

1

MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.2e-2 RGATE 9 20 2.4 RLDRAIN 2 5 10 RLGATE 1 9 51 RLSOURCE 3 7 48 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.03e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTE MPMOD 1

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

6 8

13

10

RSLC2

6

14 13

+

6 8

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CB

CIN

-

+

5 8

-

5

RSLC1

51

+

5

51

-

50 RDRAIN

21

MSTRO

14

ESLC

16

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

11

+

17 18

DBODY

DRAIN

2

-

LSOURCE

7

RLSOURCE

RVTEMP 19

SOURCE

3

-

VBAT

+

22

ESLC 51 50 VALUE={(V (5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3.9))} .MODEL DBODYMOD D (IS = 5.4e-13 RS = 1.1e-2 TRS1 = 1.5e-3 TRS2 = 5e-6 CJO = 8.2e-10 TT = 3.8e-8 M = 0.52)

.MODEL DBREAKMOD D (RS = 3.5e- 1TRS1 = 1e- 3TRS2 = -6.5e-6) .MODEL DPLCAPMOD D (CJO = 5.5e-1 0IS = 1e-3 0N = 10 M = 0.8) .MODEL MMEDMO D N MOS (VTO = 1.95 K P = 2.6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.4) .MODEL MSTROMOD NMOS (VTO = 2.32 KP = 28 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.65 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 24 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.2e- 3TC2 = -1e-6) .MODEL RDRAINMOD RES (TC1 = 7.8e-3 TC2 = 1.5e-5) .MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (T C1 = -2e-3 TC2 = -4.3 e-6) .MODEL RVTEMPMOD RES (TC1 = -1.7e- 3TC2 = 1e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -2.5) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -5.5) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0) .MODEL S2BMOD VSWITCH (RON = 1e -5 ROFF = 0.1 VON = 0 VOFF= -0.5)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Pow er Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

HUF76413D3, HUF76413D3S

SABER Electrical Model

REV 31 August 1999 template huf76413d3 n2,n1,n3

electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 5.4e-13, cjo = 8.2e-10, tt = 3.8e-8, m = 0.52) d..model dbreakmod = () d..model dplcapmod = (cjo = 5.5e-10, is = 1e-30, n=10, m = 0.8 ) m..model mmedmod = (type=_n, vto = 1.95, kp = 2.6, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.32, kp = 28, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.65, kp = 0.02, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -2.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -5.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5)

c.ca n12 n8 = 8.5e-10 c.cb n15 n14 = 8.5e-10 c.cin n6 n8 = 6.05e-10

d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9

GATE

l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 4.8e-9

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n1 7 n1 8 = 1, tc1 = 1.2e-3, tc2 = -1e-6 res.rdbody n71 n5 = 1.1e-2, tc1 = 1.5e-3, tc2 = 5e-6 res.rdbreak n72 n5 = 3.5e-1, tc1 = 1e-3, tc2 = -6.5e-6 res.rdrain n50 n16 = 2.2e-2, tc1 = 7.8e-3, tc2 = 1.5e-5 res.rgate n9 n20 = 2.4 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51 res.rlsource n3 n7 = 48 res.rslc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2e-6 res.rslc2 n5 n50 = 1e3 res.rsour ce n8 n7 = 1.03e-2, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1e-6 res.rvthres n22 n 8 = 1, tc1 = -2e-3, tc2 = -4.3e-6

LGATE

1

RLGATE

RGATE

9

CA

EVTEMP

+

20

12

10

RSLC2

-

6

ESG

8

+

6

-

18 22

S1A

S1B

S2A

14

13

8

S2B

13

+

6

EGS EDS

8

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

RSLC1

51

50 RDRAIN

21

MSTRO

14

5 8

ISCL

16

8

MMED

RDBREAK

72

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

-

17 18

71

7

RLSOURCE

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

RDBODY

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

spe.ebreak n11 n7 n17 n18 = 65.6 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc =1 equations {

i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/50))** 3.9)) } }

SPICE Thermal Model

REV 31 August 99

T76413d3

CTHERM1 th 6 7.5e-4 CTHERM2 6 5 2.8e-3 CTHERM3 5 4 3.0e-3 CTHERM4 4 3 3.4e-3 CTHERM5 3 2 5.3e-3 CTHERM6 2 tl 9.5e-2

RTHERM1 th 6 6.5e-3 RTHERM2 6 5 2.1e-2 RTHERM3 5 4 1.5e-1 RTHERM4 4 3 4.9e-1 RTHERM5 3 2 8.3e-1 RTHERM6 2 tl 5.0e-1

SABER Thermal Model

SABER thermal model t76413d3 template thermal_model th tl thermal_c th, tl

{ ctherm.ctherm1 th 6 = 7.5e-4 ctherm.ctherm2 6 5 = 2.8e-3 ctherm.ctherm3 5 4 = 3.0e-3 ctherm.ctherm4 4 3 = 3.4e-3 ctherm.ctherm5 3 2 = 5.3e-3 ctherm.ctherm6 2 tl = 9.5e-2

rtherm.rtherm1 th 6 = 6.5e-3 rtherm.rtherm2 6 5 = 2.1e-2 rtherm.rtherm3 5 4 = 1.5e-1 rtherm.rtherm4 4 3 = 4.9e-1 rtherm.rtherm5 3 2 = 8.3e-1 rtherm.rtherm6 2 tl = 5.0e-1 }

HUF76413D3, HUF76413D3S

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

tl

CASE

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Rev. H4