Datasheet HUF75617D3, HUF75617D3S Datasheet (Fairchild Semiconductor)

Data Sheet December 2001

16A, 100V, 0.090 Ohm, N-Channel, UltraFET® Power MOSFETs

Packaging

JEDEC TO-251AA JEDEC TO-252AA

HUF75617D3, HUF75617D3S

Features

SOURCE

DRAIN

GATE

DRAIN

(FLANGE)

• Ultra Low On-Resistance

-r

DS(ON)

= 0.090Ω, V

GS

= 10V

• Simulation Models

DRAIN

(FLANGE)

HUF75617D3

GATE

SOURCE

HUF75617D3S

- Temperature Compensated PSPICE® and SABER™ Electrical Models

- Spice and SABER Thermal Impedance Models

- www.fairchildsemi.com

• Peak Cu rrent vs Pulse Width Curve

• UIS Rating Curve

Symbol

D

G

S

Absolute Maximum Ratings

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (T

Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

NOTE: T

CAUTION: Stresses above those listed in “ Absolute M aximum Ratings” may cause perm anent damage to th e device. This is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

J

C

= 25oC to 150oC.

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

TC = 25oC, Unless Otherwise Specified

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75617D3 TO-251AA 75617D HUF75617D3S TO-252AA 75617D

NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF75617D3ST.

HUF75617D3,

HUF75617D3S UNITS

DSS

DGR

GS

D D

DM

D

, T

J

STG

L

pkg

100 V 100 V ±20 V

16 11

Figure 4

64

0.43

-55 to 175

300 260

A A

W

W/oC

o

C

o

C

o

C

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

For severe environments, see our Automotive HUFA series.

HUF75617D3

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R Thermal Resistance Junction to

Ambient SWITCHING SPECIFICATIONS (V

GS

= 10V) Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q Gate Charge at 10V Q Threshold Gate Charge Q Gate to Source Gate Charge Q Gate to Drain "Miller" Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C

DSSID

DSS

VDS = 95V, VGS = 0V - - 1 µA V

GSS

GS(TH)VGS

DS(ON)ID

θJC

R

θJA

ON

VGS = ±20V - - ±100 nA

TO-251, TO-252 - - 2.34oC/W

VDD = 50V, ID = 16A V

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(10)

g(TH)

ISS

OSS

RSS

R (Figures 18, 19)

r

f

VGS = 0V to 10V - 18 22 nC VGS = 0V to 2V - 1.3 1.6 nC

gs

gd

VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)

= 250µA, VGS = 0V (Figure 11) 100 - - V

= 90V, VGS = 0V, TC = 150oC - - 250 µA

DS

= VDS, ID = 250µA (Figure 10) 2 - 4 V

= 16A, VGS = 10V (Figure 9) - 0.080 0.090 ¾

- - 100

o

- - 60 ns

= 10V,

GS GS

= 12Ω

-6-ns

-35-ns

-44-ns

-28-ns

- - 108 ns

= 0V to 20V VDD = 50V,

= 16A,

I

D

I

= 1.0mA

g(REF)

-3139nC

(Figures 13, 16, 17)

-2.7-nC

-6.4-nC

- 570 - pF

- 125 - pF

-20-pF

C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TE ST CONDIT IONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

Reverse Recovery Time t Reverse Recovered Charge Q

SD

rr

RR

ISD = 16A - - 1.25 V

= 7A - - 1.00 V

I

SD

ISD = 16A, dISD/dt = 100A/µs--80ns ISD = 16A, dISD/dt = 100A/µs - - 170 nC

Typical Performance Curves

5

1

HUF75617D3

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIE R

0

0 25 50 75 100 17

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATI ON vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

-3

10

t, RECTANGULAR PULSE DURATION (s)

18

15

V

= 10V

12

GS

9

6

, DRAIN CURRENT (A)

D

I

3

0

25

50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

t

NOTES:

10

DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z

-2

-1

10

2

x R

θ

JC

10

+ T

θ

JC

0

175

2

C

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

300 200

100

VGS = 10V

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

10

-5

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC FOR TEMPERATURES ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

0

10

C

150

10

FIGURE 4. PEAK CURRENT CAPABILITY

0

HUF75617D3

Typical Performance Curves

200 100

10

1

, DRAIN CURRENT (A)

D

I

0.1

OPERATION IN THIS AREA MAY BE LIMITED BY r

1

V

DS(ON)

10

, DRAIN TO SOURCE VOLTAGE (V)

DS

(Continued)

SINGLE PULSE TJ = MAX RATED

T

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

30

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 15V

V

25

DD

20

= 25oC

C

100

100µs

1ms

10ms

100

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0 t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

10

, AVALANCHE CURRENT (A)

AS

I

20

STARTING TJ = 150oC

1

0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

1

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

30

25

20

VGS = 10V

VGS = 6V

VGS = 5V

15

10

DRAIN CURRENT (A )

D,

I

TJ = 175oC

TJ = -55oC

5

15

10

, DRAIN CURRENT (A)

D

I

5

TJ = 25oC

0

234 6

5

VGS, GATE TO SOURCE VOLTAGE (V)

0

01234

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SA TURATION CHARACTERIS TICS

3.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 200 TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 16A

160

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 200 TJ, JUNCTION TEMPERATURE (oC)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 25oC

T

C

VGS = VDS, ID = 250µA

160

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 10. NORMALIZED GA TE THRESHOLD VOL TAGE vs

JUNCTION TEMPERATURE

HUF75617D3

Typical Performance Curves

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 200 , JUNCTION TEMPERATURE (oC)

T

J

(Continued)

160

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

VDD = 50V

8

2000 1000

C

+ C

≅

OSS

DS

GD

100

C, CAPACITANCE (pF)

10

0.1 1.0 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)

C

RSS

= C

GD

V

GS

C

ISS

= 0V, f = 1MHz

+ C

= C

GS

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

015

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Q

g

10 205

, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 16A

= 10A

I

D

I

= 4A

D

V

I

HUF75617D3

Test Circuits and Wavefo rms

V

DS

BV

DSS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

0

g(REF)

0

V

GS

= 2V

Q

g(TH)

Q

gs

t

P

I

AS

t

AV

Q

g(TOT)

V

DS

Q

g(10)

VGS = 10V

Q

gd

V

DS

V

DD

V

= 20

GS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

DUT

R

GS

V

GS

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

PSPICE Electrical Model

.SUBCKT HUF75617 d3 2 1 3 ; rev 24May 2000

CA 12 8 9.9e-10 CB 15 14 1.0e-9 CIN 6 8 5.4e-10

HUF75617D3

DBODY 7 5 DBODYMOD DBREAK 5 11 D B REAK MOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 117.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1

IT 8 17 1 LDRAIN 2 5 1.0e-9

LGATE 1 9 5.24e-9 LSOURCE 3 7 4.25e-9

GATE

1

MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.9e-2 RGATE 9 20 2.45 RLDRAIN 2 5 10 RLGATE 1 9 52.4 RLSOURCE 3 7 42.5 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.2e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTE MPMOD 1

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP

+

18 22

20

S1A

12

13

8

S1B

EGS EDS

7

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

6

8

EVTHRES

+

6

-

S2A

14 13

S2B

13

+

6 8

-

5

RSLC1

51

+

5

ESLC

51

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17 18

-

ESLC 51 50 VALUE={(V (5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*32),3.5))} .MODEL DBODYMOD D (IS = 6.0e-13 RS = 11.0e-3 XTI = 4.5 TRS1 = 1.1e-3 TRS2 = 7.1e-6 CJO = 6.5e-10 TT = 4.1e-8 M = 0.54)

.MODEL DBREAKMOD D (RS = 5.6e- 1TRS1 = 8.0e- 4TRS2 = 3.0e-6) .MODEL DPLCAPMOD D (CJO = 7.0e-1 0IS = 1e-3 0M = 0.89 N = 10) .MODEL MMEDMOD NMOS (VTO = 3.10 KP = 3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.45) .MODEL MSTROMOD NMOS (VTO = 3.64 KP = 42 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKM OD NMOS (VTO = 2.68 KP = 0.02 IS = 1 e -30 N = 10 TOX = 1 L = 1u W = 1u RG = 24.5) .MODEL RBR EAKMOD RES (TC1 = 1.05e- 3TC2 = -5.0e-7) .MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 3.00e-5) .MODEL RSLCMOD RES (TC1 = 3.2e-3 TC2 = 1.0e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.2e-3 TC2 = -9.0e-6) .MODEL RVTEMPMOD RES (TC1 = -2.4e- 3TC2 = -1.8e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.9 VOFF= -3.1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.1 VOFF= -5.9) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.6 VOFF= 0.5) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.6)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Gl obal Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

HUF75617D3

SABER Electrical Model

REV 24 May 2000 template huf75617d3 n2,n1,n3

electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 6.0e-13, rs = 11.0e-3, xti = 4.5, trs1 = 1.1e-3, trs2 = 7.1e-6, cjo = 6.5e-10, tt = 4.1e-8, m = 0.54) dp..model dbreakmod = (rs = 5.6e-1, trs1 = 8.0e-4, trs2 = 3.0e-6) dp..model dplcapmod = (c jo = 7.0e-10, isl = 10e-30, m = 0.89, nl = 10) m..model mmedmod = (type=_n, vto = 3.10, kp = 3, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.64, kp = 42, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.68, kp = 0.02, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.9, voff = -3.1) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.1, voff = -5.9) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.6)

c.ca n12 n8 = 9.9e-10 c.cb n15 n14 = 1.0e-9 c.cin n6 n8 = 5.4e-10

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9

l.lgate n1 n9 = 5.24e-9 l.lsource n3 n7 = 4.25e-9

GATE

LGATE

1

RLGATE

RGATE

9

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5.0e-7 res.rdrain n50 n16 = 3.9e-2, tc1 = 1.20e-2, tc2 = 3.00e-5

12

res.rgate n9 n20 = 2.45 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 52.4 res.rlsource n3 n7 = 42.5

CA

res.rslc1 n5 n51 = 1e-6, tc1 = 3.2e-3, tc2 = 1.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.2e-2, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 1.8e-6 res.rvthres n22 n 8 = 1, tc1 = -2.2e-3, tc2 = -9.0 e-6

spe.ebreak n11 n7 n17 n18 = 117.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc =1

ESG

EVTEMP +

18 22

20

S1A

13

S1B

EGS EDS

DPLCAP

10

RSLC2

6

8

EVTHRES

+

6

-

S2A

14 13

8

S2B

13

+

6 8

-

5

RSLC1

51

ISCL

MMED

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

50 RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

+

-

17 18

7

RLSOURCE

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/32))* * 3. 5)) } }

SPICE Thermal Model

REV 24 May 2000

HUF75617D

CTHERM1 th 6 1.00e-3 CTHERM2 6 5 4.00e-3 CTHERM3 5 4 4.00e-3 CTHERM4 4 3 3.60e-3 CTHERM5 3 2 7.00e-3 CTHERM6 2 tl 5.00e-2

RTHERM1 th 6 1.59e-2 RTHERM2 6 5 3.96e-2 RTHERM3 5 4 1.12e-1 RTHERM4 4 3 4.27e-1 RTHERM5 3 2 6.45e-1 RTHERM6 2 tl 7.00e-1

SABER Thermal Model

SABER thermal model HUF75617D template thermal_model th tl

thermal_c th, tl { ctherm.ctherm1 th 6 = 1.00e-3 ctherm.ctherm2 6 5 = 4.00e-3 ctherm.ctherm3 5 4 = 4.00e-3 ctherm.ctherm4 4 3 = 3.60e-3 ctherm.ctherm5 3 2 = 7.00e-3 ctherm.ctherm6 2 tl = 5.00e-2

rtherm.rtherm1 th 6 = 1.59e-2 rtherm.rtherm2 6 5 = 3.96e-2 rtherm.rtherm3 5 4 = 1.12e-1 rtherm.rtherm4 4 3 = 4.27e-1 rtherm.rtherm5 3 2 = 6.45e-1 rtherm.rtherm6 2 tl = 7.00e-1 }

HUF75617D3

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

RTHERM6

tl

CASE

CTHERM6

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna

TM

FACT™ FACT Quiet Series™

STAR*POWER is used under license

FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™



OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench



QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER

SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™



UltraFET

VCX™



DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or In Design

First Production

Full Production

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. H4