Datasheet HUF75329D3, HUF75329D3S Datasheet (Fairchild Semiconductor)

HUF75329D3, HUF75329D3S

Data Sheet December 2001

20A, 55V, 0.026 Ohm, N-Channel UltraFE T
Power MOSFETs

These N-Channel pow er MOSFETs
are manufactured using the
innovat ive Ul traFET® pr ocess . This

advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outsta nding performance. This device is capable
of withstanding hi gh energy in the ava lan che mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low­voltage bus switches, and pow er management in portable
and battery-operated products.

Formerly developmental type TA75329.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75329D3 TO-251AA 75329D
HUF75329D3S TO-252AA 75329D

NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF75329D3ST.

Features

• 20A, 55V

• Simulation Models

- T emp eratu re Com pensat ed PSPI CE® and SABER™
Models

- SPICE and SABER Thermal Impedance Models
Available on the WEB at: www.fairchildsemi.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

JEDEC TO-251AA JEDEC TO-252AA

DRAIN

(FLANGE)

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

SOURCE

DRAIN

GATE

For severe environments, see our Automotive HUFA series.

GATE

SOURCE

DRAIN

(FLANGE)

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

HUF75329D3, HUF75329D3S

Absolute Maximum Ratings

TC = 25oC, Unless Otherwise Specified

UNITS

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

55 V
55 V

±20 V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T

, T

J

STG

D

DM

AS

D

20

Figure 4

Figure 6

128

0.86

-55 to 175

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A

W

W/oC

o

C

o

C

o

C

NOTE:

1. T

= 25oC to 150oC.

J

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

DSSID

DSS

GSS

= 250µA, VGS = 0V (Figure 11) 55 - - V
VDS = 50V, VGS = 0V - - 1 µA
V

= 45V, VGS = 0V, TC = 150oC--250µA

DS

VGS = ±20V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

GS(TH)VGS

DS(ON)ID

= VDS, ID = 250µA (Figure 10) 2 - 4 V

= 20A, VGS = 10V (Figure 9) - 0.022 0.026 Ω

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V

GS

= 10V)
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

θJC
θJA

ON

r

f

OFF

(Figure 3) - - 1.17
TO-251, TO-252 - - 100

VDD = 30V, ID ≅ 20A,
R

= 1.5Ω, VGS = 10V,

L

= 9.1Ω

R

GS

- - 60 ns

-7-ns

-30- ns

-10- ns

-33- ns

- - 65 ns

o

C/W

o

C/W

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at 10V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Reverse Transfer Capacitance Q

g(TOT)VGS

g(10)

g(TH)

gs

gd

= 0V to 20V VDD = 30V,

≅ 20A,

I

VGS = 0V to 10V - 32 40 nC
VGS = 0V to 2V - 2.0 2.5 nC

D

R

= 1.5Ω

L

I

g(REF)

= 1.0mA

(Figure 13)

-5065nC

-5-nC

-13-nC

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

5

5

HUF75329D3, HUF75329D3S

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TC, CASE TEMPERATURE (oC)

125 17

ISS

OSS

RSS

SD

rr

RR

VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)

- 1060 - pF

- 405 - pF

-95-pF

ISD = 20A - - 1.25 V
ISD = 20A, dISD/dt = 100A/µs--68ns
ISD = 20A, dISD/dt = 100A/µs - - 120 nC

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

25

50 75 100 125 150 17

TC, CASE TEMPERA TURE (oC)

FIGURE 1. NORMALIZED POWER DISSIP ATION vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-2

10

-1

10

1/t2

x R

θJC

0

10

t

θJC

2

+ T

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

0
0

5

5

HUF75329D3, HUF75329D3S

Typical Performance Curves

1000

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

500

100

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

10

-5

10

-4

10

(Continued)

-3

10

t, PULSE WIDTH (s)

-2

10

FIGURE 4. PEAK CURRENT CAPABILITY

200

TJ = MAX RATED
T

= 25oC

C

100

TC = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

-1

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

o

C DERATE PEAK

25

0

10

- VDD)

DSS

DSS

175 - T

150

- VDD) +1]

C

1

10

100µs

10

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

V

DSS(MAX)

1

120

DS(ON)

= 55V

10 100

1ms

10ms

, AVALANCHE CURRENT (A)

AS

I

VDS, DRAIN TO SOURCE VOLTAGE (V)

STARTING TJ = 150oC

1

0.01

0.1 10
tAV, TIME IN AVALANCHE (ms)

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

100

80

60

40

, DRAIN CURRENT (A)

D

I

20

0

023

VDS, DRAIN TO SOURCE VOLTAGE (V)

V

= 20V

GS

VGS = 10V
VGS = 8V
VGS = 7V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 25oC

T

C

41

VGS = 6V

VGS = 5V

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

80

60

40

, DRAIN CURRENT (A)

D

I

20

0

0 3.0 4.5 6.0 7.

1.5
VGS, GATE TO SOUR CE VOLTAGE (V)

STARTING TJ = 25oC

110

-55oC

175oC

V

25oC

DD

= 15V

FIGURE 7. SATURATION CHARACTERIS TICS FIGURE 8. TRANSFER CHARACTERISTICS

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

5

HUF75329D3, HUF75329D3S

Typical Performance Curves

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 10V, ID = 20A

V

GS

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-40 0 40 80 120 160 200

-80
TJ, JUNCTION TEMPERATURE (oC)

(Continued)

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.2
ID = 250µA

1.1

1.2

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-40 0 40 80 120 160 200

-80
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

FIGURE 10. NORMALIZED GA TE T HRESHOLD V OLT A GE vs

JUNCTION TEMPERATURE

1500

1200

C

ISS

V

= 0V, f = 1MHz

GS

= CGS + C

C

ISS

C

= C

RSS

C

≈ CDS + C

OSS

GD

GD

GD

1.0

0.9

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.8

-40 0 40 80 120 160 200-80
T

, JUNCTION TEMPERATURE (oC)

J

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0

510

Q

900

600

C, CAPACITANCE (pF)

300

0

0 1020304050

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

WAVEFORMS IN
DESCENDING ORDER:

ID = 20A

= 12.5A

I

D

= 5A

VDD = 30V

15 20 3

, GATE CHARGE (nC)

g

I

D

25 30

C

OSS

C

RSS

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

60

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

V

I

HUF75329D3, HUF75329D3S

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

I

G(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

0

g(REF)

0

V

GS

= 2V

Q

g(TH)

Q

gs

t

P

I

AS

t

AV

Q

g(TOT)

V

DS

Q

g(10)

VGS = 10V

Q

gd

V

DS

V

DD

V

= 20

GS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

DUT

R

GS

V

GS

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

t

10%

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

PSPICE Electrical Model

.SUBCKT HUF75329D 2 1 3 ; rev 6/19/97

CA 12 8 1.72e-9
CB 15 14 1.52e-9
CIN 6 8 9.61e-10

DBODY 7 5 DBODYMOD
DBREAK 5 11 D B REAK MOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 58.13
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

GATE

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 2.86e-9
LSOURCE 3 7 2.69e-9

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 1.52
RLDRAIN 2 5 10
RLGATE 1 9 26.9
RLSOURCE 3 7 28.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 13.85e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTE MPMOD 1

LGATE

1

RLGATE

RGATE

9

CA

HUF75329D3, HUF75329D3S

-

ESG

+

EVTEMP
+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

S2A

S2B

5

RSLC1

51

+

5

ESLC

51

-

50

RDRAIN

16

21

-

19

8

MMED

MSTRO

CIN

15

CB

8

14

+

5
8

-

8

DBREAK

11

+

17

EBREAK

18

-

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*135),3.5))}
.MODEL DBODYMOD D (IS = 7. 50e-13 RS = 5.05e-3 TRS1 = 2.21e-3 TRS2 = 1.02e-6 CJO = 1.51e-9 TT = 4.05e-8 M = 0.5)

.MODEL DBREAKMOD D (RS = 2.14e- 1TRS1 = 9.62e- 4TRS2 = 1.23e-6)
.MODEL DPLCAPMOD D (CJO = 13.5e-1 0IS = 1e-3 0N = 10 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 2.50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.52)
.MODEL MSTROMOD NMOS (VTO = 3.80 KP = 70.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKM OD NMOS (VTO = 2 . 91 K P = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = 1.94e-7)
.MODEL RDRAINMOD RES (TC1 = 8.04e-2 TC2 = 1.37e-4)
.MODEL RSLCMOD RES (TC1 = 4.83e-3 TC2 = 1.16e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -3.43e-3 TC2 = -1.63e-5)
.MODEL RVTEMPMOD RES (TC1 = -1.35e- 3TC2 = 1.16e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.90 VOFF= -4.90)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.90 VOFF= -7.90)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= 2.50)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.50 VOFF= -0.50)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Gl obal
Temperature Options; IEEE Pow er Electronics Specialist Conference Records, 1991, w ritten by William J. Hepp and C. Frank Wheatley.

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

E

HUF75329D3, HUF75329D3S

SABER Electrical Model

REV June 1997
template huf75329d n2, n1, n3

electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 7.50e-13, cjo = 1.51e-9, tt = 4.05e-8, m = 0.5)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 13. 5e-10, is = 1e-30, n = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 3.25, kp = 2.50, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.80, kp = 70, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.91, kp = 0.06, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.90, voff = -4.90)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4.90, voff = -7.90)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.50, voff = 2.50)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.50, voff = -0.50)

c.ca n12 n8 = 1.72e-9
c.cb n15 n14 = 1.52e-9
c.cin n6 n8 = 9.61e-10

d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1

GATE

LGATE

1

RLGATE

l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.86e-9
l.lsource n3 n7 = 2.69e-9
k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085

m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u

res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 1.94e-7
res.rdbody n71 n5 = 5.05e-3, tc1 = 2.21e-3, tc2 = 1.02e-6
res.rdbreak n72 n5 = 2.14e-1, tc1 = 9.62e-4, tc2 = 1.23e-6
res.rdrain n50 n16 = 1e-3, tc1 = 8.04e-2, tc2 = 1.37e-4
res.rgate n9 n20 = 1.52
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26.9
res.rlsource n3 n7 = 28.6
res.rslc1 n5 n51 = 1e-6, tc1 = 4.83e-3, tc2 = 1.16e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 13.85e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.35e-3, tc2 = 1.16e-6
res.rvthres n22 n 8 = 1, tc1 = -3.43e-3, tc2 = -1.63e-5

spe.ebreak n11 n7 n17 n18 = 58.13
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

RGATE

9

CA

ESG

EVTEMP
+

20

S1A

12

S1B

DPLCAP

10

RSLC2

-

6
8

EVTHRES

+

+

6

-

18
22

S2A

14

13

13

8

S2B

13

+

+

6

EGS EDS

8

-

-

71

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

RDBODY

DBODY

LSOURCE

VBAT

5

RSLC1

51

ISCL

50
RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

8

MMED

RDBREAK

72

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

DRAIN

2

SOURC

3

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc = 1
equations {

i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/135))** 3.5))
}
}

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

HUF75329D3, HUF75329D3S

SPICE Thermal Model

REV 23 February 1999

HUF75329D

CTHERM1 th 6 2.80e-3
CTHERM2 6 5 1.00e-2
CTHERM3 5 4 6.80e-3
CTHERM4 4 3 7.00e-3
CTHERM5 3 2 1.60e-2
CTHERM6 2 tl 15.55

RTHERM1 th 6 7.94e-3
RTHERM2 6 5 1.98e-2
RTHERM3 5 4 5.57e-2
RTHERM4 4 3 3.13e-1
RTHERM5 3 2 4.71e-1
RTHERM6 2 tl 6.26e-2

SABER Thermal Model

SABER thermal model HUF75329D
template thermal_model th tl

thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.80e-3
ctherm.ctherm2 6 5 = 1.00e-2
ctherm.ctherm3 5 4 = 6.80e-3
ctherm.ctherm4 4 3 = 7.00e-3
ctherm.ctherm5 3 2 = 1.60e-2
ctherm.ctherm6 2 tl = 15.55

rtherm.rtherm1 th 6 = 7.94e-3
rtherm.rtherm2 6 5 = 1.98e-2
rtherm.rtherm3 5 4 = 5.57e-2
rtherm.rtherm4 4 3 = 3.13e-1
rtherm.rtherm5 3 2 = 4.71e-1
rtherm.rtherm6 2 tl = 6.26e-2
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

tl

CASE

©2001 Fairchild Semiconductor Corpo ration HUF75329D3, HUF75329D3S Rev. B

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PRODUCT STATUS DEFINITIONS
Definition of Terms

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Advance Information

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In Design

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2. A critical component is any component of a life
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Rev. H4