Datasheet HI-8282UT, HI-8282U, HI-8282ST, HI-8282SM-01, HI-8282S Datasheet (HOLT)

...

Page 1

January2001

HI-8282

GENERALDESCRIPTION

TheHI-8282isasilicongateCMOSdeviceforinterfacing theARINC429serialdatabustoa16-bitparalleldatabus. Tworeceiversandanindependenttransmitterare provided.Thereceiverinputcircuitryandlogicare designedtomeettheARINC429specificationsforloading, leveldetection,timing,andprotocol.Thetransmitter sectionprovidestheARINC429communicationprotocol. AdditionalinterfacecircuitrysuchastheHoltHI-8382is requiredtotranslatethe5voltlogicoutputstoARINC429 drivelevels.

The16-bitparalleldatabusexchangesthe32-bitARINC datawordintw ostepswheneitherloadingthetransmitter orinterrogatingthereceivers.Thedatabusinterfaceswith CMOSandTTL.

Timingofallthecircuitrybeginswiththemasterclockinput, CLK.ForARINC429applications,themasterclock frequencyis1MHz.

Eachindependentreceivermonitorsthedatastreamwitha samplingrate10timesthedatarate.Thesamplingrateis softwareselectableateither1MHzor125KHz.Theresults ofaparitycheckareavailableasthe32ndARINCbit.The HI-8282examinesthenullanddatatimingsandwillreject erroneouspatterns.Forexample,witha125KHzclock se lection,thedatafrequencymustbebetween10.4KHz and15.6KHz.

FEATURES

ARINCspecification429compatible

16-Bitparalleldatabus

DirectreceiverinterfacetoARINCbus

Timingcontrol10timesthedatarate

Selectabledataclocks

ReceivererrorrejectionperARINC specification429

Automatictransmitterdatatiming

Selftestmode

Parityfunctions

Lowpower,single5voltsupply

Industrial&fullmilitarytemperatureranges

! DESCSMDpartnumber

PINCONFIGURATION (TopView)

ThetransmitterhasaFirstIn,FirstOut(FIFO)memoryto store8ARINCwordsfortransmission.Thedatarateofthe transmitterissoftwareselectablebydividingthemaster clock,CLK,byeither10or80.Themasterclockisusedto setthetimingoftheARINCtransmissionwithintherequired resolution.

APPLICATIONS

Avionicsdatacommunication

Serialtoparallelconversion

Paralleltoserialconversion

HOLTINTEGRATEDCIRCUITS

N/C-1

-2

D/R1

-3

D/R2

SEL-4

-5

EN1

-6

EN2 BD15-7 BD14-8 BD13-9 BD12-10

BD11-11

44-PinPlasticQuadFlatPack(PQFP)

(Seepage4-38foradditionalPackagePinConfigurations)

4-29(DS8282Rev.A) 01/01

HI-8282PQI

HI-8282PQT

33-N/C 32-N/C 31-

CWSTRX 30-ENTX 29-

429DO 28-429DO 27-TX/R 26-

PL2 25-

PL1 24-BD00 23-BD01

Page 2

PINDESCRIPTION

SYMBOLFUNCTIONDESCRIPTION

VCCPOWER+5V±5% 429DI1(A)INPUTARINCreceiver1positiveinput 429DI1(B)INPUTARINCreceiver1negativeinput 429DI2(A)INPUTARINCreceiver2positiveinput 429DI2(B)INPUTARINCreceiver2negativeinput

D/R1 D/R2

SELINPUTReceiverdatabyteselection(0=BYTE1)(1=BYTE2) EN1

EN2EN1 BD15I/ODataBus BD14I/ODataBus BD13I/ODataBus BD12I/ODataBus BD11I/ODataBus BD10I/ODataBus BD09I/ODataBus BD08I/OData Bus BD07I/ODataBus BD06I/ODataBus

GNDPOWER0V BD05I/ODataBus BD04I/ODataBus BD03I/ODataBus BD02I/ODataBus BD01I/ODataBus BD00I/ODataBus

PL1 PL2PL1.

TX/ROUTPUTTransmitterreadyflag.GoeslowwhenARINCwordloadedintoFIFO.Goeshigh

429DOOUTPUT"ONES"dataoutputfromtransmitter. 429DO

ENTXINPUTEnableTransmission

CWSTR

CLKINPUTMasterClockinput

TXCLKOUTPUTTransmitterClockequaltoMasterClock(CLK),dividedbyeither10or80.

OUTPUTReceiver1datareadyflag OUTPUTReceiver2datareadyflag

INPUTDataBuscontrol,enablesreceiver1datatooutputs INPUTDataBuscontrol,enablesreceiver2datatooutputsifishigh

INPUTLatchenableforbyte1enteredfromdatabustotransmitterFIFO. INPUTLatchenableforbyte2enteredfromdatabustotransmitterFIFO.Mustfollow

OUTPUT"ZEROES"dataoutputfromtransmitter.

INPUTClockforcontrolwordregiste r

INPUTMasterReset,activelow

HI-8282

aftertransmissionandFIFOempty.

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Page 3

FUNCTIONALDESCRIPTION

CONTROLWORDREGISTER

TheHI-8282contains10dataflipflopswhoseDinputsareconnectedtothedatabusandclocksconnectedto.Each flipflopprovidesoptionstotheuserasfollows:

DATA

BUSFUNCTIONCONTROLDESCRIPTION

CWSTR

ARINC429DATAFORMAT

Thefollowingtableshowsthebitpositionsinexchangingdatawith thereceiverorthetransmitter.ARINCbit1isthefirstbit transmittedorreceived.

BYTE1

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC13121110931303212345678

BIT

BDO5SELFTEST0=ENABLEismadepassing429DOand

RECEIVER1Ifenabled,ARINCbits9and,

BDO6DECODER1=ENABLE10mustmatchthenexttwo

BDO7--enabled,theARINCbit9

BDO8--enabled,theARINCbit10

RECEIVER2Ifenabled,ARINCbits9and

BDO9DECODER1=ENABLE10mustmatchthenexttwo

BD10--enabled,thenARINCbit9

BD11--enabled,thenARIN Cbit10

INVERTLogic0enablesnormaloddparity

BD12XMTR1=ENABLEandLogic1enablesevenparity

PARITYoutputintransmitter32ndbit

BD13XMTRDATA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainXMTRdataclock

BD14RCVRDTA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainRCVRdataclock

Ifenabled,aninternalconnection

tothereceiverlogicinputs

429DO

controlwordbits

IfReceiver1Decoderis

mustmatchthisbit

IfReceiver1Decoderis

mustmatchthisbit

controlwordbits

IfReceiver2Decoderis

mustmatchthisbit

IfReceiver2Decoderis

mustmatchthisbit

BYTE2

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC29282726252423222120191817161514

BIT

THERECEIVERS

ARINCBUSINTERFACE

Figure1showstheinputcircuitforeachreceiver.TheARINC429 specificationrequiresthefollowingdetectionlevels:

STATEDIFFERENTIALVOLTAGE

ONE+6.5Voltsto+13Volts

NULL+2.5Voltsto-2.5Volts

ZERO-6.5Voltsto-13Volts

TheHI-8282guaranteesrecognitionoftheselevelswithacommon modeVoltagewithrespecttoGNDlessthan±4Vfortheworstcase condition(4.75Vsupplyand13vsignallevel).

Thetolerancesinthedesignguaranteedetectionoftheabove levels,sotheactualacceptancerangesareslightlylarger.Ifthe ARINCsignalisoutoftheactualacceptanceranges,includingthe nulls,thechiprejectsthedata.

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HI-8282

FUNCTIONALDESCRIPTION(con't)

RECEIVERLOGICOPERATION

Figure2showsablockdiagramofthelogicsectionofeachreceiver.

BITTIMING

TheARINC429specificationcontainsthefollowingtiming specificationforthereceiveddata:

HIGHSPEEDLOWSPEED

BITRATE

PULSERISETIME

PULSEFALLTIME

PULSEWIDTH

AgaintheHI-8282acceptssignalsthatmeetthesespecifications andrejectsoutsidethetolerances.Thewaythelogicoperation achievesthisisdescribedbelow:

1.Keytotheperformanceofthetimingcheckinglogicisanaccurate1MHzclocksource.Lessthan0.1%erroris recommmended.

2.Thesamplingshiftregistersare10bi tslongandmustshow threeconsecutiveOnes,ZerosorNullstobeconsideredvalid data.Additionally,fordatabits,theOneorZerointheupperbits ofthesamplingshiftregistersmustbefollowedbyaNullinthe lowerbitswithinthedatabittime.ForaNullinthewordgap, threeconsecutiveNullsmustbefoundinboththeupperand lowerbitsofthesamplingshiftregister.Inthismannertheminimumpulsewidthisguaranteed.

100KBPS±1%12K-14.5KBPS

1.5±0.5µsec10±5µsec

1.5±0.5µsec10±5µsec 5µsec±5%34.5to41.7µsec

TOPINS

3.Eachdatabitmustfollowitspredecessorbynotlessthan 8samplesandnomorethan12samples.Inthismannerthe bitrateischecked.Withexactly1MHzinputclockfrequency, theacceptabledatabitratesareasfollows:

HIGHSPEEDLOWSPEED

DATABITRATEMIN

DATABITRATEMAX

83KBPS10.4KBPS

125KBPS15.6KBPS

4.TheWordGaptimersamplestheNullshiftregisterevery 10inputclocks(80forlowspeed)afterthelastdatabitofa validreception.IftheNullispresent,theWordGapcounteris incremented.Acountof3willenablethenextreception.

RECEIVERPARITY

ThereceiverparitycircuitcountsOnesreceived,includingthe paritybit,ARINCbit32.Iftheresu ltisodd,then"0"willappearin the32ndbit.

RETRIEVINGDATA

Once32validbitsarerecognized,thereceiverlogicgenerates anEndofSequence(EOS).Ifthereceiverdecoderisenabled andthe9thand10thARINCbitsmatchthecontrolword programbitsorifthereceiverdecoderisdisabled,thenEOS clocksthedatareadyflagflipfloptoa"1",or(orboth)

D/R1D/R2

willgolow.Thedataflagforareceiverwillremainlowuntilafter

ARINCbytesfromthatreceiverareretrieved.Thisis

both accomplishedbyactivatingwithSEL,thebyteselector,low toretrievethefirstbyteandactivatingwithSELhighto retrievethesecondbyte.retrievesdatafromreceiver1and

ret rievesdatafromreceiver2.

EN2

ENI

IfanotherARINCwordisreceived,andanewEOSoccurs beforethetwobytesareretrieved,thedataisoverwrittenbythe newword.

DECODER CONTROL

BITS

SEL

D/R

ZEROS

ONES

NULL

MUX

CONTROL

LATCH

ENABLE

CONTROL

BITS9&10

EOS

SHIFTREGISTER

32TO16DRIVER

32BITLATCH

32BITSHIFTREGISTER

DATA

BITCLOCK

WORDGAP

START

CONTROL

BITBD14

PARITY CHECK

WORDGAP

SEQUENCE

CONTROL

DETECTION

TIMER

ERROR

32ND

CLOCK

OPTION

CLOCK

BIT

COUNTER

AND

BIT

SEQUENCE

EOS

BITCLOCK

END

ERROR CLOCK

ENDOF

CLK

FIGURE2. RECEIVERBLOCKDIAGRAM

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TRANSMITTER

TRANSMITTERPARITY

AblockdiagramofthetransmittersectionisshowninFigure3.

FIFOOPERATION

TheFIFOisloadedsequentiallybyfirstpulsingtoloadbyte1 andthentoloadbyte2.Thecontrollogicautomaticallyloads the31bitwordinthenextavailablepositionoftheFIFO.IfTX/R, thetransmitterreadyflagishigh(FIFOempty),then8words, each31bitslong,maybeloaded.IfTX/Rislow,thenonlythe availablepositionsmaybeloaded.Ifall8positionsarefull,the FIFOignoresfurtherattemptstoloaddata.

PL2

PL1

DATATRANSMISSION

WhenENTXgoeshigh,enablingtransmission,theFIFO positionsareincrementedwiththetopregisterloading intothe datatransmissionshiftregister.Within2.5dataclocksthefirst databitappearsateither429DOor.The31bitsinthe datatransmissionshiftregisterarepresentedsequentiallytothe outputsintheARINC429formatwiththefollowingtiming:

ARINCDATABITTIME10Clocks80Clocks

DATABITTIME5Clocks40Clocks NULLBITTIME5Clocks40Clocks

WORDGAPTIME40Clocks320Clocks

Thewordcounterdetectswhenallloadedpositionsare transmittedandsetsthetransmitterreadyflag,TX/R,high.

429DO

HIGHSPEEDLOWSPEED

TheparitygeneratorcountstheONESinthe31-bitword.Ifthe BD12controlwordbitissetlow,the32ndbittransmittedwillmake parityodd.Ifthecontrolbitishightheparityiseven.

SELFTEST

IftheBD05controlwordbitissetlow,429DOorbecome inputstothereceiverbypassingtheinterfacecircuitry.

429DO

SYSTEMOPERATION

Thetworeceiversareindependentofthetransmitter.Therefore, controlofdataexchangesarestrictlyattheoptionoftheuser.The onlyrestrictionsare:

1.Thereceiveddatamaybeoverwrittenifnotretrieved withinoneARINCwordcycle.

2.TheFIFOcanstore8wordsmaximumandignores attemp tstoloadadditiondataiffull.

3.Byte1ofthetransmitterdatamustbeloadedfirst.

4.Eitherbyteofthereceiveddatamayberetrievedfirst. Bothbytesmustberetrievedtoclearthedatareadyflag.

5.AfterENTX,transmissionenable,goeshighitcannotgo lowuntilTX/R,transmitterreadyflag,goeshigh.Otherwise, oneARINCwordislostduringtransmission.

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Page 6

HI-8282

REPEATEROPERATION

Therepeatermodeofoperationallowsadatawordthathasbeen receivedbytheHI-8282tobeplaceddirectlyintoitsFIFOfor transmission.Aftera32-bitwordhasbeenshiftedintothereceiver shiftregister,theflagwillgolow.Alogic"0"isplacedontheSEL lineandisstrobed.Thisisthesameprocedureasfornormal

EN receiveroperationanditplacesthelowerbyte(16)ofthedataword onthedatabus.Bystrobingatthesame

429DO

D/R

DATA

ARINCBIT

BIT30

NULL

DATA

PL1

BIT31

NULL

DATA

timeas,thebytewillalsobeplacedintothetransmitterFIFO. SEListhentakenhighandisstrobedagaintoplacetheupper byteofthedatawordonthedatabus.Bystrobingatthesame timeas,thesecondbytewillalsobeplacedintotheFIFO.The

PL2

EN datawordisnowreadytobetransmittedaccordingtotheparity programmedintothecontrolwordregister.

Innormaloperation,eitherbyteofareceiveddatawordmayberead fromthereceiverlatchesfirstbyuseofSELinput.Duringrepeater operationhowever,thelowerbyteofthedatawordmustberead first.Thisisnecessarybecause,asthedataisbe ingread,itisalso beingloadedintotheFIFOandthetransmitterFIFOisalways loadedwiththelowerbyteofthedatawordfirst.

NULL

BIT32

WORDGAP

BIT1

NEXTWORD

DATABUS

CWSTR

DATABUS

VALID

CWSET

CWSTR

D/R

SELEN

D/REN

BYTE1VALID BYTE2VALID

ENDATA

ENSEL

CWHLD

DATAEN

ENEN

ENDATA

SELEN

END/R

ENSEL

DATAEN

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Page 7

HI-8282

DATABUS

PL1

PL2

TX/R

PL2

TX/R

ENTX

429DO

PL2EN

ENDAT

ARINCBIT

DATA BIT1

BYTE1VALID

DWSET

DWHLD

PL12

DATA BIT2

BYTE2VALID

DWSET

DWHLD

TX/R

PL12

DTX/R

DATA

BIT32

ENTX/R

429DI

SEL

TX/R

ENTX

429DO

D/R

PL1

PL2

BIT32

D/R

DON'TCARE

SELEN

D/REN

ENPL

END/R

PLEN

ENEN

ENSEL

ENPL

SELEN

TX/REN

DON'TCARE

ENSEL

PLEN

TX/R

ENTX/R

ENDAT

BIT1 BIT32

DTX/R

NULL

HOLTINTEGRATEDCIRCUITS

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Page 8

SupplyVoltageVcc-0.3Vto+7V

PowerDissipation500mW Voltageatpins2,3,4&5-29Vto+29V Voltageatanyotherpin-0.3VtoVcc+0.3V DCCurrentDrainperinputpin10mA

OperatingTemperatureRange:(Industrial)-40°Cto+85°C

(Military)-55°Cto+125°C

StorageTemperatureRange:-65°Cto+150°C

NOTE:Stressesabovethoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.Thesea restressratingsonly. Functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsection softhespecificationsisnotimplied. Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.

Vcc=5V±5%,GND=0V,TA=OperatingTemperatureRange(unlessotherwisespecified).

LIMITS

PARAMETERCONDITIONSUNITSYMBOL

ARINCINPUTS-Pins2,3,4&5

DifferentialInputVoltage:ONEVPins2to3,4to5:Common6.510.013.0V

ZEROVmodevoltagelessthan±4V-13.0-10.0-6.5V

NULLVwithrespecttoGND-2.502.5V

InputResistance:DifferentialR12K

ToGNDR1227K

ToVccR1227k

InputCurrent:InputSinkI200µA

InputSourceI-450µA

IH IL

NUL

I G H

IH IL

MINTYPMAX

W W W

InputCapacitance:DifferentialCPins2to3,4to520pF

(Guaranteedbutnottested)ToGNDC20pF

ToVccC20pF

I G H

BI-DIRECTIONALINPUTS-Pins11-20,22-27

InputVoltage:InputVoltageHIV2.1V

InputVoltageLOV0.7V

InputCurrent:InputSinkI1.5µA

InputSourceI-1.5µA

IH IL

ALLOTHERINPUTS-Pins8-10,28,29,33,34,37,39

InputVoltage:InputVoltageHIV3.5V

InputVoltageLOV0.7V

InputCurrent:InputSinkI10µA

I nputSourceI-20µA

IH IL

OUTPUTS-Pins6,7,11-20,22-27,30-32,38

OutputVoltage:Logic"1"OutputVoltageVI=-1.5mA2.7V

Logic"0"OutputVoltageVI=1.8mA0.4V

OutputCurrent:OutputSinkIV=0.4V3.0mA

(Bi-directionalPins)OutputSourceIV=V-0.4V1.5mA

OutputCurrent:OutputSinkIV=0.4V3.6mA

(AllOtherOutputs)OutputSourceIV=V-0.4V1.5mA

OutputCapacitance:C15pF

OHOH OLOL

OLOUT OHOUTCC

SUPPLYINPUT-Pin1

StandbySupplyCurrent:I20mA OperatingSupplyCurrent:I20mA

CC1

CC2

HOLTINTEGRATEDCIRCUITS

4-36

Page 9

Vcc=5V,GND=0V,TA=OperatingTemperatureRangeandfclk=1mhz0.1%with60/40dutycycle+

PARAMETERSYMBOLUNITS

LIMITS

MINTYPMAX

CONTROLWORDTIMING

PulseWidth-t130ns

Setup-DATABUSValidtoHIGHt140ns

Hold-HIGHtoDATABUSHi-Zt0ns

CWSTR

CWSTR CWSET CWHLD

RECEIVERTIMING

Delay-StartARINC32ndBittoLOW:HighSpeedt16µs

Delay-LOWtoHIGHt200ns

Delay-L0WtoDATABUSValidt200ns

Delay-HIGHtoDATABUSHi-Zt30ns

Spacing-HIGHtonextL0Wt50ns

D/R

LowSpeedt128µs

Delay-LOWtoL0Wt0ns

D/REN

END/R

Setup-SELtoL0Wt20ns

Hold-SELtoHIGHt50ns

PulseWidth-ort240ns

EN1EN2

ENEN

D/R D/R

D/REN END/R

SELEN ENSEL

ENDATA DATAEN

ENEN

FIFOTIMING

PulseWidth-ort200ns

PL1PL2

Setup-DATABUSValidtoHIGHt110ns

Hold-HIGHtoDATABUSHi-Zt20ns

Spacing-ort0ns

Delay-HIGHtoTX/RLOWt840ns

PL2

PL1PL2

DWSET DWHLD

PL12

TX/R

TRANSMISSIONTIMING

Spacing-HIGHtoENTXHIGHt0µs

Delay-ENTXHIGHto429DOor:HighSpeedt25µs Delay-ENTXHI GHto429DOor:LowSpeedt200µs

Delay-32ndARINCBittoTX/RHIGHt400ns

Spacing-TX/RHIGHtoENTXL0Wt0ns

PL2

429D0 429D0

PL2EN

ENDAT ENDAT

DTX/R

ENTX/R

REPEATEROPERATIONTIMING

Delay-LOWtoLOWt0ns

Hold-HIGHtoHIGHt0ns

Delay-TX/RLOWtoENTXHIGHt0ns

MasterResetPulseWidth

ENPL

PLEN

ENPL

PLEN

TX/REN

t400ns

ARINCDataRateandBitTiming

±1%

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Page 10

ADDITIONALHI-8282PINCONFIGURATIONS

(Seepage4-29forthe44-pinPlasticQuadFlatPack)

44-PINPLASTICPLCC

HI-8282J-44

44-PINJ-LEADCERQUAD

HI-8282U

44-PINCERAMICLCC

HI-8282S

40-PINCERAMICSIDEBRAZEDDIP

HI-8282C

HOLTINTEGRATEDCIRCUITS

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Page 11

HI-8282

PART

PACKAGE

NUMBER DESCRIPTION

TEMPERATURE RANGE

FLOW

BURN INLEAD

FINISH

HI-8282C 40 PIN CERAMIC SIDE BRAZED DIP -40°C TO +85°C I NO GOLD

HI-8282CT 40 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C T NO GOLD

HI-8282CM-01 40 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C M YES SOLDER

HI-8282CM-03* 40 PIN CERAMIC SIDE BRAZED DIP -55°C TO +125°C DSCC YES SOLDER

HI-8282J-44 44 PIN PLASTIC J LEAD -40°C TO +85°C I NO SOLDER

HI-8282JT-44 44 PIN PLASTIC J LEAD -55°C TO +125°C T NO SOLDER

HI-8282PQI 44 PIN PLASTIC QUAD FLAT PACK -40°C TO +85°C I NO SOLDER

HI-8282PQT 44 PIN PLASTIC QUAD FLAT PACK -55°C TO +125°C T NO SOLDER

HI-8282S 44 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C I NO GOLD

HI-8282ST 44 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C T NO GOLD

HI-8282SM-01 44 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C M YES SOLDER

HI-8282U 44 PIN CERQUAD -40°C TO +85°C I NO SOLDER

HI-8282UT 44 PIN CERQUAD -55°C TO +125°C T NO SOLDER

*SMD#5962-8688002QA

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40-PINCERAMICSIDE-BRAZEDDIP

(51.308MAX)

HI-8282PACKAGEDIMENSIONS

inches(millimeters)

PackageType:

2.020MAX

40C

.610 ± .010

(15.494 ± .254)

.225MAX

(5.715MAX)

.125MIN

(3.175MIN)

44-PINJ-LEADCERQUAD

214443

.018TYP

(.457TYP)

.050TYP

(1.270TYP)

.688 ± .005

(17.475 ± .127)

MAX.

.100BSC

(2.540BSC)

.085 ± .009

(2.159 ± .229)

.595 ± .010

(15.113 ± .254)

.010 + .002 /− .001

(.254 + .051 /− .025)

(15.748 ± .305)

.600 ± .010

(15.240 ± .254)

PackageType:

.620 ± .012

44U

.039 ± .005

(.990 ± .127)

.019 ±

.650

(16.510 .254)

± .051)

SQ.

.050

(1.270)

.100 .007

(2.540 ±

HOLTINTEGRATEDCIRCUITS

.200

(5.080)

MAX.

Page 13

44-PINPLASTICPLCC

HI-8282PACKAGEDIMENSIONS

inches(millimeters)

PackageType:

44J

PINNO.1

.045x45°

.690 ± .005

(17.526 ± .127)

SQ.

.172 ± .008

(4.369 ± .203)

(15.494 ± .508)

PINNO.1IDENT

.653 ± .004

(16.586 ± .102)

SQ.

SEEDETAIL

.610 ± .020

44-PINPLASTICQUADFLATPACK(PQFP)

.045x45°

.009 .011

DETAILA

.050 ± .005

(1.27 ± .127)

.017 ± .004

(.432 ± .102)

.015±.002

(.381 ± .051)

.020MIN

(.508 ΜΙΝ ) .025

.045

PackageType:

.007

MAX.

(.17)

.031 ± .005

(.787 ± .127)

44PQS

.097

(2.45)

.547±.010

(13.90±.25)

SQ.

MAX.

SeeDetailA

.394±.004 (10.0±.10)

SQ.

.079+.004/-.006

(2.00+.10/-.15)

HOLTINTEGRATEDCIRCUITS

.008

(.20R)

TYP.

.0315BSC

(.80BSC)

.014±..002

(.35±.05)

.035+.006/-.004

(.88+.15/-.10)

.012

TYP.

(.30R)

DetailA

0 °≤Θ≤ 7 °

Page 14

HI-8282PACKAGEDIMENSIONS

44-PINCERAMICLEADLESSCHIPCARRIER

inches(millimeters)

PackageType:

44S

.020INDEX

(.508INDEX)

.651 ± .011

(16.535 ± .279)

SQ.

PIN1

.040x45°3PLCS

(1.016x45°3PLCS)

.050 ±. 005

(1.270 ± .127)

.025 ± .003

(.635 ± .076)

.092 ±. 028

(2.336 ± .711)

.075 ± .004

(1.905 ± .101)

.050BSC

(1.270BSC)

.009R±.006

(.229R ± .152)

.326 ± .006

(8.280 ± .152)

PIN1

HOLTINTEGRATEDCIRCUITS