Datasheet HFA1149 Datasheet (Intersil Corporation)

Page 1

HFA1149

Data Sheet June 2000

450MHz, Low Power, Video Operational Ampliﬁer with Programmable Output Disable

The HFA1149 is a high speed, low power, current feedback ampliﬁer built with Intersil’s proprietary complementary bipolar UHF-1 process. This ampliﬁer features a unique combination of power and performance speciﬁcally tailored for video applications.

The HFA1149 incorporates an output disable pin which is TTL/CMOS compatible, and user programmable for polarity (active high or low). This feature eliminates the inverter required between ampliﬁers in multiplexer conﬁgurations. The ultra-fast (12ns/20ns) disable/enable times make the HFA1149 the obvious choice for pixel switching and other high speed multiplexingapplications.TheHFA1149isahigh performance, pin compatible upgrade f or the popular HA-5020 and HFA1145, as well as the CLC410.

For a comparably performing op amp without an output disable, please refer to the HFA1109 data sheet.

Ordering Information

PART NUMBER

(BRAND)

HFA1149IB (H1149)

HFA11XXEVAL DIP Evaluation Board for High Speed

TEMP.

RANGE (oC) PACKAGE

-40 to 85 8 Ld SOIC M8.15

Op Amps

PKG.

NO.

Pinout

HFA1149

(SOIC)

TOP VIEW

THRESHOLD SET

-IN

+IN

1 2

3 4

V-

DIS / DIS

V+

OUT POLARITY SET

File Number 4304.3

Features

• Wide - 3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 450MHz

• Gain Flatness (To 250MHz) . . . . . . . . . . . . . . . . . . . 0.8dB

• Very Fast Slew Rate (A

= +2). . . . . . . . . . . . . . 1100V/µs

• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1.7MΩ

• Differential Gain/Phase. . . . . . . . . . . 0.02%/0.02 Degrees

• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

• Fast Output Disable/Enable . . . . . . . . . . . . . . . 12ns/20ns

Applications

• Professional Video Processing

• Video Switchers and Routers

• Medical Imaging

• PC Multimedia Systems

• Video Pixel Switching

• Video Distribution Ampliﬁers

• Flash Converter Drivers

• Radar/IF Processing

HFA1149 PIN DESCRIPTIONS

PIN NAME DESCRIPTION

Threshold Set Optional Logic Threshold Set. Maintains disable

pin TTL compatibility with asymmetrical supplies (e.g., +10V, 0V).

Polarity Set Defines Polarity of Disable Input. High or floating

selects active low disable (i.e., DIS).

DIS/DIS TTL CompatibleDisable Input. Outputis drivento

atrueHi-Z statewhen active.Polarity dependson state of Polarity Set Pin.

HFA1149 DISABLE FUNCTIONALITY

POLARITY SET

(PIN 5) DISABLE (PIN 8) OUTPUT (PIN 6)

High or Float High or Float Enabled High or Float Low Disabled

Low High or Float Disabled Low Low Enabled

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Page 2

HFA1149

Absolute Maximum Ratings Thermal Information

Voltage Between V+ and V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V

DC Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V

Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V

Output Current (Note 2). . . . . . . . . . . . . . . . Short Circuit Protected

30mA Continuous

60mA ≤ 50% Duty Cycle

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . 1000V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . 1000V

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . 50V

SUPPLY

±1V

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. Output isshort circuitprotected to ground.Brief shortcircuits toground will notdegrade reliability,however, continuous(100% dutycycle) output current must not exceed 30mA for maximum reliability.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Speciﬁcations V

PARAMETER TEST CONDITIONS

INPUT CHARACTERISTICS

Input Offset Voltage A 25 - 1 5 mV

Average Input Offset Voltage Drift B Full - 10 - µV/oC Input Offset Voltage

Common-Mode Rejection Ratio Input Offset Voltage

Power Supply Rejection Ratio Non-Inverting Input Bias Current A 25 - 4 10 µA

Non-Inverting Input Bias Current Drift B Full - 30 - nA/oC Non-Inverting Input Bias Current

Power Supply Sensitivity Inverting Input Bias Current A 25 - 2 10 µA

Inverting Input Bias Current Drift B Full - 40 - nA/oC Inverting Input Bias Current

Common-Mode Sensitivity Inverting Input Bias Current

Power Supply Sensitivity Non-Inverting Input Resistance ∆VCM = ±2V A 25, 85 0.8 1.7 - MΩ

Inverting Input Resistance B 25 - 60 - Ω Input Capacitance B 25 - 1.6 - pF Input Voltage Common Mode Range (Implied

by VIO CMRR, +RIN, and -I

BIAS

CMS tests)

= ±5V, AV= +2, RF= 250Ω, RL = 100Ω, Unless Otherwise Speciﬁed

SUPPLY

(NOTE 3)

TEST

LEVEL

A Full - 2 8 mV

∆VCM = ±2V A 25 47 50 - dB ∆VCM = ±2V A Full 45 48 - dB ∆VPS = ±1.25V A 25 50 53 - dB ∆VPS = ±1.25V A Full 47 51 - dB

A Full - 5 15 µA

∆VPS = ±1.25V A 25 - 0.5 1 µA/V ∆VPS = ±1.25V A Full - 0.5 3 µA/V

A Full - 3 15 µA

∆VCM = ±2V A 25 - 3 6 µA/V ∆VCM = ±2V A Full - 3 8 µA/V ∆VPS = ±1.25V A 25 - 1.6 5 µA/V ∆VPS = ±1.25V A Full - 1.6 8 µA/V

∆VCM = ±2V A -40 0.5 1.4 - MΩ

A Full ±2 ±2.5 - V

TEMP.

(oC) MIN TYP MAX UNITS

Page 3

HFA1149

Electrical Speciﬁcations V

= ±5V, AV= +2, RF= 250Ω, RL = 100Ω, Unless Otherwise Speciﬁed (Continued)

SUPPLY

(NOTE 3)

PARAMETER TEST CONDITIONS

TEST

LEVEL

TEMP.

(oC) MIN TYP MAX UNITS

Input Noise Voltage Density (Note 5) f = 100kHz B 25 - 4 - nV/√Hz Non-Inverting Input Noise Current Density

f = 100kHz B 25 - 2.4 - pA/√Hz

(Note 5) Inverting Input Noise Current Density

f = 100kHz B 25 - 40 - pA/√Hz

(Note 5)

TRANSFER CHARACTERISTICS

Open Loop Transimpedance Gain (Note 5) B 25 - 500 - kΩ Minimum Stable Gain B Full - 1 - V/V

AC CHARACTERISTICS

-3dB Bandwidth (V

= 0.2V

OUT

P-P

, Note 5)

AV = -1, RF = 200Ω B 25 300 375 - MHz

B Full 290 360 - MHz

AV = +1, +RS = 700Ω B 25 280 330 - MHz

B Full 260 320 - MHz

AV = +2 B 25 390 450 - MHz

B Full 350 410 - MHz

Gain Peaking AV = +2, V

OUT

= 0.2V

P-P

B 25 - 0 0.2 dB B Full - 0 0.5 dB

Gain Flatness (AV = +2, V

OUT

= 0.2V

P-P

, Note 5)

To 125MHz B 25 -1.0 -0.45 - dB

B Full -1.1 -0.45 - dB

To 200MHz B 25 -1.6 -0.75 - dB

B Full -1.7 -0.75 - dB

To 250MHz B 25 -1.9 -0.85 - dB

B Full -2.2 -0.85 - dB

Gain Flatness AV= +1,+RS= 700Ω,V

OUT

= 0.2V

P-P

(Note 5)

To 125MHz B 25 ±0.3 ±0.1 - dB

B Full ±0.4 ±0.1 - dB

To 200MHz B 25 ±0.8 ±0.35 - dB

B Full ±0.9 ±0.35 - dB

To 250MHz B 25 ±1.3 ±0.6 - dB

B Full ±1.4 ±0.6 - dB

OUTPUT CHARACTERISTICS

Output Voltage Swing, Unloaded (Note 5)

Output Current (Note 5)

AV = -1, RL = ∞ A25±3 ±3.2 - V

A Full ±2.8 ±3- V

AV = -1, RL = 75Ω A 25, 85 ±33 ±36 - mA

A -40 ±30 ±33 - mA Output Short Circuit Current AV = -1 B 25 - 120 - mA Closed Loop Output Resistance (Note 5) DC, AV = +1, Enabled B 25 - 0.05 - Ω Second Harmonic Distortion

OUT

= 2V

P-P

, Note 5)

Third Harmonic Distortion (V

OUT

= 2V

P-P

, Note 5)

20MHz B 25 - -55 - dBc 60MHz B 25 - -57 - dBc 20MHz B 25 - -68 - dBc 60MHz B 25 - -60 - dBc

Reverse Isolation (S12) 30MHz B 25 - -65 - dB

TRANSIENT CHARACTERISTICS

Rise and Fall Times V

OUT

= 0.5V

P-P

B 25 - 1.1 1.3 ns

B Full - 1.1 1.4 ns

Page 4

HFA1149

Electrical Speciﬁcations V

= ±5V, AV= +2, RF= 250Ω, RL = 100Ω, Unless Otherwise Speciﬁed (Continued)

SUPPLY

(NOTE 3)

PARAMETER TEST CONDITIONS

Overshoot V

OUT

= 0.5V

P-P

TEST

LEVEL

B25-02%

TEMP.

(oC) MIN TYP MAX UNITS

B Full - 0.5 5 % Slew Rate AV = -1, RF= 200Ω

= 5V

OUT

AV = +1, V

P-P

OUT

= 4V

+RS = 700Ω AV = +2, V

OUT

= 5V

P-P

B 25 2300 2600 - V/µs

B Full 2200 2500 - V/µs

B 25 475 550 - V/µs

B Full 430 500 - V/µs

B 25 940 1100 - V/µs

B Full 800 950 - V/µs Settling Time

= +2V to 0V step, Note 5)

OUT

To 0.1% B 25 - 19 - ns To 0.05% B 25 - 23 - ns To 0.01% B 25 - 36 - ns

Overdrive Recovery Time VIN = ±2V B 25 - 5 - ns

VIDEO CHARACTERISTICS

Differential Gain (f = 3.58MHz)

RL = 150Ω B 25 - 0.02 0.06 %

B Full - 0.03 0.09 %

RL = 75Ω B 25 - 0.04 0.09 %

B Full - 0.05 0.12 % Differential Phase

(f = 3.58MHz)

RL = 150Ω B 25 - 0.02 0.06 Degrees

B Full - 0.02 0.06 Degrees

RL = 75Ω B 25 - 0.05 0.09 Degrees

B Full - 0.06 0.13 Degrees

POWER SUPPLY CHARACTERISTICS

Power Supply Range C 25 ±4.5 - ±5.5 V Power Supply Current (Note 4) A 25 - 9.6 10 mA

A Full - 10 11 mA HFA1149 DISABLE CHARACTERISTICS Polarity Set = Floating, Threshold Set = Floating, Unless Otherwise Specified Disabled Supply Current V

= 0V A Full - 2.8 3.5 mA

DIS

Digital Input Logic Low (Note 4) A Full - - 0.8 V Digital Input Logic High (Note 4) A 25 2.0 - - V

A Full 2.2 - - V Digital Input Logic Low Current (Note 4) V Digital Input Logic High Current (Note 4) V Output Disable Time (Note 5) VIN = ±0.5V,

Output Enable Time (Note 5) VIN = ±0.5V,

V Disabled Output Capacitance V Disabled Output Leakage V

V Off Isolation

= 0V, VIN = 1V

DIS

P-P

, Note 5)

At 10MHz B 25 - -64 - dB

At 30MHz B 25 - -54 - dB

= 0V A Full - 100 200 µA

DIGITAL

= 5V A Full - 1 15 µA

DIGITAL

B 25 - 12 - ns

= 2.4V to 0V

DIS

B 25 - 20 - ns

= 0V to 2.4V

DIS

= 0V B 25 - 2.5 - pF

DIS

= 0V, VIN = 2V,

DIS

= ±3V

OUT

A Full - 3 10 µA

NOTES:

3. Test Level: A. Production tested; B. Typical or guaranteed limit based on characterization; C. Design Typical for information only.

4. Digital inputs are Polarity Set and DIS / DIS.

5. See Typical Performance Curves for more information.

Page 5

Application Information

Optimum Feedback Resistor

Although a current feedback ampliﬁer’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback ampliﬁer, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback ampliﬁer’s unique relationship between bandwidth and R All current feedback ampliﬁers require a feedback resistor, even for unity gain applications, and R

, in conjunction with

the internal compensation capacitor, sets the dominant pole of thefrequencyresponse.Thus, the ampliﬁer’sbandwidth is inversely proportional to R optimized for a 250Ω R

. The HFA1149 design is

at a gain of +2. Decreasing R

decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problemsduetothe feedback impedancedecreaseat higher frequencies). At higher gains the ampliﬁer is more stable, so R

can be decreased in a trade-off of stability for bandwidth.

TABLE 1. OPTIMUM FEEDBACK RESISTOR

GAIN (ACL)R

-1 200 375 +1 250 (+RS = 700Ω) 330 +2 250 450 +5 100 160

+10 90 70

(Ω) BANDWIDTH (MHz)

Table 1 lists recommended RF values, and the expected bandwidth, for various closed loop gains. For a gain of +1, a resistor (

) in series with +IN is required to reduce gain

peaking and increase stability

Output Disable Function

The HFA1149incorporates an output disable function that is useful for reducing power dissipation or for multiplexing signals onto a common analog bus. When disabled, the inverting input and the output become high impedances (however, the feedback network for gains other than +1 still present a load to ground from the output), the supply current reduces by 68%, and the input to output isolation becomes greater than 60dB. The ampliﬁer is disabled by driving the DIS / DIS input to its active state.

The active state of the DIS / DIS input is user programmable via the HFA1149’s Polarity Set input (see next paragraph). If the Polarity Set input is left ﬂoating, or is tied to a logic high (e.g., V+), then the disable function is activated by a logic low on the amps). If the Polarity Set input is connected to a logic low (e.g., GND), thenalogichighon the the ampliﬁer.

DIS / DIS input (typical of most output disable op

DIS / DIS input disables

HFA1149

The

DIS / DIS input is TTL compatible, and unlike most competitive devices, the TTL compatibility can be maintained when the HFA1149 is operated at supplies other than ±5V (see the “Threshold Set input” section below).

An internal resistive bias network ensures that the

DIS / DIS

pin is pulled high if it is undriven on the PCB.

Polarity Set Input

A novel feature of the HFA1149 is the polarity programmability of the disable control pin (

DIS / DIS). Depending on the state of the Polarity Set input (pin 5), the designer can deﬁne the active state to be high or low for the DIS / DIS input (see the “HFA1149 Disable Functionality” table on the front page). With this feature, a 2:1 multiplexer can be created by deﬁning one ampliﬁer’s disable control as active low (Polarity Set = High or ﬂoating), and the other ampliﬁer’s control as active high (Polarity Set = Low). Note that if the Polarity Set pin is left ﬂoating, an internal pull-up resistor pulls the pin high, and the HFA1149 becomes a drop-in replacement for any standard ±5V supply op amp with output disable (e.g., CLC410, CLC411, CLC430, HA-5020, HFA1145, AD810). Likewise, if the disable and polarity set pins are both ﬂoated, the HFA1149 works just like a standard op amp (i.e., the output is always enabled).

Threshold Set Input for TTL Compatibility

The HFA1149derivesaninternal threshold reference forthe digital circuitry as long as the power supplies are nominally

±5V. This reference is used to ensure the TTL compatibility

of the

DIS / DIS and Polarity Set inputs. With symmetrical

±5V supplies the Threshold Set pin(Pin1)mustbe ﬂoated to

guarantee TTL compatibility. If asymmetrical supplies (e.g., +10V, 0V) are utilized, and TTL compatibility is desired, the Threshold Set pin must be connected to an external voltage (e.g., GND for +10V, 0V operation). The following equation should be used to determine the voltage (V applied to the Threshold Set pin:

THSET

where V

1.58 V

DIGTH

is the desired switching point (typically 1.4V

DIGTH

V-

1.6V+()

----- -– 0.46 V+(),–= 8

for TTL compatibility) of the Polarity Set and inputs.

Figure 1 illustrates the input impedanceoftheThresholdSet pin for calculating the input current at a given V

V+

THSET

FIGURE 1. THRESHOLD SET INPUT IMPEDANCE

3kΩ

7kΩ

25kΩ

V-

THSET)

DIS / DIS

THSET

to be

Page 6

HFA1149

PC Board Layout

The frequency response of this ampliﬁer depends greatly on the care taken in designing the PC board. The use of low

inductance components such as chipresistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to

decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases.

Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section.

Care must also be taken to minimize the capacitance to ground seen by the ampliﬁer’s inverting input (-IN). The larger thiscapacitance,the worse the gain peaking, resulting in pulse overshoot and possible instability. Thus, it is recommended that the ground plane be removed under traces connected to -IN, and connections to -IN should be kept as short as possible.

Driving Capacitive Loads

Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the ampliﬁer’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (R prior to the capacitance.

) in series with the output

BOARD SCHEMATIC

510Ω

50Ω

0.1µF10µF

510Ω

1 2 3 4

-5V

TOP LAYOUT

+IN

BOTTOM LAYOUT

8 7

50Ω

6 5

GND

OUT

V+

V-

GND

OUT

10µF0.1µF

+5V

and CL form a low pass network at the output, thus

limiting system bandwidth well below the ampliﬁer bandwidth. By decreasing R

as CL increases, the

maximum bandwidth is obtained without sacriﬁcing stability. In spite of this, bandwidth still decreases as the load capacitance increases.

Evaluation Board

The performance of the HFA1149 may be evaluated using the HFA11XX Evaluation Board (part number HFA11XXEVAL). Please contact your local sales ofﬁce for information. When evaluating this ampliﬁer, the two 510Ω gain setting resistors on the evaluation board should be changed to 250Ω.

The layout and schematic of the board are shown in Figure 2.

NOTE: The SOIC version may be evaluated in the DIP board by using aSOIC-to-DIP adapter suchas Aries Electronics Part Number 08-350000-10.

FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT

Page 7

HFA1149

Typical Performance Curves V

200

AV = +2

150

100

-50

OUTPUT VOLTAGE (mV)

-100

-150

-200

FIGURE 3. SMALL SIGNAL PULSE RESPONSE

200

AV = +1

150

100

TIME (5ns/DIV.)

= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,

SUPPLY

RL= 100Ω, Unless Otherwise Speciﬁed

2.0

1.5

1.0

0.5

-0.5

OUTPUT VOLTAGE (V)

-1.0

-1.5

-2.0

FIGURE 4. LARGE SIGNAL PULSE RESPONSE

2.0

1.5

1.0

AV = +2

TIME (5ns/DIV.)

AV = +1

-50

OUTPUT VOLTAGE (mV)

-100

-150

-200 TIME (5ns/DIV.)

0.5

-0.5

OUTPUT VOLTAGE (V)

-1.0

-1.5

-2.0

TIME (5ns/DIV.)

FIGURE 5. SMALL SIGNAL PULSE RESPONSE FIGURE 6. LARGE SIGNAL PULSE RESPONSE

200

150

100

-50

OUTPUT VOLTAGE (mV)

-100

AV = -1

2.0

1.5

1.0

0.5

-0.5

OUTPUT VOLTAGE (V)

-1.0

AV = -1

-150

-200 TIME (5ns/DIV.)

-1.5

-2.0 TIME (5ns/DIV.)

FIGURE 7. SMALL SIGNAL PULSE RESPONSE FIGURE 8. LARGE SIGNAL PULSE RESPONSE

Page 8

HFA1149

Typical Performance Curves V

200

150

= +5

100

-50

OUTPUT VOLTAGE (mV)

-100

-150

-200

FIGURE 9. SMALL SIGNAL PULSE RESPONSE FIGURE 10. LARGE SIGNAL PULSE RESPONSE

DISABLE

800mV/DIV.

(0.4V TO 2.4V)

AV = +10

AV = +5

TIME (5ns/DIV.)

= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,

SUPPLY

RL= 100Ω, Unless Otherwise Speciﬁed (Continued)

2.0

1.5 AV = +5

1.0

= +10

0.5

-0.5

OUTPUT VOLTAGE (V)

-1.0

-1.5

-2.0

OUT

3 0

GAIN (dB)

-3

= 200mV

AV = +10

P-P

TIME (5ns/DIV.)

GAIN

AV = +5

AV = +1

= +10

AV = +1

AV = -1

AV = +1

AV = -1

OUTPUT

400mV/DIV.

AV= +2, VIN = 0.5V

TIME (10ns/DIV.)

PHASE

0.3 1 10 100 700 FREQUENCY (MHz)

FIGURE 11. OUTPUT ENABLE AND DISABLE RESPONSE FIGURE 12. FREQUENCY RESPONSE

510

= 200mV

OUT

3 0

-3

NORMALIZED GAIN (dB)

0.3 1 10 100 700

P-P

GAIN

AV = +10

PHASE

AV = +10

FREQUENCY (MHz)

AV = +5

AV = +2

AV = +5

AV = +2

0 90 180 270

PHASE (DEGREES)

480

450

420

390

BANDWIDTH (MHz)

360

330

300

-75 -50 -25 0 25 50 75 100 125

AV = +2

AV = -1

AV = +1

TEMPERATURE (oC)

FIGURE 13. FREQUENCY RESPONSE FIGURE 14. -3dB BANDWIDTH vs TEMPERATURE

0 90 180 270

NORMALIZED PHASE (DEGREES)

Page 9

HFA1149

Typical Performance Curves V

= 200mV

OUT

0.1 0

-0.1

-0.2

-0.3

-0.4

-0.5

NORMALIZED GAIN (dB)

-0.6

-0.7

1 10 100 500

-30 AV=+1

-40

-50

-60

-70

DISTORTION (dBc)

-80

P-P

AV = +2

FREQUENCY (MHz)

FIGURE 15. GAIN FLATNESS FIGURE 16. OPEN LOOP TRANSIMPEDANCE

100MHz

50MHz

20MHz

= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,

SUPPLY

RL= 100Ω, Unless Otherwise Speciﬁed (Continued)

116

AV = +1

10MHz

106

)

()

76 66 56

(dB, 20 LOG

ZOL

0.01 0.1

-20 A

-30

-40

-50

-60

-70

DISTORTION (dBc)

-80

-90

=+1

0.3 1 3 6 10 30 100 500

FREQUENCY (MHz)

100MHz

50MHz

20MHz

10MHz

0 45 90 135 180

PHASE (DEGREES)

-90

-6 -3 0 9 1236 OUTPUT POWER (dBm)

FIGURE 17. 2nd HARMONIC DISTORTION vs P

-30 AV=+2

-40

-50

-60

-70

DISTORTION (dBc)

-80

-90

100MHz

50MHz

10MHz

20MHz

-6 -3 0 9 12 1536 OUTPUT POWER (dBm)

FIGURE 19. 2nd HARMONIC DISTORTION vs P

OUT

-100

-6 -3 0 9 12 OUTPUT POWER (dBm)

FIGURE 18. 3rd HARMONIC DISTORTION vs P

-30 AV=+2

-40

100MHz

-50

50MHz

-60

20MHz

-70

DISTORTION (dBc)

10MHz

-80

-90

-6 -3 0 9 12 1536 OUTPUT POWER (dBm)

FIGURE 20. 3rd HARMONIC DISTORTION vs P

OUT

Page 10

HFA1149

Typical Performance Curves V

= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,

SUPPLY

RL= 100Ω, Unless Otherwise Speciﬁed (Continued)

-20 V

= 2V

OUT

-30

-40

-50

-60

DISTORTION (dBc)

-70

-80

0 102030405060708090100

P-P

AV= +2, -1

AV=+1

FREQUENCY (MHz)

-20 V

= 2V

OUT

P-P

-30

-40

-50

-60

DISTORTION (dBc)

-70

AV=+1

-80

0 102030405060708090100

FREQUENCY (MHz)

AV = +1

AV = -1

AV = +2

FIGURE 21. 2nd HARMONIC DISTORTION vs FREQUENCY FIGURE 22. 3rd HARMONIC DISTORTION vs FREQUENCY

-30

-40

-50

-60

-70

-80

OFF ISOLATION (dB)

-90

-100

AV = +2 V

= 1V

P-P

0.01

OUTPUT RESISTANCE (Ω)

AV = +2

100

0.1

0.3 1 10 100 1000 FREQUENCY (MHz)

0.5 100101 FREQUENCY (MHz)

FIGURE 23. CLOSED LOOP OUTPUT RESISTANCE FIGURE 24. OFF ISOLATION

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

OUTPUT VOLTAGE (V)

2.0

1.8

1.6

OUT

(RL= 100Ω)

OUT

(RL=50Ω)

|-V

OUT

-50

| (RL= 100Ω)

-25 25 75 125-75

TEMPERATURE (°C)

|-V

| (RL= 100Ω)

OUT

(RL=50Ω)

OUT

|-V

| (RL=50Ω)

OUT

0 50 100

13.5 13

12.5 12

11.5 11

10.5 10

SUPPLY CURRENT (mA)

9.5 9

8.5

4.5 5.5 6.5 7.5

45678

SUPPLY VOLTAGE (±V)

FIGURE 25. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 26. SUPPLY CURRENT vs SUPPLY VOLTAGE

Page 11

HFA1149

Typical Performance Curves V

= ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,

SUPPLY

RL= 100Ω, Unless Otherwise Speciﬁed (Continued)

17 16 15 14 13 12 11 10

9 8

SUPPLY CURRENT (mA)

7 6 5 4

-75 0 50 100

VS = ±8V

VS = ±5V

-50

VS = ±4V

-25 25 75 125 TEMPERATURE (

100

NI+

NOISE VOLTAGE (nV/√Hz)

0.1 1 10 100 FREQUENCY (kHz)

FIGURE 27. SUPPLY CURRENT vs TEMPERATURE FIGURE 28. INPUT NOISE CHARACTERISTICS

= +2

= 2V

0.1

OUT

100

NI-

NI+

Hz)

NOISE CURRENT (pA/√

0.05

0.025

-0.025

-0.05

SETTLING ERROR (%)

-0.1

10 80 10090

30 50 7020 40 60

TIME (ns)

FIGURE 29. SETTLING RESPONSE

Page 12

Die Characteristics

HFA1149

DIE DIMENSIONS

59 mils x 80 mils x 19 mils 1500µm x 2020µm x 483µm

METALLIZATION

Type: Metal 1: AICu(2%)/TiW Type: Metal 2: AICu(2%) Thickness: Metal 1: 8k

Å ±0.4kÅ

Thickness: Metal 2: 16kÅ±0.8kÅ

Metallization Mask Layout

THRESHOLD SET

GLASSIVATION

Type: Nitride Thickness: 4kÅ±0.5kÅ

TRANSISTOR COUNT

130

SUBSTRATE POTENTIAL (POWERED UP)

Floating (Recommend Connection to V-)

HFA1149

DIS / DIS

-IN

+IN

V+

OUT

POLARITY SET

V-

NCNC

Page 13

Small Outline Plastic Packages (SOIC)

HFA1149

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

h x 45

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined inthe “MO Series SymbolList” in Section 2.2of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” doesnot include moldflash, protrusions orgate burrs. Mold flash,protrusion andgate burrs shallnot exceed0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer onthe body isoptional. If itis not present,a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, asmeasured 0.36mm (0.014 inch) orgreater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Convertedinch dimensions are not necessarily exact.

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6

N8 87

Rev. 0 12/93

NOTESMIN MAX MIN MAX

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor productsare sold by description only. Intersil Corporation reserves the right to make changesin circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believ edto be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240

EUROPE

Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05

ASIA

Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369