• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS112MS is a Radiation Hardened dual JK
flip-flop with set and reset. The flip-flop changes states with
the negative transition of the clock (CP1N or CP2N).
The HCTS112MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Pinouts
CP1
K1
J1
S1
Q1
Q1
Q2
GND
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
VCC
1
CP1
2
K1
3
J1
4
S1
Q1
5
6
Q1
7
Q2
8
GND
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
116
2
3
4
5
6
7
8
16
15
R1
14
R2
13
CP2
K2
12
J2
11
10
S2
9
Q2
15
14
13
12
11
10
9
VCC
R1
R2
CP2
K2
J2
S2
Q2
The HCTS112MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBERTEMPERATURE RANGESCREENING LEVELPACKAGE
HCTS112DMSR-55oC to +125oCIntersil Class S Equivalent16 Lead SBDIP
HCTS112KMSR-55oC to +125oCIntersil Class S Equivalent16 Lead Ceramic Flatpack
HCTS112D/Sample+25oCSample16 Lead SBDIP
HCTS112K/Sample+25oCSample16 Lead Ceramic Flatpack
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Input CapacitanceCINVCC = 5.0V, f = 1MHz1+25oC-10pF
Output Transition
Time
Setup Time J, K to
CP
Hold Time J, K to CPTHVCC = 4.5V1+25oC3-ns
Removal Time R, S
to CP
Pulse Width R, STW (R, S)VCC = 4.5V1+25oC16-ns
Pulse Width CPTW (CP)VCC = 4.5V1+25oC14-ns
Max Operating
Frequency
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
CPDVCC = 5.0V, f = 1MHz1+25oC-60pF
1+125oC, -55oC-150pF
1+125oC-10pF
TTHL,
TTLH
TSUVCC = 4.5V1+25oC14-ns
TREMVCC = 4.5V1+25oC18-ns
FMAXVCC = 4.5V1+25oC-30MHz
VCC = 4.5V1+25oC-15ns
1+125oC-22ns
1+125oC16-ns
1+125oC3-ns
1+125oC20-ns
1+125oC18-ns
1+125oC16-ns
1+125oC-20MHz
UNITSMINMAX
493
Spec Number 518603
Page 5
Specifications HCTS112MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K LIMITS
RAD
(NOTES 1, 2)
PARAMETERSYMBOL
Quiescent CurrentICCVCC = 5.5V, VIN = VCC or GND+25oC-0.4mA
CONDITIONSTEMPERATURE
UNITSMINMAX
Output Current (Sink)IOLVCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
Output Current
(Source)
Output Voltage LowVOLVCC = 4.5V or 5.5V, VIH = VCC/2,
Output Voltage HighVOHVCC = 4.5V or 5.5V, VIH = VCC/2,
Input Leakage CurrentIINVCC = 5.5V, VIN = VCC or GND+25oC±5µA
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
o
C min., Method 1015
+125
failures from subgroup 7.
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
C or
496
Spec Number 518603
Page 8
AC Timing Diagrams
VIH
VS
VIL
VOH
VOL
INPUT
TPLH
VS
TPHL
OUTPUT
HCTS112MS
AC VOLTAGE LEVELS
PARAMETERHCTSUNITS
VCC4.50V
VIH3.00V
VS1.30V
VIL0V
VOH
VOL
TTLH
20%
80%
OUTPUT
80%
TTHL
20%
Pulse Width, Setup, Hold Timing Diagram
Positive Edge Trigger
INPUT
VIH
VS
VIL
TSU
INPUT CP
VIH
VS
VIL
TH = HOLD TIME
TSU = SETUP TIME
TW = PULSE WIDTH
TW
TH
TW
GND0V
VOLTAGE LEVELS
PARAMETERHCTSUNITS
VCC4.50V
VIH3.00V
VS1.30V
VIL0V
GND0V
AC Load Circuit
DUTTEST
CL
CL = 50pF
RL = 500Ω
POINT
RL
Spec Number 518603
497
Page 9
Die Characteristics
DIE DIMENSIONS:
89 x 88 mils
2.25 x 2.24mm
METALLIZATION:
Type: SiAl
Metal Thickness: 11k
Å ± 1kÅ
GLASSIVATION:
Type: SiO
2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 10
5
A/cm
2
BOND PAD SIZE:
100µm x 100µm
4 mils x 4 mils
Metallization Mask Layout
K1
(2)
HCTS112MS
HCTS112MS
CP1
(1)
VCC
(16)
J1 (3)
S1 (4)
Q1 (5)
Q1 (6)
Q2 (7)
R1
(15)
(14)
R2
(13)
CP2
(12) K2
(11) J2
(8)
GND
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCTS112 is TA14441A.
(9)
Q2
(10)
S2
Spec Number 518603
498
Page 10
HCTS112MS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 727-9207
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
499
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Spec Number
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