Page 1
August 1995
HCS02MS
Radiation Hardened
Quad 2-Input NOR Gate
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD(Si)
2
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
/mg
-9
Errors/Bit-Day
(Typ)
12
• Dose Rate Survivability: >1 x 10
10
• Dose Rate Upset >10
RAD(Si)/s 20ns Pulse
Rads (Si)/s
• Latch-Up Free Under Any Conditions
o
• Military Temperature Range: -55
C to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCS02MS is a Radiation Hardened Quad 2-Input NOR
Gate. A low on both inputs forces the output to a High state.
The HCS02MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
Pinouts
A1
B1
Y2
A2
B2
GND
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
Y1
1
2
A1
3
B1
4
Y2
5
A2
6
B2
7
GND
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14
TOP VIEW
1Y1
2
3
4
5
6
7
14
VCC
13
Y4
12
B4
11
A4
10
Y3
9
B3
8
A3
14
13
12
11
10
9
8
VCC
Y4
B4
A4
Y3
B3
A3
The HCS02MS is supplied in a 14 lead Ceramic Flatpack Package
(K suffix) or a 14 lead SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
HCS02DMSR -55oC to +125oC Intersil Class
HCS02KMSR -55oC to +125oC Intersil Class
TEMPERATURE
RANGE
SCREENING
LEVEL PACKAGE
14 Lead SBDIP
S Equivalent
14 Lead Ceramic
S Equivalent
Flatpack
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
HCS02D/
Sample
HCS02K/
Sample
HCS02HMSR +25oC Die Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
+25oC Sample 14 Lead SBDIP
(2, 5, 8, 11)
+25oC Sample 14 Lead Ceramic
Flatpack
(3, 6, 9, 12)
1
TRUTH TABLE
INPUTS OUTPUTS
An Bn Yn
LLH
LHL
HLL
HHL
An
Yn
(1, 4, 10, 13)
Bn
DB NA
Spec Number 518744
File Number 2433.2
Page 2
Specifications HCS02MS
Absolute Maximum Ratings Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation..
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF). . . . . 100ns/V Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Thermal Resistance θ
SBDIP Package. . . . . . . . . . . . . . . . . . . . 74oC/W 24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 116oC/W 30oC/W
Maximum Package Power Dissipation at +125oC
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.66W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.43W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .8.6mW/oC
Input Low Voltage (VIL). . . . . . . . . . . . . . .0.0V to 30% of VCC Max.
Input High Voltage (VIH). . . . . . . . . . . . . . 70% of VCC to VCC Min.
JA
θ
JC
(NOTE 1)
PARAMETERS SYMBOL
Quiescent Current ICC VCC = 5.5V,
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low VOL VCC = 4.5V, VIH = 3.15V,
Output Voltage High VOH VCC = 4.5V, VIH = 3.15V,
Input Leakage
Current
IOL VCC = 4.5V, VIH = 4.5V,
IOH VCC = 4.5V, VIH = 4.5V,
IIN VCC = 5.5V, VIN = VCC or
CONDITIONS
VIN = VCC or GND
VOUT = 0.4V, VIL = 0V
VOUT = VCC -0.4V,
VIL = 0V
IOL = 50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
IOH = -50µA, VIL = 1.35V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
GND
GROUP
A SUB-
GROUPS TEMPERATURE
1 +25oC-10µA
2, 3 +125oC, -55oC - 200 µA
1 +25oC 4.8 - mA
2, 3 +125oC, -55oC 4.0 - mA
1 +25oC -4.8 - mA
2, 3 +125oC, -55oC -4.0 - mA
1, 2, 3 +25oC, +125oC, -55oC - 0.1 V
1, 2, 3 +25oC, +125oC, -55oC - 0.1 V
1, 2, 3 +25oC, +125oC, -55oC VCC
1, 2, 3 +25oC, +125oC, -55oC VCC
1 +25oC-±0.5 µA
2, 3 +125oC, -55oC-±5.0 µA
LIMITS
-V
-0.1
-V
-0.1
UNITSMIN MAX
Noise Immunity
Functional Test
NOTES:
1. All voltages reference to device GND.
2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
FN VCC = 4.5V,
VIH = 0.70(VCC),
VIL = 0.30(VCC) (Note 2)
7, 8A, 8B +25oC, +125oC, -55oC---
2
Spec Number 518744
Page 3
Specifications HCS02MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
(NOTES 1, 2)
PARAMETER SYMBOL
Input to Yn TPHL VCC = 4.5V 9 +25oC 2 18 ns
Input to Yn TPLH VCC = 4.5V 9 +25oC 2 20 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
Capacitance Power
Dissipation
Input Capacitance CIN VCC = 5.0V, f = 1MHz 1 +25oC - 10 pF
Output Transition
Time
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
CPD VCC = 5.0V, f = 1MHz 1 +25oC - 18 pF
TTHL
TTLH
CONDITIONS
VCC = 4.5V 1 +25oC - 15 ns
A SUB-
GROUPS TEMPERATURE
10, 11 +125oC, -55oC 2 20 ns
10, 11 +125oC, -55oC 2 22 ns
1 +125oC, -55oC - 26 pF
1 +125oC - 10 pF
1 +125oC - 22 ns
LIMITS
UNITSMIN MAX
LIMITS
UNITSMIN MAX
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
(NOTES 1, 2)
PARAMETERS SYMBOL
Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 0.2 mA
Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V +25oC 4.0 - mA
Output Current
(Source)
Output Voltage Low VOL VCC = 4.5V or 5.5V, VIH = 0.70(VCC),
Output Voltage High VOH VCC = 4.5V or 5.5V, VIH = 0.70(VCC),
Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC-±5 µA
Noise Immunity
Functional Test
Input to Yn TPHL VCC = 4.5V +25oC 2 20 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
IOH VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
VIL = 0.30(VCC) at 200K RAD, IOL = 50µA
VIL = 0.30(VCC) at 200K RAD, IOH = -50µA
FN VCC = 4.5V, VIH = 0.70(VCC),
VIL = 0.30(VCC) at 200K RAD, (Note 3)
TPLH VCC = 4.5V +25oC 2 22 ns
CONDITIONS TEMPERATURE
+25oC -4.0 - mA
+25oC - 0.1 V
+25oC VCC
+25oC ---
200K RAD LIMITS
UNITSMIN MAX
-V
-0.1
Spec Number 518744
3
Page 4
Specifications HCS02MS
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
PARAMETER
ICC 5 3µA
IOL/IOH 5 -15% of 0 Hour
TABLE 6. APPLICABLE SUBGROUPS
SUBGROUP DELTA LIMIT
GROUP A SUBGROUPS
COMFORMANCE GROUP MIL-STD-883 METHOD
Initial Test 100% 5004 1, 7, 9 1 (Note 2)
Interim Test 100% 5004 1, 7, 9, ∆ 1, ∆ (Note 2)
PDA 100% 5004 1, 7, ∆
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A (Note 1) Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆ 1, 2, 3, ∆ (Note 2)
Subgroup B6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 7, 9
NOTES:
1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised.
2. Table 5 parameters only.
TABLE 7. TOTAL DOSE IRRADIATION
TEST READ AND RECORD
CONFORMANCE
GROUPS METHOD
PRE RAD POST RAD PRE RAD POST RAD
TESTED RECORDED
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1)
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
Spec Number 518744
4
Page 5
Specifications HCS02MS
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN GROUND 1/2 VCC = 3V ± 0.5V VCC = 6V ± 0.5V
STATIC BURN-IN I TEST CONDITIONS (Note 1)
1, 4, 10, 13 2, 3, 5, 6, 7, 8, 9, 11, 12 - 14 - -
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
1, 4, 10, 13 7 - 2, 3, 5, 6, 8, 9, 11,
12, 14
DYNAMIC BURN-IN I TEST CONNECTIONS (Note 2)
- 7 1, 4, 10, 13 14 2, 3, 5, 6, 8, 9,
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ± 5% static burn-in.
2. Each Pin except VCC and GND will have a resistor of 1kΩ± 5% for dynamic burn-in.
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN GROUND VCC = 5V ± 0.5V
1, 4, 10, 13 7 2, 3, 5, 6, 8, 9, 11, 12, 14
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
50kHz 25kHz
--
11, 12
-
Spec Number 518744
5
Page 6
HCS02MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023
Sample - Wire Bond Pull Monitor, Method 2011
Sample - Die Shear Monitor, Method 2019 or 2027
100% Internal Visual Inspection, Method 2010, Condition A
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% PIND, Method 2020, Condition A
100% External Visual
100% Serialization
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
o
C min., Method 1015
+125
failures from subgroup 7.
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
100% Interim Electrical Test 1 (T1)
100% Delta Calculation (T0-T1)
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
o
C min., Method 1015
+125
100% Interim Electrical Test 2 (T2)
100% Delta Calculation (T0-T2)
100% PDA 1, Method 5004 (Notes 1and 2)
100% Dynamic Burn-In, Condition D, 240 hrs., +125
o
Equivalent, Method 1015
100% Interim Electrical Test 3 (T3)
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% Final Electrical Test
100% Fine/Gross Leak, Method 1014
100% Radiographic, Method 2012 (Note 3)
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
C or
Spec Number 518744
6
Page 7
HCS02MS
AC Timing Diagrams
VIH
VS
VIL
VOH
VOL
VOH
VOL
PARAMETER HCS UNITS
VCC 4.50 V
VIH 4.50 V
VS 2.25 V
INPUT
TPLH
VS
TTLH
20%
OUTPUT
80%
OUTPUT
FIGURE 1
AC VOLTAGE LEVELS
TPHL
80%
20%
TTHL
AC Load Circuit
DUT TEST
CL
CL = 50pF
RL = 500Ω
POINT
RL
FIGURE 2
VIL 0 V
GND 0 V
Spec Number 518744
7
Page 8
Die Characteristics
DIE DIMENSIONS:
87 x 88 mils
2.20mm x 2.24mm
METALLIZATION:
Type: AlSi
Metal Thickness: 11k
Å ± 1kÅ
GLASSIVATION:
Type: SiO
2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
<2.0 x 10
5
A/cm
2
BOND PAD SIZE:
100µm x 100µm
4 x 4 mils
Metallization Mask Layout
HCS02MS
HCS02MS
Y1 VCC Y4
(1) (14) (13)
A1 (2)
B1 (3)
Y2 (4)
A2 (5)
(6)
B2
(7)
GND
(8)
A3
(12) B4
(11) A4
(10) Y3
(9) B3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number 518744
8
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