This COMBO Driver for HDD application consists of Sensorless Spindle Driver and BTL type VCM
Driver.
Bipolar Process is applied and a “Soft Switching Circuit” for less commutation noise and a “Booster
Circuit” for smaller Saturation Voltage of Output Transistor are also implemented.
Features
• Soft Switching Driver
• Small Surface Mount Package: FP-48T (QFP48 Pin)
• Low thermal resistance: 30°C/W with 4 layer multi glass-epoxy board
• Low output saturation voltage
Spindle1.44 V Typ (@1.8 A)
VCM1.0 V Typ (@1.0 A)
Functions
• 2.2 A Max/3-phase motor driver
• 1.5 A Max BTL VCM Driver
• Auto retract
• Soft Switching Matrix
• Start up circuit
• Booster
• Speed Discriminator
• Internal Protector (OTSD, LVI)
• POR
• Power monitor
Page 2
HA13557AFH
Pin Arrangement
)
+
TAB
GND
VBST
VCMP
VCMN
BC2
BC1
GND
RS
RETON
RETPOW
Vpsv
LVI2
48 47 46 45 44 4342 41 40 393738
1
2
3
4
5
6
GND
TAB
7
GND
8
W
9
RNF
CT
10
11
12
V
13 14 15 16 17 1819 20 21 22 23 24
U
C-PUMP
R1
CLREF
Vpss
GND
TAB
GND
PCOMP
*NC : No internal connection
Please note that there is no isolation check between pin 34 and pin 35
at the testing of this IC.
(Top View)
OPIN(–)
VCTL
SS
V
LVI1
RESINH
OPIN(
COMM
DELAY
VREF1
36
COMPOUT
35
NC*
34
NC*
33
GAIN
32
VCMENAB
31
GND
TAB
30
GND
29
POR
28
SPNENAB
27
READY
26
CLOCK
25
CNTSEL
POLSEL
2
Page 3
HA13557AFH
Pin Description
Pin Number Pin NameFunction
1VBSTBoosted voltage output to realize the low output saturation voltage
2VCMPOutput terminal on VCM driver
3VCMNOutput terminal on VCM driver
4BC2To be attached the external capacitor for booster circuitry
5BC1ditto
6, TAB, 7GNDGround pins
8WW phase output terminal on spindle motor driver
9RNFSensing input for output current on spindle motor driver
10PCOMPTo be attached the external capacitor for phase compensation of spindle
motor driver
11CTTo be attached the center tap of the spindle motor for B-EMF sensing
12VV phase output terminal on spindle motor driver
13UU phase output terminal on spindle motor driver
14C-PUMPTo be attached the external integral constants for speed control of spindle
motor
15CLREFReference voltage input for current limiter of spindle motor driver
16R1To be attached the external resistor for setting up the oscillation frequency of
start-up circuitry and the gain of speed control loop of spindle motor driver
17VpssPower supply for spindle motor driver
18, TAB, 19 GNDGround pins
20V
21LVI1Sensing input for power monitor circuitry
22DELAYTo be attached the external capacitor to generate the delay time for power on
23COMMTo be attached the external capacitor for setting up the oscillation frequency
24POLSELTo be selected the input status corresponding to the pole number of spindle
25CNTSELTo select the count Number of Speed Discriminator
26CLOCKMaster clock input for this IC
27READYOutput of speed lock detector for spindle motor
28SPNENABTo select the status of spindle motor driver
29POROutput of power on reset signal for HDD system
30, TAB, 31 GNDGround pins
32VCMENABTo select the status of VCM driver
33GAINTo select the Transfer conductance gm of VCM driver
SS
Power supply for small signal block
reset signal
motor
3
Page 4
HA13557AFH
Pin Description (cont)
Pin Number Pin NameFunction
34NCNo function
35NCNo function
36COMPOUTComparator output to detect the direction of output current on VCM driver
37VREF1Regulated voltage output to be used as reference of peripheral ICs
38RESINHUsed for inhibiting the restart function of the spindle motor driver after power
down
39OPIN (+)Non inverted input of OP.Amp. to be used for filtering the signal on PWMOUT
40VCTLOP.Amp. output, this signal is used as control signal for VCM driver output
41OPIN (–)Inverted input of OP.Amp. to be used for filtering the signal on PWMOUT
42, TAB, 43 GNDGround pins
44LVI2Sensing input for power monitor circuitry
45VpsvPower supply for VCM driver
46RETPOWPower supply for retract circuitry
47RETONTo be attached the base terminal of external transistor for retracting
48RSSensing input for output current on VCM driver
4
Page 5
Block Diagram
HA13557AFH
RESINH
COMM
C103
C-PUMP
C2
C1
CLREF
R1b
SPNENAB
POLSEL
CLOCK
(5MHz Typ)
CNTSEL
READY
VCTL
OPIN(–)
OPIN(+)
Vref1
GAIN
VCM ENAB
C104
C105
R1
R1a
NC
NC
BC1
BC2
V
VSS (+5V)
V
SS
2017
38
23
C102
B-EMF
AMP.
START-UP
CIRCUIT
SOFT
SWITCHING
MATRIX
COMMUTATION
LOGIC
14
15
CHARGE
PUMP
CURRENT
CONTROL
16
28
24
(D1)
SPEED DISCRI.
26
1/32
(CNT)
25
27
SPEED
READY
V
BST
40
–
41
39
37
34
35
+
OPAMP.
Vref1
(=4.6V)
OTSD
+
VCM
DRIVER
–
33
32
5
4
1
BST
BOOSTER
Vss
(+5V)
V
BST
Vss
21 4422
LVI1
R101
POWER
MONITOR
LVI2
R103
Vps
R102R104
Vps
(+12V)
POR
Delay
DELAY
C106
V
BST
Vpss
SPINDLE
DRIVER
RETRACT
DRIVER
P
N
COMPARATOR
Vps(+12V)
U
V
W
PCOMP
Vpsv
RETPOW
RETON
VCMP
VCMN
–
+
GND
TAB
6, 7, 18, 19, 30,
31, 42, 43
C101
CT
11
13
U
12
V
8
W
9
10
45
46
47
2
3
48
RS
COMP
36
OUT
R105
29
POR
(L:RESET)
D2
D3
D4
R
C110
C111
R112
Qret2
C
R
NF
Qret1
C112
X
X
Vss(+5V)
C109
R113
R109
R
S
R
L
R111
R110
D1
5
Page 6
HA13557AFH
Truth Table
Table 1Truth Table (1)
SPNENABSpindle Driver
HON
OpenCut off
LBraking
Table 2Truth Table (2)
VCMENABVCM Driver
HON
LCut off
Table 3Truth Table (3)
OTSDSpindle DriverVCM DriverRetract DriverPOR
not ActiveSee table 1See table 2Cut offX
ActiveCut offCut offONL
Table 4Truth Table (4)
POLSEL(D1)Comment
H—Test Mode
Open1/12for 8 poles motor
L1/18for 12 poles motor
Table 5Truth Table (5)
Rotation Speed
CNTSELCNT
H26053,600 rpm
Open20844,500 rpm
L17365,400 rpm
(at CLOCK = 5 MHz)
6
Page 7
HA13557AFH
Table 6Truth Table (6)
RESINHSpindle Driver
HInhibiting the restart after power down
LNot inhibiting the restart after power down
Table 7Truth Table (7)
GAINVCM Driver
HHigh Gain Mode
LLow Gain Mode
7
Page 8
HA13557AFH
Timing Chart
1. Power on reset (1)
Vsd
Vps and
V
SS
Vhys
t
POR
1.0V
MAX
0
Note:1.How to determine the threshold voltage Vsd and the delay time t
external components table.
t
DLY
both are shown in the
DLY
t
8
Page 9
2. Power on reset (2)
HA13557AFH
VPS or
V
SS
POR
Spindle
Driver
VCM
Driver
Retract
Driver
Note:2.Retract driver need B-EMF voltage or another power supply.
ON
OFF
ON
OFF
t
por
t
por
<1µs<1µs
Retract
9
Page 10
HA13557AFH
,
3. Motor start-up seaquence
(a) Timing chart of start-up seaquence
SPNENAB
Open
No
Rotation
Speed
Synchronous
Driving
Driving by
B-EMF
sensing
0
Internal
READY
READY
(Pin 27)
Switching
t
delay
2
*
Note *1. Speed lock detection range ∆No is as follows.
∆No=1.2% when CNTSEL=H
=1.5% when CNTSEL=Open
=1.8% when CNTSEL=L
*2. READY output goes to High, if the rotation speed error keeps to be less than
∆No longer time than tdelay.
tdelay=[ms]
250 • 10
fclk [Hz]
7
*3. The turning point of driving mode from switching synchronize to the turning
point of READY output from Low to High.
Soft Switching*
3
t
No+∆No*
No–∆No*
1
1
(b) Retry circuitry for misstart-up
Motor
on
Synchronous
driving
Driving by
B-EMF
sensing
(not stop)
Motor
stop
detector
(Motor stop)
(Motor off)
The HA13557FH has the motor stop detector as shown hatching block. This function is monitoring
the situation of the motor while the motor is running by B-EMF sensing. If the motor will be caused a
misstarting up, the motor will be automatically restarted within 200 ms after the motor stopped. This
function increase the reliability for the motor starting up.
10
Page 11
4. Braking & Shut down the Spindle Driver
HA13557AFH
Open
Open
SPNENAB
> 20µs
ONCUT OFFBRAKINGCUT OFF
Note:The SPNENAB should be selected the open state after braking to reduce the supply current from
Vps and VSS.
5. Start-up of the Spindle motor
Open
SPNENAB
COMM
GND
SOURCE
I
U
0
SINK
t
(see External Components Table)
COMM
Vth1
Vth2
SOURCE
I
V
SOURCE
I
W
0
SINK
0
SINK
COMM4TCOMM4TCOMM4TCOMM4TCOMM4TCOMM6TCOMM8TCOMM
2T
not detecting the B-EMFdetecting the B-EMF
COMM
10T
COMM
12T
COMM
14T
COMM
16T
Synchronous Driving for motor start up
COMM
Driving by
B-EMF sensing
16T
11
Page 12
HA13557AFH
6. Acceleration and Running the spindle motor
+
U
BEMF
V
BEMF
W
BEMF
(1) Acceleration(switching mode)
SOURCE
Iu
SOURCE
Iv
SOURCE
Iw
0
–
+
0
–
+
0
–
0
SINK
0
SINK
0
SINK
(2) Running (soft switching mode)
SOURCE
Iu
SOURCE
Iv
SOURCE
Iw
0
SINK
0
SINK
0
SINK
12
Page 13
Application
PWMIN
V
SS
(+5V)
R101
R102
R8
R7
C104
C105
C103
C2R2
R3
R4
R105
R5
C5
C3
C102
R1aR1b
C1
C106
5
BC1
4
BC2
1
VBST
23
COMM
15
CLREF
16
14
24
25
27
26
28
32
33
38
37
41
HA13557AFH
R1
C-PUMP
POLSEL
CNTSEL
READY
CLOCK
SPNENAB
VCMENAB
GAIN
RESINH
VREF1
OPIN(–)
R6
40
VCTL
39
OPIN(+)
C4
36
COMPOUT
20
V
SS
29
POR
22
DELAY
GND
6 7 18 19 30 31 42 43 TAB
Vpss
CT
W
RNF
PCOMP
Vpsv
RETPOW
RETON
VCMP
VCMN
RS
LVl2
LVl1
HA13557AFH
V
PS
(+12V)
17
C101
11
D2
13
U
12
V
D3
8
C
R
R
C109
Qret1
X
X
NF
D4
R109
C112
R113
Qret3
D1
R
S
R103
R104
R111
RL
9
10
45
46
47
2
3
48
44
21
C110
C111
R112
Qret2
R110
13
Page 14
HA13557AFH
External Components
Parts No.Recommended ValuePurposeNote
R1a(R1a + R1b) ≥ 10 kΩV/I converter1, 4, 6
R1b(R1a + R1b) ≥ 10 kΩ
R2—Integral constant3
R3 to R8—PWM filter9
R101, R102—Setting of LVI1 voltage7
R103, R104—Setting of LVI2 voltage7
R1055.6 kΩPull up
R109, R110(R109 + R110) ≥ 10 kΩRetout voltage adjust
R111, R112, R113—Retract Driver
RS1.0 ΩCurrent sensing for VCM Driver10
Rnf—Current sensing for Spindle Driver1
R
X
C1, C2—Integral constant3
C3 to C6—PWM filter9
C
X
C101≥ 0.1 µFPower supply by passing
C102≥ 0.1 µFPower supply by passing
C103—Oscillation for start-up6
C1040.22 µFfor booster
C1052.2 µFfor booster
C106≤ 0.33 µFDelay for POR8
C109≥ 0.1 µFPower supply by passing
C110, C1110.22 µFPhase compensation
C112—Phase compensation for Retract
Qret1, Qret2, Qret3—Retract Driver12
D1TBDPrevent of counter current
D2, D3, D4Si • Diodefor rectification
—Reduction for gain peaking11
—Reduction for gain peaking11
14
Page 15
HA13557AFH
Notes: 1. Output maximum current on spindle motor driver Ispnmax is determined by following equation.
Ispnmax =[A]•
R1b
R1a + R1b
V
R1
R
NF
(1)
where, V
: Reference Voltage on Pin 16 [V] (= 1.17)
R1
2. Input clock frequency fclk on pin 26 is determined by following equation.
3. Integral constants R2, C1 and C2 can be designed as follows.
1
ω
=[rad/s]• 2 • π •
O
10
R2 =[Ω]•
C1 =[F]
1
9.55
10 • ω
N
O
60
Rnf • J • ωO • NO • (R1a + R1b)
V
• KT • Gctl
R1
1
• R2
O
(2)
(3)
(4)
(5)
C2 = 10 • C1[F]
where, J:Moment of inertia [kg•cm•s
K
:Torque constant [kg•cm/A]
T
2
]
(6)
Gctl: Current control amp gain from pin 14 to pin 9 (= 0.794)
4. It is notice that rotation speed error Nerror is caused by leak current Icer2 on pin 14 and this
error depend on R1a and R1b as following equation.
Nerror = Icer2 •[%]• 100
(R1a + R1b)
VR1
(7)
where, Icer2: Ieak current on pin 14 [A]
5. Oscillation period t
on pin 23 which period determine the start up characteristics, is should be
COMM
chosen as following equation.
t
COMM
1
=•[s]to
8
P • K
• Ispnmax
T
J
1
•
4
P • K
J
• Ispnmax
T
(8)
15
Page 16
HA13557AFH
6. The capacitor C103 on pin 23 can be determined by t
C103 =•[F]
1
4
where, Vth
Vth
VR1
R1a + R1b
: Threshold voltage on start up circuit [V] (= 2.0)
H
: Threshold voltage on start up circuit [V] (= 0.5)
L
t
COMM
•
VthH – Vth
L
and following equation.
COMM
(9)
7. LVI operatig voltage Vsd1, Vsd2 and its hysteresis voltage Vhys1, Vhys2 can be determined by
following equations.
for V
SS
Vsd1 = 1 + • Vth4[V]
Vhys1 = 1 + • Vhyspm[V]
R101
R102
R101
R102
(10)
(11)
for Vps
Vsd2 = 1 + • Vth3[V]
Vhys2 = 1 + • Vhyspm[V]
R103
R104
R103
R104
(12)
(13)
where, Vth3, Vth4: Threshold voltage on pin 21 and pin 44 [V] (= 1.39)
Vhyspm:Hysteresis voltage on pin 21 and pin 44 [mV] (= 40)
Shut down voltage Vsd1, Vsd2 can be designed by the following range.
Vsd1 ≥ 4.25 [V], Vsd2 ≥ 10 [V]
8. The delay time t
C106 • Vth5
t
=[s]
DLY
of POR for power on reset is determined as follows.
DLY
I
CH3
(14)
16
where, Vth5: Threshold voltage on pin 22 [V] (= 1.4)
I
:Charge current on pin 22 [µA] (= 6)
CH3
9. The differential voltage (Vctl – V
) using for control of VCM driver depend on PWMDAC input
REF1
PWMIN as follows.
Vctl – V
where, D
REF1
– 50
= 2 • V
PWM
H
FLT(S)
REF1
:Duty cycle on PWMIN [%]
:Normalized transfer function from PWMIN to pin 40 (Vctl) as shown in
PWM
•
100
R6
•• H
R5
FLT
(s)
D
equation (17)
To be satisfied with above equation (15), it is notice that the ratio of R6 to R7 must be choosen
If you choose the R// << R3, then equation (17) can be simplified as following equation.
H
(s) =
FLT
1 +
1
•
s
1 +2 • ζ •
ω
O
1
s
ωn
where,
=
O
1
C5 • R//
ω
(17)
(18)
(19)
(20)
ωn =
1
C3 • C4 • R3 • R4
C4 • (R3 + R4) – C3 • R3 •
ζ =
R6
R5
2 • C3 • C4 • R3 • R4
10.The relationship between the output current Ivcm and the input voltage (Vctl – V
driver is as follows.
Ivcm(s) = Vctl – V
REF1
• Kvcm •
1
Rs
• Hvcm(s)
where, Vctl:Input control voltage for VCM driver on pin 40 [V]
:Reference voltage on pin 37 [V] (= 4.6)
V
REF1
Kvcm:DC gain of VCM driver
(= 1.74 for High gain mode)
(= 0.44 for Low gain mode)
Hvcm(s): Transfer function of VCM driver as shown following equation
VCM
1
ω
s
VCM
2
s
•
ω
VCM
+
Hvcm(s) =
1 + 2 • ζ
where,
ω
VCM
=ωP•
Rs
Lm
) on VCM
REF1
(21)
(22)
(23)
(24)
(25)
17
Page 18
HA13557AFH
q
)
ζ
=•1 +
VCM
1
1
2
R
Rs
L
•
ω
Rs
•
Lm
P
(26)
where, ωp: Bandwidth of internal power amplifiers for VCM driver [rad/s]
6
(= 3•π•10
)
Lm: Inductance of the VCM coil [H]
R
: Resistance of the VCM coil [Ω]
L
and from above equations the -3 dB bandwidth f
ω
f
VCMC
VCM
=•1 – 2 • ζ
2 • π
VCM
2
+2 • ζ
of VCM driver is as following equation.
VCMC
2
– 12+ 1
VCM
(27)
11.The frequency response of VCM driver maybe have a gain peaking because of the resonation of
the motor coil impedance. If you want to tune up for this characteristics, you can reduce the
peaking by additional snubber circuit R
and CX as follows.
X
BTL Driver
+
–
R3
N
R
X
Coil
C
X
RS
R
S
1/2 V
PS
R3
–
+
P
Figure 1 VCM Driver Block Diagram
18
20
10
Normal
0
I
O
(dB)
–10
= 0.22µF
C
X
RX = 560Ω
–20
1001k10k100k
uency (Hz
Fre
(for example) RL = 14.7 Ω, RS = 1 Ω, L = 1.7 mH, Gain = L
Page 19
12.The Qret3 collector voltage Vret is determined by
Vret = VRT (
.
Iret =
.
R109
R110
Vret – V
+ 1)
(D1) – Vsat
F
RL + Rs
(Vretpow ≥ VRT (+ 1))
VL
where, Vretpow:Applied voltage on pin 46 [V]
:Reference voltage of Retract (toward voltage of Qret2) [V]
V
RT
V
(D1):Foward voltage of D1 [V]
F
Vsat
:Saturation voltage on pin 3 at retracting [V]
VL
(See electrical characteristics)
HA13557AFH
R109
R110
(28)
19
Page 20
HA13557AFH
10
Absolute Maximum Ratings (Ta = 25°C)
ItemSymbolRatingUnitNotes
Power supply voltageVps+15V1
Signal supply voltageV
Input voltageV
SS
IN
Output current-SpindleIospn (Peak)2.2A
Iospn (DC)1.8A
Output current-VCMIovcm (Peak)1.5A
Iovcm (DC)1.0A
Power dissipationP
T
Junction temperatureTj+150°C5, 6
Storage temperatureTstg–55 to +125°C
Notes: 1. Operating voltage range is 10.2 V to 13.8 V.
2. Operating voltage range is 4.25 V to 5.75 V.
3. Applied to Pin 24, 25, 26, 28, 32, 33 and pin 38
4. Operating junction temperature range is Tjop = 0°C to +125°C.
5. ASO of upper and lower power transistor are shown below.
Operating locus must be within the ASO.
6. The OTSD (Over Temperature Shut Down) function is built in this IC to avoid same damages by
over heat of this chip. However, please note that if the junction temperature of this IC becomes
higher than the operating maximum junction temperature (Tjopmax = 125°C), the reliability of this
IC often goes down.
7. Thermal resistance: θj-a ≤ 30°C/W with 4 layer multi glass-epoxy board
2. Variations of threshold voltage Vth3 and Vth4 depending on the power supply V
figure 4.
V
OL2
V
OL3
Icer5——±10µAVpor = 7 V
Vth5—1.4±5%V22
CH3
I
DIS3
Tsd125150—°C1
——0.4VIO = 1 mA29
——0.4VIO = 1 mA
V
= Vps = 1.0 V
SS
—6 ±25% µA
40——mA
Applicable
PinsNote
are shown in
SS
1.41
1.40
Test condition of Vth3
1.39
1.38
1.37
1.36
1.35
Threshold voltage Vth3, Vth4 (V)
1.34
1.33
3.8
Test condition of Vth4
4.05.04.2 4.4 4.6 4.85.2 5.4
Power supply V
Figure 4
SS
(V)
5.6 5.8
6.0
26
Page 27
Package Dimensions
17.2 ± 0.2
36
37
17.2 ± 0.2
48
1
2.9252.925
0.3 ± 0.05
0.825
14
4.85
0.13
0.1
25
2.425
M
12
13
24
0.65
2.425
2.7
0.1 ± 0.1
4.85
2.9252.925
3.05 Max
0.17 ± 0.05
0.825
Hitachi code
EIAJ code
JEDEC code
HA13557AFH
Unit: mm
1.6
0 – 10°
0.8 ± 0.3
FP-48T
—
—
27
Page 28
Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URLNorthAmerica : http:semiconductor.hitachi.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Europe: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore): http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan): http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong): http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan: http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
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