Datasheet GS7032-CVM, GS7032-CTM Datasheet (Gennum Corporation)

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

Revision Date: January 2001 Document No. 14583 - 00

PRELIMINARY DATA SHEET

GS7032

FEATURES

FEATURESFEATURES

FEATURES

• SMPTE 259M-C compliant (270Mb/s)

• serializes 8-bit or 10-bit data

• minimal external components (no loop filter
component s required)

• isolated, dual-output, adjustab le cab le driver

• 3.3V and 5.0V CMOS/TTL compatible inputs

• lock detect indication

• SMPTE scramble and NRZI coding bypass option

• EDH support with GS9001, GS9021 or EDH FPGA code

APPLICATION

APPLICATIONAPPLICATION

APPLICATION

SMPTE 259M-C parallel to serial interfaces for video
cameras, VTRs, signal generators; Generic parallel to serial
conversion.

DES C RIPTI ON

DES C RIPTI ONDESCRIPTION

DES C RIPTI ON

The GS7032 is designed to encode and serialize SMPTE
125M bit parallel digital video signals as well as other 8-bit
or 10-bit parallel formats. This device performs the following
functions:

•sync detection

• parallel to serial conversion

• data scrambling (using the X

9

+ X4 + 1 algorithm)

• 10x parall el cl o ck mult i p li cat i on

• conversio n o f NRZ to NRZ I se ri al da ta
The GS7032 features 270M/bs data rate with a single VCO

resistor. Other features include a lock detect output, NRZI
encoding and SMPTE scrambler bypass, a sync detect
disable, and an isolated dual output cable driver suitable
for driving 75Ω loads.

BLOCK DIAGRAM

BLOCK DIAGRAM BLOCK DIAGRAM

BLOCK DIAGRAM

ORDERING INFORM ATION

ORDERING INFORM ATIONORDERING INFORM ATION

ORDERING INFORM ATION

PART NUMBER PACKAGE TEMPERATURE

GS7032 - CVM 44 pin TQFP 0°C to 70°C
GS7032 - CTM 44 pin TQFP Tape 0°C to 70°C

LOCK
DETECT
(LOCK DET)

SERIAL
DIGITAL
OUTPUTS

PARALLEL CLOCK

INPUT (PCLKIN)

P

LOAD

S

CLK

S

CLK

/10

LOOP BANDWIDTH

CONTROL (LBWC)

R

VCO+RVCO-

MUTE

RESET

RESET

SYNC DETECT DISABLE (SYNC DIS)

BYPASS

BYPASS

PARALLEL

to SERIAL

CONVERTER

&

NRZ to NRZI

DATA

IN

(PD0-PD9)

10

10

8

INPUT

LATCH

2

10

SYNC

DETECT

SMPTE

SCRAMBLER

PLL

SDO0
SDO0

352/,1;

™

GS70 32

GS70 32 GS70 32

GS70 32

Digital Video Serializ er

Digital Video Serializ erDigital Video Serializ er

Digital Video Serializ er

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GS7032

ABSOLUTE MAXIMUM RATINGS

ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage (VS = VCC-VEE)5.5V
Input Voltage Range (any input) V

EE<VIN<VCC

DC Input Current (any one input) 5mA
Power Dissipation (V

CC

= 5.25V) 1200mW

θ

j-a

42.5°C/W

θ

j-c

6.4°C/W

Maximum Die Temperature 125°C
Operating Temperature Range 0°C

≤

TA ≤ 70°C

Storage Temperature Range -65°C

≤

TS ≤ 150°C

Lead Temperature (soldering, 10 sec) 260°C

DC ELECTRI C AL CHARACTE RISTICS

DC ELECTRI C AL CHARACTE RISTICSDC ELECTRI C AL CHARACTE RISTICS

DC ELECTRI C AL CHARACTE RISTICS

VCC = 5V, VEE = 0V, TA =0°C to 70°C unless otherwi se sp ec ifi ed.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

TEST

LEVEL

Positive Supply Voltage V

CC

Operating Range 4.75 5.00 5.2 5 V 1

Power (System Power) P V

CC

= 5.0V, T = 25°C (2 outputs) - 550 - mW 7,3

Supply Current

Ι

CC

VCC = 5.25V (2 outputs) - - 160 mA 1
V

CC

= 5.0V, T = 25°C (2 outputs) - 110 - mA 7

Data & Clock Inputs
(PD[9:0] PCLKIN)
SYNC DIS

V

IH

Logic Input High (wrt VEE)2.4--V 1

V

IL

Logic Input Low (wrt VEE)--0.8V

Ι

L

Input Current - - 8.0 µA

Logic Input Levels
(Bypass, RESET)

V

IH

Logic Input High (wrt to VEE)2.4--V 1

V

IL

Logic Input Low (wrt to VEE)--0.8V

Ι

L

Input Current - - 5.0 µA

Lock Detect Output V

OL

Sinking 500µA - - 0.4 V 1

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulati ons.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/charac terization data of similar product.

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GS7032

AC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICSAC ELECTRICAL CHARACTERISTICS

AC ELECTRICAL CHARACTERISTICS

VCC = 5V, VEE = 0V, TA =0°C to 70°C unless otherwi se sp ec ifi ed.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

TEST

LEVEL

Serial Data Bit Rate BR

SDO

R

VCO

= 374Ω, 270Mb/s - - - Mb/s SMPTE

259M-C

1

Serial Data Outputs Signal
Swing

V

SDO

R

LOAD

= 37.5Ω, R

SET

= 54.9

Ω

740 800 860 mVp-p 1

SD Rise/Fall Times t

r

, t

f

20% - 80% 400 - 700 ps 7

SD Overshoot/Undershoot - - 7 % 1 7
Output Return Loss O

RL

at 270MHz - - - dB 1 7

Lock Time t

LOCK

Worst case - - 5 ms 6

Min Loop Bandwidth BW

MIN

LBWC = Grounded : BW

MIN

- 220 - kHz 7

Typical Loop Bandwidth BW

TYP

LBWC = Floating : BW

MIN

- 500 - kHz 7

Max Loop Bandwidth BW

MAX

LBWC = VCC : 10 BW

MIN

-1.7-MHz 7

Intrinsic Jitter (6

σ

)LBWC = V

CC

(270Mb/s) - - - UI

Data & Clock Inputs
(PD[9:0] PCLKIN)

t

SU

Setup Time at 25°C2.5--ns 1

t

H

Hold Time at 25°C2.0--ns 1

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges using correlated test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulati ons.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/charac terization data of similar product.

NOTES

1. Depends on PCB layout.

10

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GS7032

PIN CONNECTIONS

PIN CONNECTIONSPIN CONNECTIONS

PIN CONNECTIONS

GS7032

TOP VIEW

44 43 42 41 40 39 38 37 36 35 34

R

VCO+

LF+

V

EE

R

VCO-

LF-

V

CC1

LBWC

NC

SYNC DIS

V

EE

V

EE1

33
32
31
30
29
28
27
26
25
24
23

NC
BYPASS
NC
V

EE

NC

NC

V

EE

SDO

SDO

V

EE

PD9
PD8
PD7
PD6
PD5
PD4
PD3

PD2
PD1
PD0

PCLKIN

1
2
3
4
5
6
7
8
9
10
11

12 13 14 15 16 17 18 19 20 21 22

V

CC2

V

EE

2

RSV2

R

SET

RSV1

NC

NC

LOCK

V

EE3

NC

V

CC3

RESET

PIN DESCRIPTIONS

PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

1-10 PD9 - PD0 I CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is t he M SB.

11 PCLK IN I CMOS or TTL compatible parallel clock input.
12 V

EE3

- Most negative power supply connection for parallel data and clock inputs.

13 V

CC3

- Most positive power supply connection for parallel data and clock inputs.

14 RSV2 I Reserved pin. Do not connect.

15, 19, 21, 27,

28, 30, 32, 37

NC I No connect.

16 RSV1 I Reserved pin. Always connect to V

CC

.

17 V

CC2

- Most positive power supply connection for internal logic and digital circuits.

18 V

EE2

- Most negative power supply connection for internal logic and digital circuits.
20 LOCK O TTL level which is high when the internal PLL is locked.
22 R

SET

I External resistor used to set the data output amplitude for SDO and SDO.

23, 26, 29 V

EE

- Most negative power supply connection for shielding (not connected).

24, 25 SDO

, SDO O Primary, current mode, 75Ω cable driving output (inverse and true)

31 BYPASS I When high, the SMPTE Scrambler and NRZ encoder are bypassed.

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GS7032

33 RESET I Resets the scrambler when asserted.
34 V

CC1

- Most positive power supply connection for analog circuits.
35 V

EE1

- Most negative power supply connection for analog circuits.

36, 38 R

VCO

+, R

VCO

- I Differential VCO current setting resistor that s ets t he VCO frequency.

39, 43 V

EE

- Most negative power supply connection (substrate).
40 LBWC I TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest

jitter. If the pin i s set to ground the loop bandwidth is BW

MIN

. If the pin is left floating, the

loop bandwidth is approximately 3 BW

MIN

, if the pin is tied to VCC the loop bandwidth is

approximately10 BW

MIN

41, 42 LF+, LF- I Differential loop filter pins to optimize loop transfer per formance at low loop bandwidths

(NC if not used).

44 SYNC DIS I Sync detect disable. Logic high disables sync detection. Logic low al l ows 8 bit operation

by mapping 000-003 to 000 and 3FC-3FF to 3FF.

PIN DESCRIPTIONS

PIN DESCRIPTIONSPIN DESCRIPTIONS

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

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GS7032

TYPICAL PERFORMANCE CURVES

TYPICAL PERFORMANCE CURVESTYPICAL PERFORMANCE CURVES

TYPICAL PERFORMANCE CURVES

(VS = 5V, TA = 25°C unless otherwise shown. Guard band tested to 70°C only.)

Fig. 1 Rise/Fall Times vs. Temperature

Fig. 2 Supply Current vs. Temperature (SDO ON)

Fig. 3a Output Swing vs. Temperature (1000mV)

Fig. 3b Output Swing vs. Temperature (800mV)

Fig. 4 Waveforms

Fig. 5 Timing Diagram

5.25 FALL

4.75 RISE

5.0 RISE

5.0 FALL

5.25 RISE

4.75 FALL

020406080

500

490

480

470

460

450

440

430

420

RISE / FALL TIME (ps)

TEMPERATURE (˚C)

4.75

5.0

5.25

020406080

155

150

145

140

135

130

125

CURRENT (mA)

TEMPERATURE (˚C)

4.75

5.0

5.25

020406080

1.01

1.005

1.000

0.995

0.99

OUTPUT SWING (V)

TEMPERATURE (˚C)

4.75

5.0

5.25

020406080

0.8075

0.805

0.8025

0.800

0.7975

0.795

0.7925

OUTPUT SWING (V)

TEMPERATURE (˚C)

t

SU

t

HOLD

t

CLKL

=

t

CLKH

PARALLEL

CLOCK

PLCK

50%

PARALLEL

DATA

PDn

E
A
V

S
A
V

ACTIVE

VIDEO

4:2:2
DATA

STREAM

E
A
V

S
A
V

H

BLNK

H

BLNK

SYNC
DETECT

SYNC
DETECT

XXX 3FF 000 000 XXX ••• ••• XXX 3FF 000 000 XXX •••

PCLK IN

PDN

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GS7032

Fig. 6 Output Jitter vs. LBWC

Fig. 7 Output Eye Diagram (270Mb/s)

DETAILED DESCRIPTION

DETAILED DESCRIPTIONDETAILED DESCRIPTION

DETAILED DESCRIPTION

The GS7032 Serializer is a bipolar integrated circuit used to
convert parallel data into a serial format according to the
SMPTE 259M-C standard. The device encodes both 8-bit
and 10-bit TTL-compatible parallel signals producing serial
data rates at 270Mb/s. It operates from a single 5V supply
and is packaged in a 44 pin TQFP.

Functional blocks within the device include the following:

• input latches

• sync detecto r

• parallel to serial converter

• SMPTE scrambler

• NRZ to NRZI converter

• internal cable driver

• PLL for 10x parallel clock multiplication

• lock detect

The parallel data (PD0-PD9) and parallel clock (PCLKIN)
are applied via pins 1 through 11 respectively.

1. SYNC DETECTOR

The Sync Detector looks for the reserved words used in the
TRS-ID sync word. The reserved words are 000-003 and
3FC-3FF in 10-bit hexadecimal, or 00 and FF in 8-bit
hexadecimal. When the occurrence of either all zeros or all
ones at inputs PD2-PD9 are detected, the lower two bits
PD0 and PD1 are forced to zeros or ones, respectively. This
makes the system compatible with 8-bit or 10-bit data.

For non-SMPTE standard parallel data, the Sync Detector
can be disabled with a logic input, Sync Detect Disable (pin

44).

2. SCRAMBLER

The Scrambler is a linear feedback shift register used to
pseudo-randomize the incoming serial data according to
the fixed polynomial (X

9+X4

+1). This minimizes the DC
component in the output serial data stream. The NRZ to
NRZI converter uses another polynomial (X+1) to convert a
long sequence of ones to a series of transitions, minimizing
polarity effects. These functions can be disabled by setting
BYPASS high (pin 31).

3. PHASE LOCKED LOOP

The PLL performs parallel clock multiplication and provides
the timing signal for the serializer. It is composed of a
phase/frequency detector (with no dead zone), charge
pump, VCO

,

a divide-by-ten counter, and a divide by two

counter.
The phase/frequency detector allows a wider capture range

and faster lock time than can be achieved with a phase
discriminator alone. The discrimination of frequency also
eliminates harmonic locking. With this type of discriminator,
the PLL can be over-damped for good stability without
sacrificing lock time.

The charge pump delivers a 'charge packet' to the loop
filter which is proportional to the system phase error.
Internal voltage clamps are used to constrain the loop filter
voltage between approximately 1.8 and 3.4 volts.

The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PCB noise and
precise control of the VCO centre frequency. The VCO has
a pull range of ±15% about the centre frequency. The single
external resistor, R

VCO

, sets the VCO frequency.

GROUNDED FLOATING V

CC

600

500

400

300

200

100

0

JITTER p-p (ps)

LOOP BANDWIDTH CONTROL (LBWC)

(270Mb/s)

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GS7032

4. VCO CENTRE FREQUENCY SELECTION

The recommended R

VCO

value for auto rate SMPTE 259M-C
applicatio ns ( 270 Mb/s ) is 3 74Ω (see the Typical Application
Circuit).

The VCO and an internal divider generate the PLL clock.

5. LOCK DETECT OUTPUT

The Lock Detect output is available from pin 20 and is HIGH
when the lo op is locked. Wh en the loop is no t locked, the
lock detect circuit mutes the serial data outputs.

6. SERIAL OUTPUTS

The true and complement serial data, SDO and SDO, are
available from pins 24 and 25. These outputs will drive two
75Ω co-axial cables with SMPTE level serial digital video
signals.

R

SET

calculati on :

where R

LOAD

= R

PULL-UP

|| Z

O

TYPICAL APPLICATION CIRCUIT

TYPICAL APPLICATION CIRCUITTYPICAL APPLICATION CIRCUIT

TYPICAL APPLICATION CIRCUIT

R

SET

1.154 R

LOAD

×

V

SDO

---------------------------------------=

33
32
31
30
29
28
27
26
25
24
23

1
2
3
4
5
6
7
8

9
10
11

GS7032

V

EE3VCC3

RSV2NCRSV1

V

CC2VEE2

NC

LOCKNCR

SET

SYNC_DIS

V

EE

LF-

LF+

LBWC

V

EE

R

VCO

NC

R

VCO+

V

EE1

V

CC1

RESET

NC

BYPASS

NC

V

EE

NC
NC

V

EE

SDO
SDO

V

EE

PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLKIN

V

CC

J3

J4

V

CC

V

CC

V

CC

V

CC

V

CC

374

100n

L

R

L

R

1µ

1µ

75

75

100n

54.9

220

J1

LBWC

100n

100n

10k

PARALLEL
CLOCK
INPUT

PARALLEL
DATA
INPUTS

L = 8.2nH
R = 75Ω

LOCK

All resistors on ohms,
all capacitors in farads,
unless otherwise stated.

12 13 14 15 16 17 18 19 20 21 22

44 43 42 41 40 39 38 37 36 35 34

RESET

V

CC

14583 - 00

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GENNUM CORPORATION

MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. [phone] Fax. [phone]

SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5

GENNUM JAPAN CORPORAT ION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. [phone] Fax. [phone]

GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. [phone] Fax [phone]

Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.

© Copyright January 2001 Gennum Corporation. All rights reserved. Printed in Canada.

GS7032

PACKAGE DIMENSIONS

PACKAGE DIMENSIONSPACKAGE DIMENSIONS

PACKAGE DIMENSIONS

10.00

12.00

10.00

0.80

0.30

12.00

0.20 MAX
RADIUS

0.08 MIN.
RADIUS

0.60
±0.15

0.20 MIN

12˚ TYP

12˚ TYP

1.00

0.10

1.10

0.127

7˚ MAX
0˚ MIN

0 MIN

PIN 1

0.20 MIN

All dimensions in millimetres

44 pin TQFP

REVISION NOTES:

New document.

For latest product information, visit www.gennum.com.

DOCUMENT IDENTIFICATION

PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change.

CAUTION

ELECTROSTATIC

SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE

EXCEPT AT A STATIC-F REE WORKSTATION