ISO9001
ISO9001ISO9001
ISO9001
Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
I
DD
f
XTAL
= 13.5MHz; CL = 10pF 20 mA
Voltage Controlled Crystal Oscillator - VDD=5.0V
Crystal Loading Capacitance C
L(xtal)
As seen by a crystal connected to XIN and
XOUT ( @ V
XTUNE
= 1.65V)
14 pF
Crystal Resonator Motional Capacitance C
1(xtal)
AT cut 25 fF
VCXO Tuning Range
f
XTAL
= 13.5MHz; C
L(xtal)
= 14pF; C
1(xtal)
= 25fF
300 ppm
VCXO Tuning Characteristic
Note: positive ∆F for positive ∆V
100 ppm/V
Crystal Drive Level
R
XTAL
=20Ω; C
L(xtal)
= 14pF
200 uW
Clock Outputs (CLKA, CLKB) - VDDO=3.3V
High-Level Output Source Current * I
OH
VO = 2.0V -40 mA
Low-Level Output Sink Current * I
OL
VO = 0.4V 17 mA
z
OH
VO = 0.1VDD; output driving high 25
Output Impedance *
z
OL
VO = 0.1VDD; output driving low 25
Ω
Short Circuit Source Current * I
OSH
VO = 0V; shorted for 30s, max. -55 mA
Short Circuit Sink Current * I
OSL
VO = 5V; shorted for 30s, max. 55 mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 5V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data
and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
PARAMETER SYMBOL CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN. TYP. MAX. UNITS
Overall
VCXO Stabilization Time * t
VCXOSTB
From power valid 10 ms
PLL Stabilization Time * t
PLLSTB
From VCXO stable 500 us
Output Frequency Synthesis Error (unless otherwise noted in Frequency Table) 0 ppm
Clock Output (CLK)
Duty Cycle *
Ratio of high pulse width (as measured from rising edge
to next falling edge at V
DD
/2) to one clock period
45 55 %
Jitter, Period (peak-peak) *
t
j(∆P)
From rising edge to next rising edge at
V
DD
/2, CL = 10pF
300 ps
Jitter, Long Term (σy(τ)) *
t
j(LT)
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
150 ps
Rise Time * t
r
VDD = 5V; VO = 0.5V to 4.5V; CL = 10pF ns
Fall Time * t
f
VDD = 5V; VO = 4.5V to 0.5V; CL = 10pF ns