Datasheet FQP2P25 Datasheet (Fairchild Semiconductor)

Page 1
April 2000

 


!!!!
!!!!
!!!!

 


!!!!
!!!!
!!!!
FQP2P25
FQP2P25
General Description
These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters.
G
D
S
TO-220
FQP Series
Features
• -2.3A, -250V, R
• Low gate charge ( typical 6.5 nC)
• Low Crss ( typical 6.5 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
= 4.0Ω @VGS = -10 V
DS(on)
S
G
D
QFET
QFET
QFETQFET
TM
Absolute Maximum Ratings
TC = 25°C unless otherwise noted
Symbol Parameter FQP2P25 Units
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt P
D
Drain-Source Voltage -250 V Drain Current
- Continuous (T
- Continuous (T Drain Current - Pulsed Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Power Dissipation (TC = 25°C)
= 25°C)
C
= 100°C)
C
(Note 1)
(Note 2) (Note 1) (Note 1) (Note 3)
-2.3 A
-1.45 A
-9.2 A
±
30 V
120 mJ
-2.3 A
5.2 mJ
-5.5 V/ns 52 W
- Derate above 25°C 0.42 W/°C
T
, T
J
STG
T
L
Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes, 1/8 from case for 5 seconds
300 °C
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θ
JC
R
θ
CS
R
θ
JA
Thermal Resistance, Junction-to-Case -- 2.4 °CW Thermal Resistance, Case-to-Sink 0.5 -- °CW Thermal Resistance, Junction-to-Ambient -- 62.5 °CW
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Page 2
FQP2P25
Electrical Characteristics

TC = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
BV / ∆T I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
DSS
Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
= 0 V, ID = -250 µA
V
GS
= -250 µA, Referenced to 25°C
I
D
V
= -250 V, VGS = 0 V
DS
V
= -200 V, TC = 125°C
DS
= -30 V, VDS = 0 V
V
GS
V
= 30 V, VDS = 0 V
GS
-250 -- -- V
-- -0.2 -- V/°C
-- -- -1
-- -- -10
-- -- -100 nA
-- -- 100 nA
On Characteristics
V R
g
FS
GS(th)
DS(on)
Gate Threshold Voltage Static Drain-Source
On-Resistance Forward Transconductance
= VGS, ID = -250 µA
V
DS
= -10 V, ID = -1.15 A
V
GS
= -40 V, ID = -1.15 A
V
DS
(Note 4)
-3.0 -- -5.0 V
-- 3.15 4.0
-- 1.2 -- S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance -- 40 55 pF Reverse Transfer Capacitance -- 6.5 8.5 pF
= -25 V, VGS = 0 V,
V
DS
f = 1.0 MHz
-- 190 250 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q
g gs gd
Turn-On Delay Time Turn-On Rise Time -- 40 90 ns Turn-Off Delay Time -- 12 35 ns Turn-Off Fall Time -- 25 60 n s Total Gate Charge Gate-Source Charge -- 1.8 -- nC Gate-Drain Charge -- 3.0 -- nC
= -125 V, ID = -2.3 A,
V
DD
= 25
R
G
V
= -200 V, ID = -2.3 A,
DS
V
GS
= -10 V
(Note 4, 5)
(Note 4, 5)
-- 8.5 25 ns
-- 6.5 8.5 nC
µ
A
µ
A
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 36mH, I
3. ISD  -2.3A, di/dt  300A/µs, VDD  BV
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Maximum Continuous Drain-Source Diode Forward Current -- -- -2.3 A Maximum Pulsed Drain-Source Diode Forward Current -- -- -9.2 A
= 0 V, IS = -2.3 A
Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 0.4 --
= -2.3A, VDD = -50V, RG = 25
AS
Ω,
Starting TJ = 25°C
Starting TJ = 25°C
DSS,
V
GS
= 0 V, IS = -2.3 A,
V
GS
/ dt = 100 A/µs
dI
F
(Note 4)
-- -- -5.0 V
-- 110 -- ns
µ
Rev. A, April 2000
C
Page 3
Typical Characteristics
FQP2P25
10
, Dra in Curre nt [A]
D
-1
-I
10
V Top : -1 5 .0 V
-10.0 V
-8.0 V
-7.0 V
-6.5 V
-6.0 V Bottom : -5.5 V
0
-1
10
GS
-VDS, Drain-Source Voltage [V]
0
Note s :
1. 250s Pulse Test
2. T
= 25
C
0
10
1
10
10
, Drain Current [A]
D
-I
-1
10
246810
-VGS , Gate-Source Voltage [V]
150
25
-55
Notes :
= -40V
1. V
DS
2. 250s Pulse Test
Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s
15
12
VGS = - 10V
],
9
[
DS(on)
R
6
Drain-Source On-Resistance
3
0
0.0 1.5 3.0 4.5 6.0
VGS = - 20V
Note : T
-ID , Drai n Curren t [A]
0
= 25
J
10
150
, Reverse Drain Current [A]
DR
-I
-1
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
-VSD , Source-Drain Voltage [V]
25
Note s :
= 0V
1. V
GS
2. 250s Pulse Test
Figure 3. On-Resistance Variati on vs.
Drain Current and Gate Voltage
400
300
200
Capacitance [pF]
100
0
-1
10
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
C C C
C
iss
C
oss
C
rss
0
10
-VDS, Drain-Source Voltage [V]
= Cgs + Cgd (Cds = shorted)
iss
= Cds + C
oss
gd
= C
rss
gd
Note s :
1. V
2. f = 1 MHz
1
10
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
VDS = -50V
VDS = -125V
VDS = -200V
= -2.3 A
Note : I
D
Rev. A, April 2000
12
10
8
= 0 V
GS
6
4
, Gate-Source Voltage [V]
GS
2
-V
0
01234567
QG, Total Gate C h arg e [nC]
Page 4
FQP2P25
Typical Characteristics
1.2
1.1
1.0
, (N o r ma lize d )
DSS
-BV
0.9
Drain-Source Breakdown V oltage
0.8
-100 -50 0 50 100 150 200
TJ, Junction Tem perature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
1
10
0
10
, Drain C u rren t [A ]
D
-1
-I
10
-2
10
0
10
-VDS, Drain-Source Voltage [V]
Operation in This Area is Limited by R
DS(on)
Notes :
1. T
= 25 oC
C
2. T
= 150 oC
J
3. Single Pulse
1
10
(Continued)
No tes :
1. V
2. I
1 ms
10 ms
DC
2
10
= 0 V
GS
= -250 A
D
100 µs
2.5
2.0
1.5
, (Normalized)
1.0
DS(ON)
R
0.5
Drain-Source On-Resistance
0.0
-100 -50 0 50 100 150 200
Notes :
= -10 V
1. V
GS
= -1.15 A
2. I
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Variation
vs. Temperature
2.5
2.0
1.5
1.0
, Drain Current [A]
D
-I
0.5
0.0 25 50 75 100 125 150
TC, Case Temperature []
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
©2000 Fairchild Semiconductor International
vs. Case Temperature
D=0.5
0
10
0.2
0.1
0.05
-1
10
0.02
0.01
(t), Therm al Response
JC
Z
-2
10
-5
10
single pulse
-4
10
-3
10
-2
10
N o te s :
(t) = 2.4 /W M ax.
1. Z
JC
2. D u ty F a c to r , D = t
3. TJM - TC = PDM * Z
P
DM
t
1
t
2
-1
10
10
1/t2
(t)
JC
0
1
10
t1, S q u a re W a v e P u lse D ura tio n [s e c]
Figure 11. Transient Thermal Response Cur ve
Rev. A, April 2000
Page 5
Gate Charge Test Circuit & Waveform
FQP2P25
V
V
GS
DS
DS
GS
-10V
-10V
V
V
GS
GS
10%
10%
Q
Q
gs
gs
t
t
t
t
d(on)tr
d(on)tr
Q
Q
g
g
Q
Q
gd
gd
Charge
Charge
t
on
on
t
off
off
t
t
d(off )
d(off )
t
t
f
f
12V
12V
200nF
200nF
-3mA
-3mA
Same Type
50K
50K
300nF
300nF
V
V
GS
GS
Same Type
as DUT
as DUT
DUT
DUT
V
V
Resistive Switching Test Circuit & Waveforms
R
R
L
V
V
DS
DS
V
V
GS
GS
R
R
G
G
L
V
V
DD
DD
-10V
-10V
-10V
-10V
DUT
DUT
90%
90%
V
V
DS
DS
Unclamped Inductive Switching Test Circuit & Waveforms
BV
BV
DSS
L
V
LL
V
DS
DS
I
IDI
D
D
V
V
DD
BV
BV
DD
I
I
AS
AS
DSS
DSS
R
R
G
G
DUT
DUT
t
t
p
p
V
V
DD
DD
1
1
1
1
----
----
----
----
E
E
=LI
E
=LI
=LI
AS
AS
AS
2
2
2
2
2
2
2
AS
AS
AS
t
t
p
p
(t)
(t)
I
I
D
D
DSS
--------------------
-------------------­BV
BV
DSS-VDD
DSS-VDD
Time
Time
V
(t)
V
(t)
DS
DS
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Page 6
Peak Diode Recovery dv /d t Test Circuit & Waveforms
+
+
V
V
DS
DS
DUT
DUT
I
I
SD
SD
Driver
Driver
R
R
G
G
V
V
GS
GS
_
_
L
LL
Compliment of DUT
Compliment of DUT
(N-Channel)
(N-Channel)
• dv/dt controlled by R
• dv/dt controlled by R
•ISDcontrolled by pulse period
•ISDcontrolled by pulse period
G
G
FQP2P25
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
Body Diode Reverse Current
Body Diode Reverse Current
I
I
RM
RM
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
V
V
SD
SD
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
Body Diode Recoverydv/dt
Body Diode Recoverydv/dt
di/dt
di/dt
10V
10V
V
V
DD
DD
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Page 7
Package Dimensions
FQP2P25
9.90 ±0.20
TO-220
4.50 ±0.20
(8.70)
+0.10
1.30
–0.05
(1.70)
1.30 ±0.10
ø3.60 ±0.10
2.80 ±0.1015.90 ±0.20
(3.70)(3.00)
18.95MAX.
9.20 ±0.2013.08 ±0.20 (1.46)
(45°)
(1.00)
1.27 ±0.10
2.54TYP
±0.20]
[2.54
10.00 ±0.20
1.52 ±0.10
0.80 ±0.10
2.54TYP
±0.20]
[2.54
10.08 ±0.30
0.50
+0.10 –0.05
2.40 ±0.20
©2000 Fairchild Semiconductor International
Rev. A, April 2000
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™
2
E
CMOS™
FACT™ FACT Quiet Series™
®
FAST FASTr™ GTO™
HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench
®
QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6
SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
Preliminary First Production This datasheet contains preliminary data, and
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Obsolete Not In Production This datasheet contains specifications on a product
©2000 Fairchild Semiconductor International Rev. A, January 2000
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Semiconductor reserves the right to make changes at any time without notice in order to improve design.
that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only .
Loading...