Datasheet FM27C040V90, FM27C040V150, FM27C040V120, FM27C040QE150, FM27C040QE120 Datasheet (Fairchild Semiconductor)

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Page 1

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

January 2000

General Description

The FM27C040 is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is organized as 512K words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through 8 Mbit EPROMs. The “Don’t Care” feature on VPP during read operations allows memory expansions from 1M to 8 Mbits with no printed circuit board changes.

The FM27C040 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 120ns access time provides high speed operation with high-performance CPUs. The FM27C040 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently used software routines are quickly executed from EPROM storage, greatly enhancing system utility.

The FM27C040 is manufactured using Fairchild’s advanced CMOS AMG™ EPROM technology.

Block Diagram

GND

CE/PGM

Output Enable,

Chip Enable, and

Program Logic

Features

■ High performance CMOS —120, 150ns access time*

■ Simplified upgrade path —VPP is a “Don’t Care” during normal read operation

■ Manufacturer’s identification code

■ JEDEC standard pin configuration

—32-pin PDIP —32-pin PLCC —32-pin CERDIP

*Note: New revision meets 70ns. Please check with factory for availability.

Data Outputs O0 - O

Output Buffers

A0 - A Address

Inputs

AMG™ is a trademark of WSI, Inc.

. . . . . . . . .

Y Gating

4,194,304-Bit

Cell Matrix

DS800033-1

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Y Decoder

X Decoder

Page 2

Connection Diagrams

27C010

XX/V

GND

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C040 pin.

XX/V

GND

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE A

CE/PGM O

27C010FM27C040

XX/PGM

CE O

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

DS800033-2

Commercial Temperature Range (0°C to +70°C) VCC = 5V ±10%

Parameter/Order Number Access Time (ns)

FM27C040 Q, N, V 90 90

FM27C040 Q, N, V 120 120

FM27C040 Q, N, V 150 150

• All versions are guaranteed to function for slower speeds.

Pin Names

A0–A18 Addresses

CE/PGM Chip Enable/Program

OE Output Enable

O0–O7 Outputs

XX Don’t Care (During Read)

Extended Temperature Range (-40°C to +85°C) VCC = 5V ±10%

Parameter/Order Number Access Time (ns)

FM27C040 QE, NE, VE 90 90

FM27C040 QE, NE, VE 120 120

FM27C040 QE, NE, VE 150 150

Package Types: FM27C040 Q, N,V XXX Q = Quartz-Windowed Ceramic DIP N = Plastic DIP V = PLCC

• All packages conform to the JEDEC standard.

FM27C040 Rev. A

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FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Absolute Maximum Ratings (Note 1)

All Output Voltages with

Respect to Ground VCC +1.0V to GND - 0.6V

Storage Temperature -65°C to +150°C

All Input Voltages except A9 with

Respect to Ground -0.6V to +7V

VPP and A9 with Respect to Ground -0.6V to +14V

Supply Voltage with

Respect to Ground -0.6V to +7V

Operating Range

Range Temperature V

Commercial 0°C to +70°C +5V ±10%

Industrial -40°C to +85°C +5V ±10%

Tolerance

ESD Protection >2000V

Read Operation

DC Electrical Characteristics

Symbol Parameter Test Conditions Min Max Units

SB1

SB2

Input Low Level -0.5 0.8 V

Input High Level 2.0 VCC +1 V

Output Low Voltage IOL = 2.1 mA 0.4 V

Output High Voltage IOH = -2.5 mA 3.5 V

VCC Standby Current (CMOS) CE = VCC ± 0.3V 100 µA

VCC Standby Current CE = V

VCC Active Current CE = OE = VIL, f=5 MHz 30 mA

VPP Supply Current VPP = V

VPP Read Voltage VCC - 0.4 V

Input Load Current VIN = 5.5V or GND -1 1 µA

Output Leakage Current V

Over operating range with VPP = V

I/O = 0 mA

= 5.5V or GND -10 10 µA

OUT

1mA

10 µA

AC Electrical Characteristics Over operating range with V

= V

Symbol Parameter 120 150 Units

Min Max Min Max

ACC

(Note 2) Output Float

(Note 2) Whichever Occurred First

Capacitance T

Address to Output Delay 120 150

CE to Output Delay 120 150

OE to Output Delay 50 50

Output Disable to 45 55 ns

Output Hold from Addresses CE or OE , 0 0

= +25°C, f = 1 MHz (Note 2)

Symbol Parameter Conditions Typ Max Units

OUT

Input Capacitance VIN = 0V 9 15 pF

Output Capacitance V

= 0V 12 15 pF

OUT

FM27C040 Rev. A

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Page 4

AC Test Conditions

Output Load 1 TTL Gate and CL = 100 pF (Note 8)

Input Rise and Fall Times ≤5 ns

Input Pulse Levels 0.45V to 2.4V

Timing Measurement Reference Level (Note 10)

Inputs 0.8V and 2V Outputs` 0.8V and 2V

AC Waveforms (Notes 6, 7, 9)

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

ADDRESSES

OUTPUT

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to t Note 4: The tDF and tCF compare level is determined as follows:

High to TRI-STATE®, the measured V Low to TRI-STATE, the measured V

Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device

between VCC and GND.

Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 µA.

CL: 100 pF includes fixture capacitance.

Note 9: VPP may be connected to VCC except during programming. Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

0.8V

Hi-Z

(Note 3)

- tOE after the falling edge of CE without impacting t

ACC

(DC) - 0.10V;

OH1

(DC) + 0.10V.

OL1

ACC

Addresses Valid

(Note 3)

ACC

Valid Output

(Note 4, 5)

Hi-Z

DS800033-4

FM27C040 Rev. A

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Page 5

Programming Waveform (Note 13)

DATA

0.8V

6.25V

12.75V

ADDRESSES

VCS

VPS

Program

Address N

Data In Stable

ADD N

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Program

Verify

Hi-Z

Data Out Valid

ADD N

0.8V

OES

DS800033-5

CE/PGM

Programming Characteristics (Notes 11, 12, 13, 14)

Symbol Parameter Conditions Min Typ Max Units

OES

VPS

VCS

OUT

Address Setup Time 1 µs

OE Setup Time 1 µs

Data Setup Time 1 µs

VPP Setup Time 1 µs

VCC Setup Time 1 µs

Address Hold Time 0 µs

Data Hold Time 1 µs

Output Enable to Output Float Delay CE/PGM = X 0 60 ns

Program Pulse Width 45 50 105 µs

Data Valid from OE CE/PGM = X 100 ns

VPP Supply Current during CE/PGM = V Programming Pulse

30 mA

VCC Supply Current 30 mA

Temperature Ambient 20 25 30 °C

Power Supply Voltage 6.25 6.5 6.75 V

Programming Supply Voltage 12.5 12.75 13.0 V

Input Rise, Fall Time 5 ns

Input Low Voltage -0.1 0.0 0.45 V

Input High Voltage 2.4 4.0 V

Input Timing Reference Voltage 0.8 2.0 V

Output Timing Reference Voltage 0.8 2.0 V

Note 11: Fairchild’s standard product warranty applies only to devices programmed to specifications described herein. Note 12: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with

voltage applied to VPP or VCC. Note 13: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to

prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across VPP, VCC to GND to suppress spurious voltage transients which may damage the device.

Note 14: During power up the CE/PGM pin must be brought high (≥VIH) either coincident with or before power is applied to VPP.

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FM27C040 Rev. A

Page 6

Turbo Programming Algorithm Flow Chart

VCC = 6.5V VPP = 12.75V

n = 0

ADDRESS = FIRST LOCATION

PROGRAM ONE 50µs PULSE

INCREMENT n

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

DEVICE

FAILED

YES

n = 10?

INCREMENT

ADDRESS

FAIL

VERIFY

BYTE

PAS S

LAST

ADDRESS

YES

ADDRESS = FIRST LOCATION

VERIFY

FAIL

BYTE

PAS S

LAST

ADDRESS

YES

INCREMENT

ADDRESS

n = 0

PROGRAM ONE

50 µs

PULSE

CHECK ALL BYTES

= VPP = 6.0V

1ST: V

2ND: V

Note: The standard National Semiconductor algorithm may also be used with it will have longer programming time.

= VPP = 4.3V

FIGURE 1.

FM27C040 Rev. A

DS800033-6

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FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are V supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The V must be at 6.25V during the three programming modes, and at 5V in the other three modes.

Read Mode

The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (t available at the outputs tOE after the falling edge of OE, assuming that CE/PGM has been low and addresses have been stable for at least t

) is equal to the delay from CE to output (tCE). Data is

ACC

-tOE.

ACC

Standby Mode

The EPROM has a standby mode which reduces the active power dissipation by over 99%, from of 65 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE).

Output OR-Typing

Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for:

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended

that CE/PGM be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.

Programming

CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM.

Initially, and after each erasure, all bits of the EPROM are in the “1’s” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure.

The EPROM is in the programming mode when the VPP power

and VPP. The VPP power

power supply

supply is at 12.75V and OE is at VIH. It is required that at least a

0.1 µF capacitor be placed across V

spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.

When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.)

The EPROM must not be programmed with a DC signal applied to the CE/PGM input.

Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the pro-gramming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM.

, VCC to ground to suppress

Program Inhibit

Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like in-puts (including OE) of the parallel EPROMs may be com-mon. A TTL low level program pulse applied to an EPROM’s CE/PGM input with VPP at 12.75V will program that EPROM. A TTL high level CE/ PGM input inhibits the other EPROMs from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 12.75V. VPP must be at VCC, except during programming and program verify.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code.

The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for FM27C040 is “8F08”, where “8F” designates that it is made by Fairchild Semiconductor, and “08” designates a 4 Megabit (512K x 8) part.

The code is accessed by applying 12V ±0.5V to address pin A9. Addresses A1–A8, A10–A18, and all control pins are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the eight data pins, O0 –O7 . Proper code access is only guaranteed at 25°C ± 5°C.

FM27C040 Rev. A

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Page 8

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Functional Description (Continued)

ERASURE CHARACTERISTICS

The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Å–4000Å range.

The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Å. The integrated dose (i.e., UV intensity X exposure time) for erasure should be minimum of 15W-sec/cm2.

The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure.

An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increase as the square of the distance from the lamp. (If distance is doubled the erasure time increases by factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should

be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.

SYSTEM CONSIDERATION

The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, I segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance loading of the device. The associated V transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between V GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.

, has three

and

Mode Selection

The modes of operation of the FM27C040 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature.

TABLE 1. Modes Selection

Pins CE/PGM OE V

Mode

Read V

Output Disable X V

Standby V

Programming V

Program Verify X V

Program Inhibit V

Note 15: X can be VIL or V

X 5.0V D

(Note 15)

X 5.0V High Z

X X 5.0V High Z

12.75V 6.25V D

12.75V 6.25V High Z

TABLE 2. Manufacturer’s Identification Code

Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex

(12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data

Manufacturer Code

Device Code V

12V100011118F

12V0000100008

Outputs

OUT

FM27C040 Rev. A

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Page 9

Physical Dimensions inches (millimeters) unless otherwise noted

1.660 MAX

R 0.025

0.585 MAX

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

0.225 MAX TYP

0.125 MIN TYP

R 0.030-0.055

TYP

0.005 MIN TYP

0.060-0.100 TYP

Glass Sealant

86°-94°

TYP

0.175 MAX

0.150 MIN TYP

0.10

MAX

0.015 -0.060 TYP

0.090-0.110 TYP

UV WINDOW SIZE AND CONFIGURATION DETERMINED BY DEVICE SIZE

0.050-0.060 TYP

0.015-0.021 TYP

32-Lead EPROM Ceramic Dual-In-Line Package (Q)

Order Number FM27C040QXXX

Package Number J32AQ

90° - 100°

TYP

0.685

0.590-0.620

0.008-0.012

+0.025

-0.060

TYP

FM27C040 Rev. A

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Page 10

Physical Dimensions inches (millimeters) unless otherwise noted

0.485-0.495

0.000-0.010

Polished Optional

0.549-0.553

[13.94-14.05]

0.585-0.595

[14.86-15.11]

0.007[0.18]

0.045

[1.143]

[0.00-0.25]

-B-

-F-

0.002[0.05]

0.007[0.18]

F-G

0.007[0.18]

[12.32-12.57]

0.449-0.453

[11.40-11.51]

0.002[0.05]

F-G

D-E

-A-

D-E

-D-

-G-

0.050

2014

-E-

0.106-0.112 [2.69-2.84]

0.023-0.029 [0.58-0.74]

0.541-0.545

[13.74-13-84]

See detail A

0.123-0.140 [3.12-3.56]

60°

-H-

-J-

0.004[0.10]

-C-

Base Plane

0.015 [0.38]

0.400

( )

[10.16]

0.013-0.021 [0.33-0.53]

0.078-0.095 [1.98-2.41]

Min Typ

0.015[0.38]

TYP

0.007[0.18]

0.490-0530

[12.45-13.46]

C D-E, F-G

0.020 [0.51]

D-E, F-G

0.005 [0.13]

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

Max

0.0100 [0.254]

0.118-0.129 [3.00-3.28]

0.010[0.25]

0.026-0.032 [0.66-0.81]

0.007[0.18]

0.045

B A

D-E, F-G

°X

0.042-0.048 [1.07-1.22]

0.025 [0.64]

Min

0.006-0.012 [0.15-0.30]

0.019-0.025 [0.48-0.64]

Typ

0.025 Min

[0.64]

0.021-0.027 [0.53-0.69]

0.027-0.033 [0.69-0.84]

Section B-B

0.065-0.071 [1.65-1.80]

0.053-0.059 [1.65-1.80]

0.031-0.037 [0.79-0.94]

[1.14]

Detail A

Typical

Rotated 90°

0.030-0.040

[0.76-1.02]

Typical

32-Lead PLCC Package (V)

Order Number FM27C040VXXX

Package Number VA32A

FM27C040 Rev. A

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Page 11

Physical Dimensions inches (millimeters) unless otherwise noted

1.64 – 1.66

(41.66 – 42.164)

0.062

(1.575)

RAD

TYP

0.490 – 0.550

(12.446 – 13.97)

FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM

0.600 – 0.620

(15.240 – 15.748)

90°–105°

0.580

(14.73)

MIN

0.008 - 0.015

(0.203 – 0.381)

0.040 - 0.090

(1.016 – 2.286)

Pin No. 1 IDENT

0.050

(1.270)

TYP

0.100 ±0.010

(2.540 ±0.254)

0.035 – 0.07

(0.889 – 1.778)

0.018 ±0.003

(0.457 ±0.078)

32-Lead PDIP Package

Order Number FM27C040NXXX

0.125 – 0.165

(3.175 – 4.191)

86°- 94°

TYP

(3.683 – 5.334)

0.015

(0.381)

0.120 – 0.150 (3.048 – 3.81)

0.145 – 0.210

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Americas Europe Hong Kong Japan Ltd. Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.

Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

FM27C040 Rev. A

English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan Français Tel: +33 (0) 1-6930-3696 Tel; +852-2722-8338 Tel: 81-3-3818-8840 Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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